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x86: Refactor interrupt_init()

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Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to
i8259_init() and create a new interrupt_init() in
arch/x86/cpu/interrupt.c to call i8259_init() followed by a
call to cpu_init_interrupts().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2014-11-20 16:11:16 +08:00 committed by Simon Glass
parent a549f7497b
commit 1dae2e0eb6
3 changed files with 23 additions and 14 deletions
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26
arch/x86/cpu/interrupts.c
View file

@ -20,6 +20,7 @@
#include <linux/compiler.h>
#include <asm/msr.h>
#include <asm/u-boot-x86.h>
#include <asm/i8259.h>
DECLARE_GLOBAL_DATA_PTR;
@ -128,9 +129,6 @@ int cpu_init_interrupts(void)
int irq_entry_size = irq_1 - irq_0;
void *irq_entry = (void *)irq_0;
/* Just in case... */
disable_interrupts();
/* Setup the IDT */
for (i = 0; i < 256; i++) {
idt[i].access = 0x8e;
@ -146,9 +144,6 @@ int cpu_init_interrupts(void)
load_idt(&idt_ptr);
/* It is now safe to enable interrupts */
enable_interrupts();
return 0;
}
@ -172,6 +167,25 @@ int disable_interrupts(void)
return flags & X86_EFLAGS_IF;
}
int interrupt_init(void)
{
/* Just in case... */
disable_interrupts();
#ifdef CONFIG_SYS_PCAT_INTERRUPTS
/* Initialize the master/slave i8259 pic */
i8259_init();
#endif
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts();
/* It is now safe to enable interrupts */
enable_interrupts();
return 0;
}
/* IRQ Low-Level Service Routine */
void irq_llsr(struct irq_regs *regs)
{

2
arch/x86/include/asm/i8259.h
View file

@ -69,4 +69,6 @@
#define ICW4_AEOI 0x02 /* Automatic EOI Mode */
#define ICW4_PM 0x01 /* Microprocessor Mode */
int i8259_init(void);
#endif

9
arch/x86/lib/pcat_interrupts.c
View file

@ -24,12 +24,10 @@
#error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined"
#endif
int interrupt_init(void)
int i8259_init(void)
{
u8 i;
disable_interrupts();
/* Mask all interrupts */
outb(0xff, MASTER_PIC + IMR);
outb(0xff, SLAVE_PIC + IMR);
@ -65,11 +63,6 @@ int interrupt_init(void)
/* Interrupt 9 should be level triggered (SCI). The OS might do this */
configure_irq_trigger(9, true);
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts();
enable_interrupts();
return 0;
}