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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

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This commit is contained in:
Tom Rini 2015-01-22 11:24:11 -05:00
commit 032c6867a2
12 changed files with 128 additions and 1126 deletions
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26
arch/arm/cpu/armv7/uniphier/init_page_table.S Normal file
View file

@ -0,0 +1,26 @@
#include <config.h>
#include <linux/linkage.h>
/* page table */
#define NR_SECTIONS 4096
#define SECTION_SHIFT 20
#define DEVICE 0x00002002 /* Non-shareable Device */
#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT))
.section ".rodata"
.align 14
ENTRY(init_page_table)
section = 0
.rept NR_SECTIONS
.if section == TEXT_SECTION || section == STACK_SECTION
attr = NORMAL
.else
attr = DEVICE
.endif
.word (section << SECTION_SHIFT) | attr
section = section + 1
.endr
END(init_page_table)

1069
arch/arm/cpu/armv7/uniphier/init_page_table.c
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File diff suppressed because it is too large Load diff

6
arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
View file

@ -11,7 +11,7 @@
#undef DPLL_SSC_RATE_1PER
void dpll_init(void)
static void dpll_init(void)
{
u32 tmp;
@ -42,7 +42,7 @@ void dpll_init(void)
writel(tmp, SC_DPLLCTRL2);
}
void upll_init(void)
static void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
@ -82,7 +82,7 @@ void upll_init(void)
writel(tmp, SC_UPLLCTRL);
}
void vpll_init(void)
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;

2
arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
View file

@ -21,7 +21,7 @@ void sg_init(void)
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled deasserting reset of cores */
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);

8
arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
View file

@ -9,7 +9,7 @@
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
@ -43,8 +43,8 @@ static inline void umc_start_ssif(void __iomem *ssif_base)
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
if (freq == 1333) {
writel(0x45990b11, dramcont + UMC_CMDCTLA);
@ -119,7 +119,7 @@ void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
static int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);

6
arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
View file

@ -11,7 +11,7 @@
#undef DPLL_SSC_RATE_1PER
void dpll_init(void)
static void dpll_init(void)
{
u32 tmp;
@ -46,7 +46,7 @@ void dpll_init(void)
writel(tmp, SC_DPLLCTRL2);
}
void stop_mpll(void)
static void stop_mpll(void)
{
u32 tmp;
@ -62,7 +62,7 @@ void stop_mpll(void)
;
}
void vpll_init(void)
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;

4
arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
View file

@ -21,8 +21,8 @@ void sg_init(void)
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled deasserting reset of cores */
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
tmp |= 1 << 6;
writel(tmp, SG_IECTRL);
}

8
arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
View file

@ -9,7 +9,7 @@
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000001, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
@ -52,8 +52,8 @@ static inline void umc_start_ssif(void __iomem *ssif_base)
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
@ -88,7 +88,7 @@ void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
static int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);

6
arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
View file

@ -9,7 +9,7 @@
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
void dpll_init(void)
static void dpll_init(void)
{
u32 tmp;
/*
@ -54,7 +54,7 @@ void dpll_init(void)
writel(tmp, SC_DPLLCTRL2);
}
void upll_init(void)
static void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
@ -94,7 +94,7 @@ void upll_init(void)
writel(tmp, SC_UPLLCTRL);
}
void vpll_init(void)
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;

8
arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
View file

@ -9,7 +9,7 @@
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
@ -43,8 +43,8 @@ static inline void umc_start_ssif(void __iomem *ssif_base)
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
#ifdef CONFIG_DDR_STANDARD
writel(0x55990b11, dramcont + UMC_CMDCTLA);
@ -99,7 +99,7 @@ void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
static int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);

2
arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
View file

@ -72,7 +72,7 @@ struct ddrphy {
u32 gtr; /* General Timing Register */
u32 rsv[3]; /* Reserved */
} dx[9];
} __packed;
};
#endif /* __ASSEMBLY__ */

109
arch/arm/include/asm/arch-uniphier/sg-regs.h
View file

@ -25,22 +25,29 @@
/* Memory Configuration */
#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
#define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0))
#define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0))
#define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
#define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2))
#define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2))
#define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
/* Pin Control */
@ -101,6 +108,7 @@
#else
#include <linux/types.h>
#include <linux/sizes.h>
#include <asm/io.h>
static inline void sg_set_pinsel(int n, int value)
@ -111,24 +119,24 @@ static inline void sg_set_pinsel(int n, int value)
static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
{
int size_mb = (size >> 20) / num;
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case 64:
ret = SG_MEMCONF_CH0_SIZE_64MB;
case SZ_64M:
ret = SG_MEMCONF_CH0_SZ_64M;
break;
case 128:
ret = SG_MEMCONF_CH0_SIZE_128MB;
case SZ_128M:
ret = SG_MEMCONF_CH0_SZ_128M;
break;
case 256:
ret = SG_MEMCONF_CH0_SIZE_256MB;
case SZ_256M:
ret = SG_MEMCONF_CH0_SZ_256M;
break;
case 512:
ret = SG_MEMCONF_CH0_SIZE_512MB;
case SZ_512M:
ret = SG_MEMCONF_CH0_SZ_512M;
break;
case 1024:
ret = SG_MEMCONF_CH0_SIZE_1024MB;
case SZ_1G:
ret = SG_MEMCONF_CH0_SZ_1G;
break;
default:
BUG();
@ -151,24 +159,24 @@ static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
{
int size_mb = (size >> 20) / num;
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case 64:
ret = SG_MEMCONF_CH1_SIZE_64MB;
case SZ_64M:
ret = SG_MEMCONF_CH1_SZ_64M;
break;
case 128:
ret = SG_MEMCONF_CH1_SIZE_128MB;
case SZ_128M:
ret = SG_MEMCONF_CH1_SZ_128M;
break;
case 256:
ret = SG_MEMCONF_CH1_SIZE_256MB;
case SZ_256M:
ret = SG_MEMCONF_CH1_SZ_256M;
break;
case 512:
ret = SG_MEMCONF_CH1_SIZE_512MB;
case SZ_512M:
ret = SG_MEMCONF_CH1_SZ_512M;
break;
case 1024:
ret = SG_MEMCONF_CH1_SIZE_1024MB;
case SZ_1G:
ret = SG_MEMCONF_CH1_SZ_1G;
break;
default:
BUG();
@ -188,6 +196,43 @@ static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
}
return ret;
}
static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH2_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH2_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH2_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH2_SZ_512M;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH2_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH2_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
#endif /* __ASSEMBLY__ */
#endif /* ARCH_SG_REGS_H */