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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

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This commit is contained in:
Tom Rini 2015-02-10 10:40:43 -05:00
commit 307367eaff
62 changed files with 2864 additions and 330 deletions
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13
arch/arm/Kconfig
View file

@ -646,6 +646,7 @@ config TARGET_MX6SLEVK
config TARGET_MX6SXSABRESD
bool "Support mx6sxsabresd"
select CPU_V7
select SUPPORT_SPL
config TARGET_GW_VENTANA
bool "Support gw_ventana"
@ -672,6 +673,17 @@ config TARGET_TQMA6
config TARGET_OT1200
bool "Bachmann OT1200"
select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_PICON
bool "Support platinum-picon"
select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_TITANIUM
bool "Support platinum-titanium"
select CPU_V7
select SUPPORT_SPL
config OMAP34XX
bool "OMAP34XX SoC"
@ -887,6 +899,7 @@ source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
source "board/bachmann/ot1200/Kconfig"
source "board/balloon3/Kconfig"
source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
source "board/bluewater/snapper9260/Kconfig"

6
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
View file

@ -147,6 +147,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
mxs_spl_console_init();
debug("SPL: Serial Console Initialised\n");
mxs_power_init();
@ -156,6 +157,11 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
data->boot_mode_idx = bootmode;
mxs_power_wait_pswitch();
if (mxs_boot_modes[data->boot_mode_idx].boot_pads == MXS_BM_JTAG) {
debug("SPL: Waiting for JTAG user\n");
asm volatile ("x: b x");
}
}
/* Support aparatus */

13
arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
View file

@ -18,6 +18,8 @@ void mxs_lradc_init(void)
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
debug("SPL: Initialisating LRADC\n");
writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
@ -37,9 +39,15 @@ void mxs_lradc_enable_batt_measurement(void)
{
struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
debug("SPL: Enabling LRADC battery measurement\n");
/* Check if the channel is present at all. */
if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) {
debug("SPL: LRADC channel 7 is not present - aborting\n");
return;
}
debug("SPL: LRADC channel 7 is present - configuring\n");
writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
@ -65,6 +73,7 @@ void mxs_lradc_enable_batt_measurement(void)
100, &regs->hw_lradc_delay3);
writel(0xffffffff, &regs->hw_lradc_ch7_clr);
writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
debug("SPL: LRADC channel 7 configuration complete\n");
}

18
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
View file

@ -92,6 +92,7 @@ static uint32_t dram_vals[] = {
__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
{
debug("SPL: Using default SDRAM parameters\n");
}
#ifdef CONFIG_MX28
@ -99,8 +100,10 @@ static void initialize_dram_values(void)
{
int i;
debug("SPL: Setting mx28 board specific SDRAM parameters\n");
mxs_adjust_memory_params(dram_vals);
debug("SPL: Applying SDRAM parameters\n");
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
@ -109,6 +112,7 @@ static void initialize_dram_values(void)
{
int i;
debug("SPL: Setting mx23 board specific SDRAM parameters\n");
mxs_adjust_memory_params(dram_vals);
/*
@ -120,6 +124,7 @@ static void initialize_dram_values(void)
* HW_DRAM_CTL8 is setup as the last element.
* So skip the initialization of these HW_DRAM_CTL registers.
*/
debug("SPL: Applying SDRAM parameters\n");
for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
if (i == 8 || i == 27 || i == 28 || i == 35)
continue;
@ -146,6 +151,8 @@ static void mxs_mem_init_clock(void)
const unsigned char divider = 21;
#endif
debug("SPL: Initialising FRAC0\n");
/* Gate EMI clock */
writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
@ -170,6 +177,7 @@ static void mxs_mem_init_clock(void)
&clkctrl_regs->hw_clkctrl_clkseq_clr);
early_delay(10000);
debug("SPL: FRAC0 Initialised\n");
}
static void mxs_mem_setup_cpu_and_hbus(void)
@ -177,6 +185,8 @@ static void mxs_mem_setup_cpu_and_hbus(void)
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
debug("SPL: Setting CPU and HBUS clock frequencies\n");
/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
* and ungate CPU clock */
writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
@ -209,6 +219,8 @@ static void mxs_mem_setup_vdda(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Configuring VDDA\n");
writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
@ -240,6 +252,8 @@ static void mx23_mem_setup_vddmem(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Setting mx23 VDDMEM\n");
/* We must wait before and after disabling the current limiter! */
early_delay(10000);
@ -252,6 +266,8 @@ static void mx23_mem_setup_vddmem(void)
static void mx23_mem_init(void)
{
debug("SPL: Initialising mx23 SDRAM Controller\n");
/*
* Reset/ungate the EMI block. This is essential, otherwise the system
* suffers from memory instability. This thing is mx23 specific and is
@ -297,6 +313,8 @@ static void mx28_mem_init(void)
struct mxs_pinctrl_regs *pinctrl_regs =
(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
debug("SPL: Initialising mx28 SDRAM Controller\n");
/* Set DDR2 mode */
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);

110
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View file

@ -14,6 +14,13 @@
#include "mxs_init.h"
#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
#else
#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
#endif
/**
* mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
*
@ -26,6 +33,8 @@ static void mxs_power_clock2xtal(void)
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
debug("SPL: Switching CPU clock to 24MHz XTAL\n");
/* Set XTAL as CPU reference clock */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_set);
@ -43,9 +52,23 @@ static void mxs_power_clock2pll(void)
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
debug("SPL: Switching CPU core clock source to PLL\n");
/*
* TODO: Are we really? It looks like we turn on PLL0, but we then
* set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
* set by mxs_power_clock2xtal()). Clearing this bit here seems to
* introduce some instability (causing the CPU core to hang). Maybe
* we aren't giving PLL0 enough time to stabilise?
*/
setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
CLKCTRL_PLL0CTRL0_POWER);
early_delay(100);
/*
* TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
* wait on the PLL0 LOCK bit?
*/
setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
@ -62,6 +85,8 @@ static void mxs_power_set_auto_restart(void)
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
debug("SPL: Setting auto-restart bit\n");
writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
;
@ -101,14 +126,17 @@ static void mxs_power_set_linreg(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Set linear regulator 25mV below switching converter */
debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vddactrl,
POWER_VDDACTRL_LINREG_OFFSET_MASK,
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
@ -127,6 +155,8 @@ static int mxs_get_batt_volt(void)
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
debug("SPL: Battery Voltage = %dmV\n", volt);
return volt;
}
@ -154,8 +184,10 @@ static int mxs_is_batt_good(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = mxs_get_batt_volt();
if ((volt >= 2400) && (volt <= 4300))
if ((volt >= 2400) && (volt <= 4300)) {
debug("SPL: Battery is good\n");
return 1;
}
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
@ -175,16 +207,21 @@ static int mxs_is_batt_good(void)
volt = mxs_get_batt_volt();
if (volt >= 3500)
if (volt >= 3500) {
debug("SPL: Battery Voltage too high\n");
return 0;
}
if (volt >= 2400)
if (volt >= 2400) {
debug("SPL: Battery is good\n");
return 1;
}
writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
&power_regs->hw_power_charge_clr);
writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
debug("SPL: Battery Voltage too low\n");
return 0;
}
@ -203,6 +240,7 @@ static void mxs_power_setup_5v_detect(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
/* Start 5V detection */
debug("SPL: Starting 5V input detection comparator\n");
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK,
POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
@ -220,6 +258,8 @@ static void mxs_src_power_init(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Pre-Configuring power block\n");
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
@ -257,6 +297,8 @@ static void mxs_power_init_4p2_params(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Configuring common 4P2 regulator params\n");
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
@ -268,8 +310,7 @@ static void mxs_power_init_4p2_params(void)
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_DROPOUT_CTRL_MASK,
POWER_DCDC4P2_DROPOUT_CTRL_100MV |
POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
DCDC4P2_DROPOUT_CONFIG);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
@ -289,6 +330,8 @@ static void mxs_enable_4p2_dcdc_input(int xfer)
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_PWDN_5VBRNOUT;
prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
@ -390,6 +433,8 @@ static void mxs_power_init_4p2_regulator(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
debug("SPL: Enabling 4P2 regulator\n");
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
@ -407,6 +452,7 @@ static void mxs_power_init_4p2_regulator(void)
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
debug("SPL: Charging 4P2 capacitor\n");
mxs_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
@ -420,6 +466,8 @@ static void mxs_power_init_4p2_regulator(void)
POWER_DCDC4P2_ENABLE_DCDC);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_set);
debug("SPL: Unable to recover from mx23 errata 5837\n");
hang();
}
@ -433,6 +481,7 @@ static void mxs_power_init_4p2_regulator(void)
* current limit until the brownout status is false or until we've
* reached our maximum defined 4p2 current limit.
*/
debug("SPL: Setting 4P2 brownout level\n");
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK,
22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
@ -479,8 +528,11 @@ static void mxs_power_init_dcdc_4p2_source(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Switching DC-DC converters to 4P2\n");
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
debug("SPL: Already switched - aborting\n");
hang();
}
@ -509,6 +561,8 @@ static void mxs_power_enable_4p2(void)
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
debug("SPL: Powering up 4P2 regulator\n");
vdddctrl = readl(&power_regs->hw_power_vdddctrl);
vddactrl = readl(&power_regs->hw_power_vddactrl);
vddioctrl = readl(&power_regs->hw_power_vddioctrl);
@ -559,6 +613,8 @@ static void mxs_power_enable_4p2(void)
if (tmp)
writel(POWER_CHARGE_ENABLE_LOAD,
&power_regs->hw_power_charge_clr);
debug("SPL: 4P2 regulator powered-up\n");
}
/**
@ -574,6 +630,8 @@ static void mxs_boot_valid_5v(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Booting from 5V supply\n");
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
* disconnect event. FIXME
@ -601,6 +659,9 @@ static void mxs_powerdown(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("Powering Down\n");
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
@ -617,6 +678,8 @@ static void mxs_batt_boot(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Configuring power block to boot from battery\n");
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
@ -672,6 +735,8 @@ static void mxs_handle_5v_conflict(void)
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
debug("SPL: Resolving 5V conflict\n");
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_BO_OFFSET_MASK);
@ -683,19 +748,27 @@ static void mxs_handle_5v_conflict(void)
* VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
* unreliable
*/
debug("SPL: VDDIO has a brownout\n");
mxs_powerdown();
break;
}
if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
mxs_boot_valid_5v();
break;
} else {
debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
mxs_powerdown();
break;
}
/*
* TODO: I can't see this being reached. We'll either
* powerdown or boot from a stable 5V supply.
*/
if (tmp & POWER_STS_PSWITCH_MASK) {
debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
mxs_batt_boot();
break;
}
@ -713,21 +786,26 @@ static void mxs_5v_boot(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Configuring power block to boot from 5V input\n");
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
*/
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
debug("SPL: 5V VDD good\n");
mxs_boot_valid_5v();
return;
}
early_delay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
debug("SPL: 5V VDD good (after delay)\n");
mxs_boot_valid_5v();
return;
}
debug("SPL: 5V VDD not good\n");
mxs_handle_5v_conflict();
}
@ -742,6 +820,8 @@ static void mxs_init_batt_bo(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Initialising battery brown-out level to 3.0V\n");
/* Brownout at 3V */
clrsetbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
@ -762,6 +842,8 @@ static void mxs_switch_vddd_to_dcdc_source(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Switching VDDD to DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
@ -788,6 +870,8 @@ static void mxs_power_configure_power_source(void)
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
debug("SPL: Configuring power source\n");
mxs_src_power_init();
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
@ -811,6 +895,10 @@ static void mxs_power_configure_power_source(void)
mxs_batt_boot();
}
/*
* TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
* from USB VBUS
*/
mxs_power_clock2pll();
mxs_init_batt_bo();
@ -819,6 +907,7 @@ static void mxs_power_configure_power_source(void)
#ifdef CONFIG_MX23
/* Fire up the VDDMEM LinReg now that we're all set. */
debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
&power_regs->hw_power_vddmemctrl);
#endif
@ -838,6 +927,8 @@ static void mxs_enable_output_rail_protection(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Enabling output rail protection\n");
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
@ -1077,6 +1168,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
*/
static void mxs_setup_batt_detect(void)
{
debug("SPL: Starting battery voltage measurement logic\n");
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();
early_delay(10);
@ -1111,6 +1204,8 @@ void mxs_power_init(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Initialising Power Block\n");
mxs_ungate_power();
mxs_power_clock2xtal();
@ -1123,9 +1218,13 @@ void mxs_power_init(void)
mxs_power_configure_power_source();
mxs_enable_output_rail_protection();
debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
debug("SPL: Setting VDDD to 1V5 (brownout @ 1v0)\n");
mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
#ifdef CONFIG_MX23
debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
#endif
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
@ -1150,6 +1249,7 @@ void mxs_power_wait_pswitch(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("SPL: Waiting for power switch input\n");
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;
}

96
arch/arm/cpu/armv7/mx6/ddr.c
View file

@ -12,6 +12,65 @@
#include <asm/io.h>
#include <asm/types.h>
#if defined(CONFIG_MX6SX)
/* Configure MX6SX mmdc iomux */
void mx6sx_dram_iocfg(unsigned width,
const struct mx6sx_iomux_ddr_regs *ddr,
const struct mx6sx_iomux_grp_regs *grp)
{
struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
/* DDR IO TYPE */
writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
/* CLOCK */
writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
/* ADDRESS */
writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
/* Control */
writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
/* Data Strobes */
writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
if (width >= 32) {
writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
}
/* Data */
writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
if (width >= 32) {
writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
}
writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
if (width >= 32) {
writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
}
}
#endif
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
/* Configure MX6DQ mmdc iomux */
void mx6dq_dram_iocfg(unsigned width,
@ -184,12 +243,19 @@ void mx6sdl_dram_iocfg(unsigned width,
*/
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#ifdef CONFIG_MX6SX
#define MMDC1(entry, value) do {} while (0)
#else
#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
#endif
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const struct mx6_ddr3_cfg *ddr3_cfg)
{
volatile struct mmdc_p_regs *mmdc0;
#ifndef CONFIG_MX6SX
volatile struct mmdc_p_regs *mmdc1;
#endif
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@ -203,7 +269,9 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
int cs;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
#ifndef CONFIG_MX6SX
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
#endif
/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
@ -362,12 +430,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
mmdc0->mprddlctl = calib->p0_mprddlctl;
mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
if (sysinfo->dsize > 1) {
mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
mmdc1->mprddlctl = calib->p1_mprddlctl;
mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
MMDC1(mprddlctl, calib->p1_mprddlctl);
MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
}
/* Read data DQ Byte0-3 delay */
@ -379,23 +447,23 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
}
if (sysinfo->dsize > 1) {
mmdc1->mprddqby0dl = 0x33333333;
mmdc1->mprddqby1dl = 0x33333333;
mmdc1->mprddqby2dl = 0x33333333;
mmdc1->mprddqby3dl = 0x33333333;
MMDC1(mprddqby0dl, 0x33333333);
MMDC1(mprddqby1dl, 0x33333333);
MMDC1(mprddqby2dl, 0x33333333);
MMDC1(mprddqby3dl, 0x33333333);
}
/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
mmdc0->mpodtctrl = val;
if (sysinfo->dsize > 1)
mmdc1->mpodtctrl = val;
MMDC1(mpodtctrl, val);
/* complete calibration */
val = (1 << 11); /* Force measurement on delay-lines */
mmdc0->mpmur0 = val;
if (sysinfo->dsize > 1)
mmdc1->mpmur0 = val;
MMDC1(mpmur0, val);
/* Step 1: configuration request */
mmdc0->mdscr = (u32)(1 << 15); /* config request */
@ -435,7 +503,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
val = 0xa1390001; /* one-time HW ZQ calib */
mmdc0->mpzqhwctrl = val;
if (sysinfo->dsize > 1)
mmdc1->mpzqhwctrl = val;
MMDC1(mpzqhwctrl, val);
/* Step 7: Enable MMDC with desired chip select */
mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
@ -477,7 +545,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
val = 0xa1390003;
mmdc0->mpzqhwctrl = val;
if (sysinfo->dsize > 1)
mmdc1->mpzqhwctrl = val;
MMDC1(mpzqhwctrl, val);
/* Step 12: Configure and activate periodic refresh */
mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */

2
arch/arm/cpu/armv7/mx6/soc.c
View file

@ -109,7 +109,7 @@ void init_aips(void)
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
#endif
/*

16
arch/arm/include/asm/arch-mx6/imx-regs.h
View file

@ -88,8 +88,8 @@
#define AIPS2_ARB_BASE_ADDR 0x02100000
#define AIPS2_ARB_END_ADDR 0x021FFFFF
#ifdef CONFIG_MX6SX
#define AIPS3_BASE_ADDR 0x02200000
#define AIPS3_END_ADDR 0x022FFFFF
#define AIPS3_ARB_BASE_ADDR 0x02200000
#define AIPS3_ARB_END_ADDR 0x022FFFFF
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
@ -624,12 +624,16 @@ struct fuse_bank0_regs {
u32 rsvd1[3];
u32 uid_high;
u32 rsvd2[3];
u32 rsvd3[4];
u32 rsvd4[4];
u32 rsvd5[4];
u32 cfg2;
u32 rsvd3[3];
u32 cfg3;
u32 rsvd4[3];
u32 cfg4;
u32 rsvd5[3];
u32 cfg5;
u32 rsvd6[3];
u32 rsvd7[4];
u32 cfg6;
u32 rsvd7[3];
};
#ifdef CONFIG_MX6SX

46
arch/arm/include/asm/arch-mx6/mx6-ddr.h
View file

@ -62,6 +62,49 @@ struct mmdc_p_regs {
u32 mpmur0;
};
#define MX6SX_IOM_DDR_BASE 0x020e0200
struct mx6sx_iomux_ddr_regs {
u32 res1[59];
u32 dram_dqm0;
u32 dram_dqm1;
u32 dram_dqm2;
u32 dram_dqm3;
u32 dram_ras;
u32 dram_cas;
u32 res2[2];
u32 dram_sdwe_b;
u32 dram_odt0;
u32 dram_odt1;
u32 dram_sdba0;
u32 dram_sdba1;
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdcke1;
u32 dram_sdclk_0;
u32 dram_sdqs0;
u32 dram_sdqs1;
u32 dram_sdqs2;
u32 dram_sdqs3;
u32 dram_reset;
};
#define MX6SX_IOM_GRP_BASE 0x020e0500
struct mx6sx_iomux_grp_regs {
u32 res1[61];
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 grp_ddrpke;
u32 grp_ddrpk;
u32 grp_ddrhys;
u32 grp_ddrmode;
u32 grp_b0ds;
u32 grp_b1ds;
u32 grp_ctlds;
u32 grp_ddr_type;
u32 grp_b2ds;
u32 grp_b3ds;
};
/*
* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
*/
@ -243,6 +286,9 @@ void mx6dq_dram_iocfg(unsigned width,
void mx6sdl_dram_iocfg(unsigned width,
const struct mx6sdl_iomux_ddr_regs *,
const struct mx6sdl_iomux_grp_regs *);
void mx6sx_dram_iocfg(unsigned width,
const struct mx6sx_iomux_ddr_regs *,
const struct mx6sx_iomux_grp_regs *);
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,

17
arch/arm/include/asm/arch-mxs/sys_proto.h
View file

@ -74,6 +74,23 @@ static const struct mxs_pair mxs_boot_modes[] = {
#endif
};
#define MXS_BM_USB 0x00
#define MXS_BM_I2C_MASTER_3V3 0x01
#define MXS_BM_I2C_MASTER_1V8 0x11
#define MXS_BM_SPI2_MASTER_3V3_NOR 0x02
#define MXS_BM_SPI2_MASTER_1V8_NOR 0x12
#define MXS_BM_SPI3_MASTER_3V3_NOR 0x03
#define MXS_BM_SPI3_MASTER_1V8_NOR 0x13
#define MXS_BM_NAND_3V3 0x04
#define MXS_BM_NAND_1V8 0x14
#define MXS_BM_JTAG 0x06
#define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08
#define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18
#define MXS_BM_SDMMC0_3V3 0x09
#define MXS_BM_SDMMC0_1V8 0x19
#define MXS_BM_SDMMC1_3V3 0x0a
#define MXS_BM_SDMMC1_1V8 0x1a
struct mxs_spl_data {
uint8_t boot_mode_idx;
uint32_t mem_dram_size;

8
board/aristainetos/aristainetos.c
View file

@ -321,8 +321,8 @@ static void enable_lvds(struct display_info_t const *dev)
/* enable backlight PWM 3 */
if (pwm_init(2, 0, 0))
goto error;
/* duty cycle 200ns, period: 3000ns */
if (pwm_config(2, 200, 3000))
/* duty cycle 500ns, period: 3000ns */
if (pwm_config(2, 500, 3000))
goto error;
if (pwm_enable(2))
goto error;
@ -350,8 +350,8 @@ struct display_info_t const displays[] = {
.right_margin = 88,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 25,
.vsync_len = 1,
.hsync_len = 80,
.vsync_len = 25,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
}

4
board/bachmann/ot1200/Makefile
View file

@ -6,4 +6,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y := ot1200.o ot1200_spl.o
else
obj-y := ot1200.o
endif

14
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
View file

@ -142,20 +142,6 @@ DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
/*
* Setup CCM_CCOSR register as follows:

34
board/bachmann/ot1200/ot1200.c
View file

@ -6,6 +6,7 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
@ -16,6 +17,7 @@
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <netdev.h>
@ -46,7 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
gd->ram_size = imx_ddr_size();
return 0;
}
@ -118,8 +120,35 @@ static void setup_iomux_features(void)
ARRAY_SIZE(feature_pads));
}
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC33, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
int board_early_init_f(void)
{
ccgr_init();
gpr_init();
setup_iomux_uart();
setup_iomux_spi();
setup_iomux_features();
@ -290,9 +319,6 @@ int board_init(void)
leds_on();
/* enable ecspi3 clocks */
enable_cspi_clock(1, 2);
#ifdef CONFIG_CMD_SATA
setup_sata();
#endif

162
board/bachmann/ot1200/ot1200_spl.c Normal file
View file

@ -0,0 +1,162 @@
/*
* Copyright (C) 2015, Bachmann electronic GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
DECLARE_GLOBAL_DATA_PTR;
/* Configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
.dram_sdclk_0 = 0x00000028,
.dram_sdclk_1 = 0x00000028,
.dram_cas = 0x00000028,
.dram_ras = 0x00000028,
.dram_reset = 0x00000028,
/* SDCKE[0:1]: 100k pull-up */
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
/* SDBA2: pull-up disabled */
.dram_sdba2 = 0x00000000,
/* SDODT[0:1]: 100k pull-up, 48 ohm */
.dram_sdodt0 = 0x00000028,
.dram_sdodt1 = 0x00000028,
/* SDQS[0:7]: Differential input, 48 ohm */
.dram_sdqs0 = 0x00000028,
.dram_sdqs1 = 0x00000028,
.dram_sdqs2 = 0x00000028,
.dram_sdqs3 = 0x00000028,
.dram_sdqs4 = 0x00000028,
.dram_sdqs5 = 0x00000028,
.dram_sdqs6 = 0x00000028,
.dram_sdqs7 = 0x00000028,
/* DQM[0:7]: Differential input, 48 ohm */
.dram_dqm0 = 0x00000028,
.dram_dqm1 = 0x00000028,
.dram_dqm2 = 0x00000028,
.dram_dqm3 = 0x00000028,
.dram_dqm4 = 0x00000028,
.dram_dqm5 = 0x00000028,
.dram_dqm6 = 0x00000028,
.dram_dqm7 = 0x00000028,
};
/* Configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
/* DDR3 */
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
/* Disable DDR pullups */
.grp_ddrpke = 0x00000000,
/* ADDR[00:16], SDBA[0:1]: 48 ohm */
.grp_addds = 0x00000028,
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
.grp_ctlds = 0x00000028,
/* DATA[00:63]: Differential input, 48 ohm */
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000028,
.grp_b1ds = 0x00000028,
.grp_b2ds = 0x00000028,
.grp_b3ds = 0x00000028,
.grp_b4ds = 0x00000028,
.grp_b5ds = 0x00000028,
.grp_b6ds = 0x00000028,
.grp_b7ds = 0x00000028,
};
static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
/* Width of data bus: 0=16, 1=32, 2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* Single chip select */
.ncs = 1,
.cs1_mirror = 0, /* war 0 */
.rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
.rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */ /* war 1 */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
};
/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg micron_2gib_1600 = {
.mem_speed = 1600,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.SRT = 1,
};
static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x00260025,
.p0_mpwldectrl1 = 0x00270021,
.p1_mpwldectrl0 = 0x00180034,
.p1_mpwldectrl1 = 0x00180024,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x04380344,
.p0_mpdgctrl1 = 0x0330032C,
.p1_mpdgctrl0 = 0x0338033C,
.p1_mpdgctrl1 = 0x032C0300,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x3C2E3238,
.p1_mprddlctl = 0x3A2E303C,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x36384036,
.p1_mpwrdlctl = 0x442E4438,
};
static void ot1200_spl_dram_init(void)
{
mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
&micron_2gib_1600);
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* configure MMDC for SDRAM width/size and per-model calibration */
ot1200_spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void reset_cpu(ulong addr)
{
}

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if TARGET_PLATINUM_PICON
config SYS_CPU
default "armv7"
config SYS_VENDOR
default "barco"
config SYS_SOC
default "mx6"
config SYS_BOARD
default "platinum"
config SYS_CONFIG_NAME
default "platinum_picon"
endif
if TARGET_PLATINUM_TITANIUM
config SYS_CPU
default "armv7"
config SYS_VENDOR
default "barco"
config SYS_SOC
default "mx6"
config SYS_BOARD
default "platinum"
config SYS_CONFIG_NAME
default "platinum_titanium"
endif

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PLATINUM BOARD
M: Stefan Roese <sr@denx.de>
S: Maintained
F: board/barco/platinum/
F: include/configs/platinum.h
F: configs/platinum_picon_defconfig
F: configs/platinum_titanium_defconfig

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#
# Copyright (C) 2014, Barco (www.barco.com)
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := platinum.o
obj-$(CONFIG_TARGET_PLATINUM_PICON) += platinum_picon.o
obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += platinum_titanium.o
ifneq ($(CONFIG_SPL_BUILD),)
obj-$(CONFIG_TARGET_PLATINUM_PICON) += spl_picon.o
obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += spl_titanium.o
endif

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/*
* Copyright (C) 2014, Barco (www.barco.com)
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include "platinum.h"
DECLARE_GLOBAL_DATA_PTR;
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t nfc_pads[] = {
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
};
struct fsl_esdhc_cfg usdhc_cfg[] = {
{ USDHC3_BASE_ADDR },
};
void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
/* config gpmi and bch clock to 100 MHz */
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
int board_ehci_hcd_init(int port)
{
return 0;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) {
unsigned sd3_cd = IMX_GPIO_NR(7, 0);
gpio_direction_input(sd3_cd);
return !gpio_get_value(sd3_cd);
}
return 0;
}
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
void board_init_gpio(void)
{
platinum_init_gpio();
}
void board_init_gpmi_nand(void)
{
setup_gpmi_nand();
}
void board_init_i2c(void)
{
platinum_setup_i2c();
}
void board_init_spi(void)
{
platinum_setup_spi();
}
void board_init_uart(void)
{
platinum_setup_uart();
}
void board_init_usb(void)
{
platinum_init_usb();
}
void board_init_finished(void)
{
platinum_init_finished();
}
int board_phy_config(struct phy_device *phydev)
{
return platinum_phy_config(phydev);
}
int board_eth_init(bd_t *bis)
{
return cpu_eth_init(bis);
}
int board_early_init_f(void)
{
board_init_uart();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
board_init_spi();
board_init_i2c();
board_init_gpmi_nand();
board_init_gpio();
board_init_usb();
board_init_finished();
return 0;
}
int checkboard(void)
{
puts("Board: " CONFIG_PLATINUM_BOARD "\n");
return 0;
}
static const struct boot_mode board_boot_modes[] = {
/* NAND */
{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
/* 4 bit bus width */
{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
{ NULL, 0 },
};
int misc_init_r(void)
{
add_board_boot_modes(board_boot_modes);
return 0;
}

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/*
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PLATINUM_H_
#define _PLATINUM_H_
#include <miiphy.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
/* Defines */
#define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
PAD_CTL_HYS)
#define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
#define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL)
/* Prototypes */
int platinum_setup_enet(void);
int platinum_setup_i2c(void);
int platinum_setup_spi(void);
int platinum_setup_uart(void);
int platinum_phy_config(struct phy_device *phydev);
int platinum_init_gpio(void);
int platinum_init_usb(void);
int platinum_init_finished(void);
static inline void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static inline void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
#endif /* _PLATINUM_H_ */

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/*
* Copyright (C) 2014, Barco (www.barco.com)
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <i2c.h>
#include <miiphy.h>
#include "platinum.h"
#define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18)
#define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13)
#define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19)
#define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2)
#define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11)
#define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13)
#define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17)
#define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20)
#define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14)
#define GPIO_USB_RESET IMX_GPIO_NR(1, 5)
iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS),
MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS),
};
iomux_v3_cfg_t const ecspi2_pads[] = {
MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS),
};
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
/* PHY nRESET */
iomux_v3_cfg_t const phy_reset_pad = {
MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart5_pads[] = {
MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const i2c0_mux_pads[] = {
MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const i2c2_mux_pads[] = {
MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
};
/*
* This enet related pin-muxing and GPIO handling is done
* in SPL U-Boot. For early initialization. And to give the
* PHY some time to come out of reset before the U-Boot
* ethernet driver tries to access its registers via MDIO.
*/
int platinum_setup_enet(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned phy_reset = IMX_GPIO_NR(1, 19);
/* First configure PHY reset GPIO pin */
imx_iomux_v3_setup_pad(phy_reset_pad);
/* Reconfigure enet muxing while PHY is in reset */
gpio_direction_output(phy_reset, 0);
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
mdelay(10);
gpio_set_value(phy_reset, 1);
udelay(100);
/* set GPIO_16 as ENET_REF_CLK_OUT */
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
return enable_fec_anatop_clock(ENET_50MHZ);
}
int platinum_setup_i2c(void)
{
imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads,
ARRAY_SIZE(i2c0_mux_pads));
imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads,
ARRAY_SIZE(i2c2_mux_pads));
mdelay(10);
/* Disable i2c mux 0 */
gpio_direction_output(GPIO_I2C0_SEL0, 0);
gpio_direction_output(GPIO_I2C0_SEL1, 0);
gpio_direction_output(GPIO_I2C0_ENBN, 1);
/* Disable i2c mux 1 */
gpio_direction_output(GPIO_I2C2_SEL0, 0);
gpio_direction_output(GPIO_I2C2_SEL1, 0);
gpio_direction_output(GPIO_I2C2_ENBN, 1);
udelay(10);
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
/* Disable all leds */
i2c_set_bus_num(0);
i2c_reg_write(0x60, 0x05, 0x55);
return 0;
}
int platinum_setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
return 0;
}
int platinum_setup_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
return 0;
}
int platinum_phy_config(struct phy_device *phydev)
{
/* Use generic infrastructure, no specific setup */
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int platinum_init_gpio(void)
{
/* Reset FPGA's */
gpio_direction_output(GPIO_IP_NCONFIG, 0);
gpio_direction_output(GPIO_HK_NCONFIG, 0);
gpio_direction_output(GPIO_LS_NCONFIG, 0);
udelay(3);
gpio_set_value(GPIO_IP_NCONFIG, 1);
gpio_set_value(GPIO_HK_NCONFIG, 1);
gpio_set_value(GPIO_LS_NCONFIG, 1);
/* no dmd configuration yet */
return 0;
}
int platinum_init_usb(void)
{
/* Reset usb hub */
gpio_direction_output(GPIO_USB_RESET, 0);
udelay(100);
gpio_set_value(GPIO_USB_RESET, 1);
return 0;
}
int platinum_init_finished(void)
{
/* Enable led 0 */
i2c_set_bus_num(0);
i2c_reg_write(0x60, 0x05, 0x54);
return 0;
}

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/*
* Copyright (C) 2014, Barco (www.barco.com)
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <miiphy.h>
#include <micrel.h>
#include "platinum.h"
iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
/* non mounted spi nor flash for booting */
MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS),
MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS),
};
iomux_v3_cfg_t const ecspi2_pads[] = {
MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
};
iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 42 PHY nRST */
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL,
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL,
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
/*
* This enet related pin-muxing and GPIO handling is done
* in SPL U-Boot. For early initialization. And to give the
* PHY some time to come out of reset before the U-Boot
* ethernet driver tries to access its registers via MDIO.
*/
int platinum_setup_enet(void)
{
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
/* Need delay 10ms according to KSZ9021 spec */
mdelay(10);
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
udelay(100);
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
return 0;
}
int platinum_setup_i2c(void)
{
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
return 0;
}
int platinum_setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
return 0;
}
int platinum_setup_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
return 0;
}
int platinum_phy_config(struct phy_device *phydev)
{
/* min rx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x0);
/* min tx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x0);
/* max rx/tx clock delay, min rx/tx control */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf0f0);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int platinum_init_gpio(void)
{
/* Default GPIO's */
/* Toggle CONFIG_n to reset fpga on every boot */
gpio_direction_output(IMX_GPIO_NR(5, 18), 0);
/* Need delay >=2uS */
udelay(3);
gpio_set_value(IMX_GPIO_NR(5, 18), 1);
/* Default pin 1,15 high - DLP_FLASH_WPZ */
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
return 0;
}
int platinum_init_usb(void)
{
return 0;
}
int platinum_init_finished(void)
{
return 0;
}

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/*
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*
* Based on: gw_ventana_spl.c which is:
* Copyright (C) 2014 Gateworks Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <spl.h>
#include "platinum.h"
DECLARE_GLOBAL_DATA_PTR;
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
.dram_cas = 0x00020030,
.dram_ras = 0x00020030,
.dram_reset = 0x00020030,
/* SDCKE[0:1]: 100k pull-up */
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
/* SDBA2: pull-up disabled */
.dram_sdba2 = 0x00000000,
/* SDODT[0:1]: 100k pull-up, 40 ohm */
.dram_sdodt0 = 0x00003030,
.dram_sdodt1 = 0x00003030,
/* SDQS[0:7]: Differential input, 40 ohm */
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
/* DQM[0:7]: Differential input, 40 ohm */
.dram_dqm0 = 0x00020030,
.dram_dqm1 = 0x00020030,
.dram_dqm2 = 0x00020030,
.dram_dqm3 = 0x00020030,
.dram_dqm4 = 0x00020030,
.dram_dqm5 = 0x00020030,
.dram_dqm6 = 0x00020030,
.dram_dqm7 = 0x00020030,
};
/* Configure MX6Q/DUAL mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
/* DDR3 */
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
/* disable DDR pullups */
.grp_ddrpke = 0x00000000,
/* ADDR[00:16], SDBA[0:1]: 40 ohm */
.grp_addds = 0x00000030,
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
.grp_ctlds = 0x00000030,
/* DATA[00:63]: Differential input, 40 ohm */
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_b2ds = 0x00000030,
.grp_b3ds = 0x00000030,
.grp_b4ds = 0x00000030,
.grp_b5ds = 0x00000030,
.grp_b6ds = 0x00000030,
.grp_b7ds = 0x00000030,
};
/* MT41K256M16HA-125 */
static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
.mem_speed = 1600,
.density = 4, /* 4Gbit */
.width = 16,
.banks = 8,
.rowaddr = 15,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
/*
* Values from running the Freescale DDR stress tool via USB
*/
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x0044004E,
.p0_mpwldectrl1 = 0x001F0023,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x02480248,
.p0_mpdgctrl1 = 0x0210021C,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x42444444,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x36322C32,
};
static void spl_dram_init(int width)
{
struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = width / 32,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 1,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
#else
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
#endif
.walat = 0, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
};
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
}
/*
* Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* Setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* UART iomux */
board_early_init_f();
/* Setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Init DDR with 32bit width */
spl_dram_init(32);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
/*
* Setup enet related MUXing early to give the PHY
* some time to wake-up from reset
*/
platinum_setup_enet();
/* load/boot image from boot device */
board_init_r(NULL, 0);
}

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/*
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*
* Based on: gw_ventana_spl.c which is:
* Copyright (C) 2014 Gateworks Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <spl.h>
#include "platinum.h"
DECLARE_GLOBAL_DATA_PTR;
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
/* Configure MX6Q/DUAL mmdc DDR io registers */
struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
.dram_cas = 0x00020030,
.dram_ras = 0x00020030,
.dram_reset = 0x00020030,
/* SDCKE[0:1]: 100k pull-up */
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
/* SDBA2: pull-up disabled */
.dram_sdba2 = 0x00000000,
/* SDODT[0:1]: 100k pull-up, 40 ohm */
.dram_sdodt0 = 0x00003030,
.dram_sdodt1 = 0x00003030,
/* SDQS[0:7]: Differential input, 40 ohm */
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
/* DQM[0:7]: Differential input, 40 ohm */
.dram_dqm0 = 0x00020030,
.dram_dqm1 = 0x00020030,
.dram_dqm2 = 0x00020030,
.dram_dqm3 = 0x00020030,
.dram_dqm4 = 0x00020030,
.dram_dqm5 = 0x00020030,
.dram_dqm6 = 0x00020030,
.dram_dqm7 = 0x00020030,
};
/* Configure MX6Q/DUAL mmdc GRP io registers */
struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
/* DDR3 */
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
/* disable DDR pullups */
.grp_ddrpke = 0x00000000,
/* ADDR[00:16], SDBA[0:1]: 40 ohm */
.grp_addds = 0x00000030,
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
.grp_ctlds = 0x00000030,
/* DATA[00:63]: Differential input, 40 ohm */
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_b2ds = 0x00000030,
.grp_b3ds = 0x00000030,
.grp_b4ds = 0x00000030,
.grp_b5ds = 0x00000030,
.grp_b6ds = 0x00000030,
.grp_b7ds = 0x00000030,
};
/* MT41J128M16JT-125 */
static struct mx6_ddr3_cfg mt41j128m16jt_125 = {
.mem_speed = 1600,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
/* Write leveling calibration determine */
.p0_mpwldectrl0 = 0x001f001f,
.p0_mpwldectrl1 = 0x001f001f,
.p1_mpwldectrl0 = 0x00440044,
.p1_mpwldectrl1 = 0x00440044,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x434b0350,
.p0_mpdgctrl1 = 0x034c0359,
.p1_mpdgctrl0 = 0x434b0350,
.p1_mpdgctrl1 = 0x03650348,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x4436383b,
.p1_mprddlctl = 0x39393341,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x35373933,
.p1_mpwrdlctl = 0x48254a36,
};
static void spl_dram_init(int width)
{
struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = width / 32,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 1,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
#else
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
#endif
.walat = 0, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
};
mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
}
/*
* Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
* - no variable global data is available
*/
void board_init_f(ulong dummy)
{
/* Setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* UART iomux */
board_early_init_f();
/* Setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* Init DDR with 32bit width */
spl_dram_init(32);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
/*
* Setup enet related MUXing early to give the PHY
* some time to wake-up from reset
*/
platinum_setup_enet();
/* load/boot image from boot device */
board_init_r(NULL, 0);
}

95
board/compulab/cm_fx6/cm_fx6.c
View file

@ -15,19 +15,86 @@
#include <netdev.h>
#include <fdt_support.h>
#include <sata.h>
#include <splash.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/sata.h>
#include <asm/imx-common/video.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/platform_data/serial_mxc.h>
#include "common.h"
#include "../common/eeprom.h"
#include "../common/common.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPLASH_SCREEN
static struct splash_location cm_fx6_splash_locations[] = {
{
.name = "sf",
.storage = SPLASH_STORAGE_SF,
.offset = 0x100000,
},
};
int splash_screen_prepare(void)
{
return splash_source_load(cm_fx6_splash_locations,
ARRAY_SIZE(cm_fx6_splash_locations));
}
#endif
#ifdef CONFIG_IMX_HDMI
static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
{
imx_enable_hdmi_phy();
}
struct display_info_t const displays[] = {
{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.enable = cm_fx6_enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 40385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED,
}
},
};
size_t display_count = ARRAY_SIZE(displays);
static void cm_fx6_setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int reg;
enable_ipu_clock();
imx_setup_hdmi();
reg = __raw_readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
}
#else
static inline void cm_fx6_setup_display(void) {}
#endif /* CONFIG_VIDEO_IPUV3 */
#ifdef CONFIG_DWC_AHSATA
static int cm_fx6_issd_gpios[] = {
/* The order of the GPIOs in the array is important! */
@ -345,32 +412,36 @@ static iomux_v3_cfg_t const enet_pads[] = {
MUX_PAD_CTRL(ENET_PAD_CTRL)),
};
static int handle_mac_address(void)
static int handle_mac_address(char *env_var, uint eeprom_bus)
{
unsigned char enetaddr[6];
int rc;
rc = eth_getenv_enetaddr("ethaddr", enetaddr);
rc = eth_getenv_enetaddr(env_var, enetaddr);
if (rc)
return 0;
rc = cl_eeprom_read_mac_addr(enetaddr);
rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
if (rc)
return rc;
if (!is_valid_ether_addr(enetaddr))
return -1;
return eth_setenv_enetaddr("ethaddr", enetaddr);
return eth_setenv_enetaddr(env_var, enetaddr);
}
#define SB_FX6_I2C_EEPROM_BUS 0
#define NO_MAC_ADDR "No MAC address found for %s\n"
int board_eth_init(bd_t *bis)
{
int err;
err = handle_mac_address();
if (err)
puts("No MAC address found\n");
if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
printf(NO_MAC_ADDR, "primary NIC");
if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
printf(NO_MAC_ADDR, "secondary NIC");
SETUP_IOMUX_PADS(enet_pads);
/* phy reset */
@ -464,7 +535,13 @@ int ft_board_setup(void *blob, bd_t *bd)
/* MAC addr */
if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
fdt_find_and_setprop(blob, "/fec", "local-mac-address",
fdt_find_and_setprop(blob,
"/soc/aips-bus@02100000/ethernet@02188000",
"local-mac-address", enetaddr, 6, 1);
}
if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
enetaddr, 6, 1);
}
@ -506,6 +583,8 @@ int board_init(void)
if (ret)
printf("Warning: I2C setup failed: %d\n", ret);
cm_fx6_setup_display();
return 0;
}

2
board/compulab/cm_t335/cm_t335.c
View file

@ -110,7 +110,7 @@ static int handle_mac_address(void)
if (rv)
return 0;
rv = cl_eeprom_read_mac_addr(enetaddr);
rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
if (rv)
get_efuse_mac_addr(enetaddr);

14
board/compulab/cm_t35/cm_t35.c
View file

@ -19,6 +19,7 @@
#include <i2c.h>
#include <usb.h>
#include <mmc.h>
#include <splash.h>
#include <twl4030.h>
#include <linux/compiler.h>
@ -59,11 +60,18 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
}
#endif
#define CM_T35_SPLASH_NAND_OFFSET 0x100000
struct splash_location splash_locations[] = {
{
.name = "nand",
.storage = SPLASH_STORAGE_NAND,
.offset = 0x100000,
},
};
int splash_screen_prepare(void)
{
return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET);
return splash_source_load(splash_locations,
ARRAY_SIZE(splash_locations));
}
/*
@ -429,7 +437,7 @@ static int handle_mac_address(void)
if (rc)
return 0;
rc = cl_eeprom_read_mac_addr(enetaddr);
rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
if (rc)
return rc;

2
board/compulab/cm_t3517/cm_t3517.c
View file

@ -163,7 +163,7 @@ static int cm_t3517_handle_mac_address(void)
if (ret)
return 0;
ret = cl_eeprom_read_mac_addr(enetaddr);
ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
if (ret) {
ret = am3517_get_efuse_enetaddr(enetaddr);
if (ret)

2
board/compulab/cm_t54/cm_t54.c
View file

@ -165,7 +165,7 @@ static int handle_mac_address(void)
if (ret)
return 0;
ret = cl_eeprom_read_mac_addr(enetaddr);
ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
if (ret || !is_valid_ether_addr(enetaddr))
generate_mac_addr(enetaddr);

1
board/compulab/common/Makefile
View file

@ -9,5 +9,4 @@
obj-y += common.o
obj-$(CONFIG_SYS_I2C) += eeprom.o
obj-$(CONFIG_LCD) += omap3_display.o
obj-$(CONFIG_SPLASH_SCREEN) += splash.o
obj-$(CONFIG_SMC911X) += omap3_smc911x.o

9
board/compulab/common/common.h
View file

@ -24,15 +24,6 @@ static inline int cl_usb_hub_init(int gpio, const char *label)
static inline void cl_usb_hub_deinit(int gpio) {}
#endif /* CONFIG_CMD_USB */
#ifdef CONFIG_SPLASH_SCREEN
int cl_splash_screen_prepare(int nand_offset);
#else /* !CONFIG_SPLASH_SCREEN */
static inline int cl_splash_screen_prepare(int nand_offset)
{
return -ENOSYS;
}
#endif /* CONFIG_SPLASH_SCREEN */
#ifdef CONFIG_SMC911X
int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
int (*reset)(int), int rst_gpio);

20
board/compulab/common/eeprom.c
View file

@ -31,6 +31,7 @@
#define LAYOUT_INVALID 0
#define LAYOUT_LEGACY 0xff
static int cl_eeprom_bus;
static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
static int cl_eeprom_read(uint offset, uchar *buf, int len)
@ -38,7 +39,7 @@ static int cl_eeprom_read(uint offset, uchar *buf, int len)
int res;
unsigned int current_i2c_bus = i2c_get_bus_num();
res = i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
res = i2c_set_bus_num(cl_eeprom_bus);
if (res < 0)
return res;
@ -50,13 +51,18 @@ static int cl_eeprom_read(uint offset, uchar *buf, int len)
return res;
}
static int cl_eeprom_setup_layout(void)
static int cl_eeprom_setup(uint eeprom_bus)
{
int res;
if (cl_eeprom_layout != LAYOUT_INVALID)
/*
* We know the setup was already done when the layout is set to a valid
* value and we're using the same bus as before.
*/
if (cl_eeprom_layout != LAYOUT_INVALID && eeprom_bus == cl_eeprom_bus)
return 0;
cl_eeprom_bus = eeprom_bus;
res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET,
(uchar *)&cl_eeprom_layout, 1);
if (res) {
@ -77,7 +83,7 @@ void get_board_serial(struct tag_serialnr *serialnr)
memset(serialnr, 0, sizeof(*serialnr));
if (cl_eeprom_setup_layout())
if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS))
return;
offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
@ -96,11 +102,11 @@ void get_board_serial(struct tag_serialnr *serialnr)
* Routine: cl_eeprom_read_mac_addr
* Description: read mac address and store it in buf.
*/
int cl_eeprom_read_mac_addr(uchar *buf)
int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus)
{
uint offset;
if (cl_eeprom_setup_layout())
if (cl_eeprom_setup(eeprom_bus))
return 0;
offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
@ -123,7 +129,7 @@ u32 cl_eeprom_get_board_rev(void)
if (board_rev)
return board_rev;
if (cl_eeprom_setup_layout())
if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS))
return 0;
if (cl_eeprom_layout != LAYOUT_LEGACY)

4
board/compulab/common/eeprom.h
View file

@ -11,10 +11,10 @@
#define _EEPROM_
#ifdef CONFIG_SYS_I2C
int cl_eeprom_read_mac_addr(uchar *buf);
int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus);
u32 cl_eeprom_get_board_rev(void);
#else
static inline int cl_eeprom_read_mac_addr(uchar *buf)
static inline int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus)
{
return 1;
}

72
board/compulab/common/splash.c
View file

@ -1,72 +0,0 @@
/*
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
*
* Authors: Igor Grinberg <grinberg@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <nand.h>
#include <bmp_layout.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
{
struct bmp_header *bmp_hdr;
int res;
size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
goto splash_address_too_high;
res = nand_read_skip_bad(&nand_info[nand_curr_device],
nand_offset, &bmp_header_size,
NULL, nand_info[nand_curr_device].size,
(u_char *)bmp_load_addr);
if (res < 0)
return res;
bmp_hdr = (struct bmp_header *)bmp_load_addr;
bmp_size = le32_to_cpu(bmp_hdr->file_size);
if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
goto splash_address_too_high;
return nand_read_skip_bad(&nand_info[nand_curr_device],
nand_offset, &bmp_size,
NULL, nand_info[nand_curr_device].size,
(u_char *)bmp_load_addr);
splash_address_too_high:
printf("Error: splashimage address too high. Data overwrites U-Boot "
"and/or placed beyond DRAM boundaries.\n");
return -1;
}
#else
static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
{
return -1;
}
#endif /* CONFIG_CMD_NAND */
int cl_splash_screen_prepare(int nand_offset)
{
char *env_splashimage_value;
u32 bmp_load_addr;
env_splashimage_value = getenv("splashimage");
if (env_splashimage_value == NULL)
return -1;
bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
if (bmp_load_addr == 0) {
printf("Error: bad splashimage address specified\n");
return -1;
}
return splash_load_from_nand(bmp_load_addr, nand_offset);
}

3
board/freescale/mx53loco/imximage.cfg
View file

@ -59,7 +59,7 @@ DATA 4 0x63fd9090 0x4d444c44
DATA 4 0x63fd907c 0x01370138
DATA 4 0x63fd9080 0x013b013c
DATA 4 0x63fd9018 0x00011740
DATA 4 0x63fd9000 0xc3190000
DATA 4 0x63fd9000 0x83190000
DATA 4 0x63fd900c 0x9f5152e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
@ -72,6 +72,7 @@ DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x052080b0
DATA 4 0x63fd901c 0x04008040
DATA 4 0x63fd9000 0xc3190000
DATA 4 0x63fd901c 0x0000803a
DATA 4 0x63fd901c 0x0000803b
DATA 4 0x63fd901c 0x00028039

25
board/freescale/mx6qsabreauto/mx6qsabreauto.c
View file

@ -311,30 +311,9 @@ static void setup_gpmi_nand(void)
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
/* gate ENFC_CLK_ROOT clock first,before clk source switch */
clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
/* config gpmi and bch clock to 100 MHz */
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
/* enable ENFC_CLK_ROOT clock */
setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);

1
board/freescale/mx6sxsabresd/MAINTAINERS
View file

@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/mx6sxsabresd/
F: include/configs/mx6sxsabresd.h
F: configs/mx6sxsabresd_defconfig
F: configs/mx6sxsabresd_spl_defconfig

173
board/freescale/mx6sxsabresd/mx6sxsabresd.c
View file

@ -326,6 +326,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
int i, ret;
/*
@ -369,6 +370,47 @@ int board_mmc_init(bd_t *bis)
}
return 0;
#else
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
u32 port;
val = readl(&src_regs->sbmr1);
if ((val & 0xc0) != 0x40) {
printf("Not boot from USDHC!\n");
return -EINVAL;
}
port = (val >> 11) & 0x3;
printf("port %d\n", port);
switch (port) {
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
gpio_direction_output(USDHC3_PWR_GPIO, 1);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
break;
case 3:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
break;
}
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
}
#ifdef CONFIG_FSL_QSPI
@ -423,14 +465,135 @@ int board_init(void)
return 0;
}
int board_late_init(void)
{
return 0;
}
int checkboard(void)
{
puts("Board: MX6SX SABRE SDB\n");
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000028,
.dram_dqm1 = 0x00000028,
.dram_dqm2 = 0x00000028,
.dram_dqm3 = 0x00000028,
.dram_ras = 0x00000020,
.dram_cas = 0x00000020,
.dram_odt0 = 0x00000020,
.dram_odt1 = 0x00000020,
.dram_sdba2 = 0x00000000,
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
.dram_sdclk_0 = 0x00000030,
.dram_sdqs0 = 0x00000028,
.dram_sdqs1 = 0x00000028,
.dram_sdqs2 = 0x00000028,
.dram_sdqs3 = 0x00000028,
.dram_reset = 0x00000020,
};
const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000020,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000028,
.grp_b1ds = 0x00000028,
.grp_ctlds = 0x00000020,
.grp_ddr_type = 0x000c0000,
.grp_b2ds = 0x00000028,
.grp_b3ds = 0x00000028,
};
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00290025,
.p0_mpwldectrl1 = 0x00220022,
.p0_mpdgctrl0 = 0x41480144,
.p0_mpdgctrl1 = 0x01340130,
.p0_mprddlctl = 0x3C3E4244,
.p0_mpwrdlctl = 0x34363638,
};
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
.density = 4,
.width = 32,
.banks = 8,
.rowaddr = 15,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0xFFFFFFFF, &ccm->CCGR0);
writel(0xFFFFFFFF, &ccm->CCGR1);
writel(0xFFFFFFFF, &ccm->CCGR2);
writel(0xFFFFFFFF, &ccm->CCGR3);
writel(0xFFFFFFFF, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0xFFFFFFFF, &ccm->CCGR6);
writel(0xFFFFFFFF, &ccm->CCGR7);
}
static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
.dsize = mem_ddr.width/32,
.cs_density = 24,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 2, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
};
mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void reset_cpu(ulong addr)
{
}
#endif

1
common/Makefile
View file

@ -198,6 +198,7 @@ obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
obj-$(CONFIG_I2C_EDID) += edid.o
obj-$(CONFIG_KALLSYMS) += kallsyms.o
obj-y += splash.o
obj-$(CONFIG_SPLASH_SOURCE) += splash_source.o
obj-$(CONFIG_LCD) += lcd.o lcd_console.o
obj-$(CONFIG_LYNXKDI) += lynxkdi.o
obj-$(CONFIG_MENU) += menu.o

176
common/splash_source.c Normal file
View file

@ -0,0 +1,176 @@
/*
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
*
* Authors: Igor Grinberg <grinberg@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <nand.h>
#include <errno.h>
#include <splash.h>
#include <spi_flash.h>
#include <spi.h>
#include <bmp_layout.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPI_FLASH
static struct spi_flash *sf;
static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size)
{
if (!sf) {
sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
CONFIG_SF_DEFAULT_CS,
CONFIG_SF_DEFAULT_SPEED,
CONFIG_SF_DEFAULT_MODE);
if (!sf)
return -ENODEV;
}
return spi_flash_read(sf, offset, read_size, (void *)bmp_load_addr);
}
#else
static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size)
{
debug("%s: sf support not available\n", __func__);
return -ENOSYS;
}
#endif
#ifdef CONFIG_CMD_NAND
static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size)
{
return nand_read_skip_bad(&nand_info[nand_curr_device], offset,
&read_size, NULL,
nand_info[nand_curr_device].size,
(u_char *)bmp_load_addr);
}
#else
static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size)
{
debug("%s: nand support not available\n", __func__);
return -ENOSYS;
}
#endif
static int splash_storage_read(struct splash_location *location,
u32 bmp_load_addr, size_t read_size)
{
u32 offset;
if (!location)
return -EINVAL;
offset = location->offset;
switch (location->storage) {
case SPLASH_STORAGE_NAND:
return splash_nand_read(bmp_load_addr, offset, read_size);
case SPLASH_STORAGE_SF:
return splash_sf_read(bmp_load_addr, offset, read_size);
default:
printf("Unknown splash location\n");
}
return -EINVAL;
}
static int splash_load_raw(struct splash_location *location, u32 bmp_load_addr)
{
struct bmp_header *bmp_hdr;
int res;
size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
goto splash_address_too_high;
res = splash_storage_read(location, bmp_load_addr, bmp_header_size);
if (res < 0)
return res;
bmp_hdr = (struct bmp_header *)bmp_load_addr;
bmp_size = le32_to_cpu(bmp_hdr->file_size);
if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
goto splash_address_too_high;
return splash_storage_read(location, bmp_load_addr, bmp_size);
splash_address_too_high:
printf("Error: splashimage address too high. Data overwrites U-Boot and/or placed beyond DRAM boundaries.\n");
return -EFAULT;
}
/**
* select_splash_location - return the splash location based on board support
* and env variable "splashsource".
*
* @locations: An array of supported splash locations.
* @size: Size of splash_locations array.
*
* @return: If a null set of splash locations is given, or
* splashsource env variable is set to unsupported value
* return NULL.
* If splashsource env variable is not defined
* return the first entry in splash_locations as default.
* If splashsource env variable contains a supported value
* return the location selected by splashsource.
*/
static struct splash_location *select_splash_location(
struct splash_location *locations, uint size)
{
int i;
char *env_splashsource;
if (!locations || size == 0)
return NULL;
env_splashsource = getenv("splashsource");
if (env_splashsource == NULL)
return &locations[0];
for (i = 0; i < size; i++) {
if (!strcmp(locations[i].name, env_splashsource))
return &locations[i];
}
printf("splashsource env variable set to unsupported value\n");
return NULL;
}
/**
* splash_source_load - load splash image from a supported location.
*
* Select a splash image location based on the value of splashsource environment
* variable and the board supported splash source locations, and load a
* splashimage to the address pointed to by splashimage environment variable.
*
* @locations: An array of supported splash locations.
* @size: Size of splash_locations array.
*
* @return: 0 on success, negative value on failure.
*/
int splash_source_load(struct splash_location *locations, uint size)
{
struct splash_location *splash_location;
char *env_splashimage_value;
u32 bmp_load_addr;
env_splashimage_value = getenv("splashimage");
if (env_splashimage_value == NULL)
return -ENOENT;
bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
if (bmp_load_addr == 0) {
printf("Error: bad splashimage address specified\n");
return -EFAULT;
}
splash_location = select_splash_location(locations, size);
if (!splash_location)
return -EINVAL;
return splash_load_raw(splash_location, bmp_load_addr);
}

4
configs/mx6sxsabresd_spl_defconfig Normal file
View file

@ -0,0 +1,4 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_MX6SXSABRESD=y

4
configs/ot1200_spl_defconfig Normal file
View file

@ -0,0 +1,4 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_OT1200=y

4
configs/platinum_picon_defconfig Normal file
View file

@ -0,0 +1,4 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_PLATINUM_PICON=y

4
configs/platinum_titanium_defconfig Normal file
View file

@ -0,0 +1,4 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_PLATINUM_TITANIUM=y

13
doc/README.splashprepare
View file

@ -6,3 +6,16 @@ common/splash.c. It is called as part of the splash screen display
sequence. It gives the board an opportunity to prepare the splash
image data before it is processed and sent to the frame buffer by
U-Boot. Define your own version to use this feature.
CONFIG_SPLASH_SOURCE
Use the splash_source.c library. This library provides facilities to declare
board specific splash image locations, routines for loading splash image from
supported locations, and a way of controlling the selected splash location
using the "splashsource" environment variable.
splashsource works as follows:
- If splashsource is set to a supported location name as defined by board code,
use that splash location.
- If splashsource is undefined, use the first splash location as default.
- If splashsource is set to an unsupported value, do not load a splash screen.

167
include/configs/aristainetos.h
View file

@ -1,4 +1,5 @@
/*
* (C) Copyright 2015
* (C) Copyright 2014
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
@ -24,8 +25,7 @@
#include <asm/imx-common/gpio.h>
#define CONFIG_MACH_TYPE 4501
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define CONFIG_DEFAULT_FDT_FILE "aristainetos.dtb"
#define CONFIG_MMCROOT "/dev/mmcblk0p1"
#define CONFIG_HOSTNAME aristainetos
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
@ -81,7 +81,6 @@
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
@ -101,84 +100,108 @@
#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_EXTRA_ENV_SETTINGS \
"uimage=uImage\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr_r=0x11000000\0" \
"kernel_addr_r=0x12000000\0" \
"kernel_file=uImage\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"script=u-boot.scr\0" \
"fit_file=/boot/system.itb\0" \
"loadaddr=0x12000000\0" \
"fit_addr_r=0x14000000\0" \
"uboot=/boot/u-boot.imx\0" \
"uboot_sz=d0000\0" \
"rescue_sys_addr=f0000\0" \
"rescue_sys_length=f10000\0" \
"board_type=aristainetos7@1\0" \
"panel=lb07wv8\0" \
"splashpos=m,m\0" \
"console=" CONFIG_CONSOLE_DEV "\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"mtdids=nand0=gpmi-nand,nor0=spi3.0\0" \
"mtdparts=mtdparts=spi3.0:832k(u-boot),64k(env),64k(env-red)," \
"-(rescue-system);gpmi-nand:-(ubi)\0" \
"addmisc=setenv bootargs ${bootargs} consoleblank=0\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
"default ${board_type}\0" \
"get_env=mw ${loadaddr} 0 0x20000;" \
"mmc rescan;" \
"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
"env import -t ${loadaddr}\0" \
"default_env=mw ${loadaddr} 0 0x20000;" \
"env export -t ${loadaddr} serial# ethaddr eth1addr " \
"board_type panel;" \
"env default -a;" \
"env import -t ${loadaddr}\0" \
"loadbootscript=" \
"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"mmcpart=1\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcdev=0\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} " \
"${uimage}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} " \
"${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs;run loadimage loadfdt fdt_setup;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r};\0" \
"rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-sato-sdk\0" \
"nfsopts=nfsvers=3 nolock rw\0" \
"netdev=eth0\0" \
"fdt_setup=fdt addr ${fdt_addr_r};fdt resize;fdt chosen;fdt board\0"\
"load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
"load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"get_env=mw ${loadaddr} 0x00000000 0x20000;" \
"tftp ${loadaddr} /tftpboot/aristainetos/env.txt;" \
"env import -t ${loadaddr}\0" \
"addmisc=setenv bootargs ${bootargs} maxcpus=1 loglevel=8\0" \
"bootargs_defaults=setenv bootargs ${console} ${mtdoops} " \
"${optargs}\0" \
"net_args=run bootargs_defaults;setenv bootargs ${bootargs} " \
"root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
"${hostname}:${netdev}:off\0" \
"net_nfs=run load_kernel load_fdt;run net_args addmtd addmisc;" \
"run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"uboot=/tftpboot/aristainetos/u-boot.imx\0" \
"load_uboot=tftp ${loadaddr} ${uboot}\0" \
"uboot_sz=c0000\0" \
"upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
"mw.b 10200000 0x00 ${uboot_sz};" \
"run load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
"run mmcargs addmtd addmisc set_fit_default;" \
"bootm ${fit_addr_r}\0" \
"mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
"${fit_file}\0" \
"mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
"${uboot}\0" \
"mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
"setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
"setexpr uboot_maxsize ${uboot_sz} - 400;" \
"mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
"run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
"sf write ${loadaddr} 400 ${filesize};" \
"sf read 10200000 400 ${uboot_sz};" \
"cmp.b ${loadaddr} 10200000 bc000\0" \
"ubi_prep=ubi part ubi 2048;ubifsmount ubi:kernel\0" \
"load_kernel_ubi=ubifsload ${kernel_addr_r} uImage\0" \
"load_fdt_ubi=ubifsload ${fdt_addr_r} aristainetos.dtb\0" \
"ubi_nfs=run ubiprep load_kernel_ubi load_fdt_ubi;" \
"run net_args addmtd addmisc;run fdt_setup;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"rootfsname=rootfs\0" \
"ubi_args=run bootargs_defaults;setenv bootargs ${bootargs} " \
"ubi.mtd=0,2048 root=ubi0:${rootfsname} rootfstype=ubifs " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
"${hostname}:${netdev}:off\0" \
"ubi_ubi=run ubi_prep load_kernel_ubi load_fdt_ubi;" \
"run bootargs_defaults ubi_args addmtd addmisc;" \
"run fdt_setup;bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"ubirootfs_file=/tftpboot/aristainetos/rootfs-minimal.ubifs\0" \
"upd_ubirootfs=run ubi_prep;tftp ${loadaddr} ${ubirootfs_file};" \
"ubi write ${loadaddr} rootfs ${filesize}\0" \
"ksz=800000\0" \
"rootsz=2000000\0" \
"usersz=8000000\0" \
"ubi_make=run ubi_prep;ubi create kernel ${ksz};" \
"ubi create rootfs ${rootsz};ubi create userfs ${usersz}\0"
"sf read ${cmp_buf} 400 ${uboot_sz};" \
"cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
"ubiargs=setenv bootargs console=${console},${baudrate} " \
"ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " \
"ubiboot=echo Booting from ubi ...; " \
"run ubiargs addmtd addmisc set_fit_default;" \
"bootm ${fit_addr_r}\0" \
"ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \
"ubifsload ${fit_addr_r} /boot/system.itb; " \
"imi ${fit_addr_r}\0 " \
"rescueargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/ram rw\0 " \
"rescueboot=echo Booting rescue system from NOR ...; " \
"run rescueargs addmtd addmisc set_fit_default;" \
"bootm ${fit_addr_r}\0" \
"rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
"${rescue_sys_length}; imi ${fit_addr_r}\0 "
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
"if mmc rescan; then " \
"run mmcboot;" \
"else run ubi_ubi; fi"
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run mmc_load_fit; then " \
"run mmcboot; " \
"else " \
"if run ubifs_load_fit; then " \
"run ubiboot; " \
"else " \
"if run rescue_load_fit; then " \
"run rescueboot; " \
"else " \
"echo RESCUE SYSTEM BOOT " \
"FAILURE;" \
"fi; " \
"fi; " \
"fi; " \
"fi; " \
"else " \
"if run ubifs_load_fit; then " \
"run ubiboot; " \
"else " \
"if run rescue_load_fit; then " \
"run rescueboot; " \
"else " \
"echo RESCUE SYSTEM BOOT FAILURE;" \
"fi; " \
"fi; " \
"fi"
#define CONFIG_ARP_TIMEOUT 200UL
@ -227,8 +250,8 @@
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SECT_SIZE (0x010000)
#define CONFIG_ENV_OFFSET (0x0c0000)
#define CONFIG_ENV_OFFSET_REDUND (0x0d0000)
#define CONFIG_ENV_OFFSET (0x0d0000)
#define CONFIG_ENV_OFFSET_REDUND (0x0e0000)
#define CONFIG_OF_LIBFDT
@ -289,9 +312,6 @@
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:-(ubi)"
#define CONFIG_MTD_UBI_FASTMAP
#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1
@ -321,5 +341,4 @@
#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#endif /* __ARISTAINETOS_CONFIG_H */

158
include/configs/cm_fx6.h
View file

@ -103,97 +103,98 @@
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel=uImage-cm-fx6\0" \
"stdin=serial,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0" \
"panel=HDMI\0" \
"autoload=no\0" \
"kernel=uImage-cm-fx6\0" \
"script=boot.scr\0" \
"dtb=cm-fx6.dtb\0" \
"bootm_low=18000000\0" \
"loadaddr=0x10800000\0" \
"fdtaddr=0x11000000\0" \
"console=ttymxc3,115200\0" \
"ethprime=FEC0\0" \
"bootscr=boot.scr\0" \
"bootm_low=18000000\0" \
"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
"fdtfile=cm-fx6.dtb\0" \
"doboot=bootm ${loadaddr}\0" \
"loadfdt=false\0" \
"doloadfdt=false\0" \
"setboottypez=setenv kernel zImage-cm-fx6;" \
"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
"setenv loadfdt true;\0" \
"setenv doloadfdt true;\0" \
"setboottypem=setenv kernel uImage-cm-fx6;" \
"setenv doboot bootm ${loadaddr};" \
"setenv loadfdt false;\0"\
"run_eboot=echo Starting EBOOT ...; "\
"mmc dev ${mmcdev} && " \
"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
"mmcdev=2\0" \
"setenv doloadfdt false;\0"\
"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
"loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
"mmcbootscript=echo Running bootscript from mmc ...; "\
"source ${loadaddr}\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=${mmcroot} " \
"${video}\0" \
"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"run doboot\0" \
"satadev=0\0" \
"sataroot=/dev/sda2 rw rootwait\0" \
"sataargs=setenv bootargs console=${console} " \
"root=${sataroot} " \
"${video}\0" \
"loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \
"satabootscript=echo Running bootscript from sata ...; " \
"source ${loadaddr}\0" \
"sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \
"sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \
"sataboot=echo Booting from sata ...; "\
"run sataargs; " \
"run doboot\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"nandrootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
"${video}\0" \
"sataargs=setenv bootargs console=${console} root=${sataroot} " \
"${video}\0" \
"nandargs=setenv bootargs console=${console} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype} " \
"${video}\0" \
"nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 0 780000; " \
"if ${loadfdt}; then " \
"nandboot=if run nandloadkernel; then " \
"run nandloadfdt;" \
"fi; " \
"run doboot\0" \
"boot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"if run loadmmcbootscript; then " \
"run mmcbootscript;" \
"else " \
"if run mmcloadkernel; then " \
"if ${loadfdt}; then " \
"run mmcloadfdt;" \
"fi;" \
"run mmcboot;" \
"fi;" \
"fi;" \
"run setboottypem;" \
"run storagebootcmd;" \
"run setboottypez;" \
"run storagebootcmd;" \
"fi;\0" \
"run_eboot=echo Starting EBOOT ...; "\
"mmc dev 2 && " \
"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
"loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\
"loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\
"loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \
"bootscript=echo Running bootscript from ${storagetype} ...;" \
"source ${loadaddr};\0" \
"nandloadkernel=nand read ${loadaddr} 0 780000;\0" \
"nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
"setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \
"setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \
"setupnandboot=setenv storagetype nand;\0" \
"setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \
"storagebootcmd=echo Booting from ${storagetype} ...;" \
"run ${storagetype}args; run doboot;\0" \
"trybootk=if run loadkernel; then " \
"if ${doloadfdt}; then " \
"run loadfdt;" \
"fi;" \
"if sata init; then " \
"if run loadsatabootscript; then " \
"run satabootscript;" \
"else "\
"if run sataloadkernel; then " \
"if ${loadfdt}; then " \
"run sataloadfdt; " \
"fi;" \
"run sataboot;" \
"fi;" \
"fi;" \
"run storagebootcmd;" \
"fi;\0" \
"trybootsmz=if run loadscript; then " \
"run bootscript;" \
"fi;" \
"run nandboot\0"
"run setboottypem;" \
"run trybootk;" \
"run setboottypez;" \
"run trybootk;\0"
#define CONFIG_BOOTCOMMAND \
"run setboottypem; run boot"
"run setupmmcboot;" \
"mmc dev ${storagedev};" \
"if mmc rescan; then " \
"run trybootsmz;" \
"fi;" \
"run setupusbboot;" \
"if usb start; then "\
"if run loadscript; then " \
"run bootscript;" \
"fi;" \
"fi;" \
"run setupsataboot;" \
"if sata init; then " \
"run trybootsmz;" \
"fi;" \
"run setupnandboot;" \
"run nandboot;"
#define CONFIG_PREBOOT "usb start"
/* SPI */
#define CONFIG_SPI
@ -243,6 +244,9 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
#define CONFIG_SYS_STDIO_DEREGISTER
/* I2C */
#define CONFIG_CMD_I2C
@ -281,7 +285,7 @@
/* misc */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_STACKSIZE (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
#define CONFIG_OF_BOARD_SETUP
@ -296,4 +300,24 @@
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#define CONFIG_SPL_SPI_LOAD
/* Display */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_CONSOLE_MUX
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SOURCE
#define CONFIG_CMD_BMP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif /* __CONFIG_CM_FX6_H */

1
include/configs/cm_t35.h
View file

@ -310,6 +310,7 @@
#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SOURCE
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_SCF0403_LCD

8
include/configs/imx6_spl.h
View file

@ -61,11 +61,19 @@
#define CONFIG_SPL_LIBDISK_SUPPORT
#endif
#if defined(CONFIG_MX6SX)
#define CONFIG_SPL_BSS_START_ADDR 0x88200000
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_SPL_MALLOC_START 0x88300000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */
#define CONFIG_SYS_TEXT_BASE 0x87800000
#else
#define CONFIG_SPL_BSS_START_ADDR 0x18200000
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
#define CONFIG_SYS_SPL_MALLOC_START 0x18300000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */
#define CONFIG_SYS_TEXT_BASE 0x17800000
#endif
#endif
#endif

2
include/configs/mx6slevk.h
View file

@ -198,7 +198,7 @@
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#else
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_ENV_IS_IN_MMC
#endif

9
include/configs/mx6sxsabresd.h
View file

@ -18,6 +18,12 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#ifdef CONFIG_SPL
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
#endif
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@ -28,7 +34,6 @@
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
@ -255,7 +260,7 @@
#define FSL_QSPI_FLASH_NUM 2
#endif
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC

11
include/configs/ot1200.h
View file

@ -108,6 +108,16 @@
#endif
/* SPL */
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#define CONFIG_SPL_SPI_LOAD
#endif
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
@ -159,7 +169,6 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

319
include/configs/platinum.h Normal file
View file

@ -0,0 +1,319 @@
/*
* Copyright (C) 2014, Barco (www.barco.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PLATINUM_CONFIG_H__
#define __PLATINUM_CONFIG_H__
#define CONFIG_SYS_GENERIC_BOARD
/* SPL */
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
/* Location in NAND to read U-Boot from */
#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024)
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
/*
* Console configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FUSE
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_TIME
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_USB
/*
* Hardware configuration
*/
/* GPIO config */
#define CONFIG_MXC_GPIO
/* UART config */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_BAUDRATE 115200
#define CONFIG_CONS_INDEX 1
/* I2C config */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC config */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_DOS_PARTITION
/* Ethernet config */
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_PHYLIB
/* USB config */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
/* Memory config */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#ifndef PHYS_SDRAM_SIZE
#define PHYS_SDRAM_SIZE (1024 << 20)
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_CMD_NAND
/* NAND config */
#define CONFIG_NAND_MXS
#ifndef CONFIG_SYS_NAND_MAX_CHIPS
#define CONFIG_SYS_NAND_MAX_CHIPS 2
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA config, needed for GPMI/MXS NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
/* Fuse support */
#define CONFIG_MXC_OCOTP
/* Environment in NAND */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (16 << 20)
#define CONFIG_ENV_SECT_SIZE (128 << 10)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10))
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#else /* CONFIG_CMD_NAND */
/* Environment in MMC */
#define CONFIG_ENV_SIZE (8 << 10)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif /* CONFIG_CMD_NAND */
/*
* U-Boot configuration
*/
/* Console boot messages */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* Tag config */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
/* Board startup config */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Device tree support */
#define CONFIG_OF_LIBFDT
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
PHYS_SDRAM_SIZE - (12 << 20))
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "run bootubi_scr"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_PREBOOT
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* MTD/UBI/UBIFS config */
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#if (CONFIG_SYS_NAND_MAX_CHIPS == 1)
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:14M(spl),2M(uboot)," \
"512k(env1),512k(env2),-(ubi)"
#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2)
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:14M(spl),2M(uboot)," \
"512k(env1),512k(env2),495M(ubi0)," \
"14M(res0),2M(res1)," \
"512k(res2),512k(res3),-(ubi1)"
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMD_CACHE
#endif
/*
* Environment configuration
*/
#if (CONFIG_SYS_NAND_MAX_CHIPS == 1)
#define CONFIG_COMMON_ENV_UBI \
"setubipartition=env set ubipartition ubi\0" \
"setubirfs=env set ubirfs $ubipartition:rootfs$boot_vol\0"
#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2)
#define CONFIG_COMMON_ENV_UBI \
"setubipartition=env set ubipartition ubi$boot_vol\0" \
"setubirfs=env set ubirfs ubi0:rootfs\0"
#endif
#define CONFIG_COMMON_ENV_MISC \
"user=user\0" \
"project="CONFIG_PLATINUM_PROJECT"\0" \
"uimage=uImage\0" \
"dtb="CONFIG_PLATINUM_CPU"-platinum-"CONFIG_PLATINUM_PROJECT".dtb\0" \
"serverip=serverip\0" \
"memaddrlinux=0x10800000\0" \
"memaddrsrc=0x11000000\0" \
"memaddrdtb=0x12000000\0" \
"console=ttymxc0\0" \
"baudrate=115200\0" \
"boot_scr=boot.uboot\0" \
"boot_vol=0\0" \
"mtdids="MTDIDS_DEFAULT"\0" \
"mtdparts="MTDPARTS_DEFAULT"\0" \
"mmcfs=ext2\0" \
"mmcrootpart=1\0" \
\
"setnfspath=env set nfspath /home/nfs/$user/$project/root\0" \
"settftpfilelinux=env set tftpfilelinux $user/$project/$uimage\0" \
"settftpfiledtb=env set tftpfiledtb $user/$project/$dtb\0" \
"setubifilelinux=env set ubifilelinux boot/$uimage\0" \
"setubipfiledtb=env set ubifiledtb boot/$dtb\0" \
"setmmcrootdev=env set mmcrootdev /dev/mmcblk0p$mmcrootpart\0" \
"setmmcfilelinux=env set mmcfilelinux /boot/$uimage\0" \
"setmmcfiledtb=env set mmcfiledtb /boot/$dtb\0" \
\
"loadtftpkernel=dhcp $memaddrlinux $tftpfilelinux\0" \
"loadtftpdtb=dhcp $memaddrdtb $tftpfiledtb\0" \
"loadubikernel=ubifsload $memaddrlinux $ubifilelinux\0" \
"loadubidtb=ubifsload $memaddrdtb $ubifiledtb\0" \
"loadmmckernel=${mmcfs}load mmc 0:$mmcrootpart $memaddrlinux " \
"$mmcfilelinux\0" \
"loadmmcdtb=${mmcfs}load mmc 0:$mmcrootpart $memaddrdtb " \
"$mmcfiledtb\0" \
\
"ubipart=ubi part $ubipartition\0" \
"ubimount=ubifsmount $ubirfs\0" \
\
"setbootargscommon=env set bootargs $bootargs " \
"console=$console,$baudrate enable_wait_mode=off\0" \
"setbootargsmtd=env set bootargs $bootargs $mtdparts\0" \
"setbootargsdhcp=env set bootargs $bootargs ip=dhcp\0" \
"setbootargsubirfs=env set bootargs $bootargs " \
"ubi.mtd=$ubipartition root=$ubirfs rootfstype=ubifs\0" \
"setbootargsnfsrfs=env set bootargs $bootargs root=/dev/nfs " \
"nfsroot=$serverip:$nfspath,v3,tcp\0" \
"setbootargsmmcrfs=env set bootargs $bootargs " \
"root=$mmcrootdev rootwait rw\0" \
\
"bootnet=run settftpfilelinux settftpfiledtb setnfspath " \
"setbootargscommon setbootargsmtd setbootargsdhcp " \
"setbootargsnfsrfs;" \
"run loadtftpkernel loadtftpdtb;" \
"bootm $memaddrlinux - $memaddrdtb\0" \
"bootnet_ubirfs=run settftpfilelinux settftpfiledtb;" \
"run setubipartition setubirfs;" \
"run setbootargscommon setbootargsmtd " \
"setbootargsubirfs;" \
"run loadtftpkernel loadtftpdtb;" \
"bootm $memaddrlinux - $memaddrdtb\0" \
"bootubi=run setubipartition setubirfs setubifilelinux " \
"setubipfiledtb;" \
"run setbootargscommon setbootargsmtd " \
"setbootargsubirfs;" \
"run ubipart ubimount loadubikernel loadubidtb;" \
"bootm $memaddrlinux - $memaddrdtb\0" \
"bootubi_scr=run setubipartition setubirfs;" \
"run ubipart ubimount;" \
"if ubifsload ${memaddrsrc} boot/${boot_scr}; " \
"then source ${memaddrsrc}; else run bootubi; fi\0" \
"bootmmc=run setmmcrootdev setmmcfilelinux setmmcfiledtb " \
"setbootargscommon setbootargsmmcrfs;" \
"run loadmmckernel loadmmcdtb;" \
"bootm $memaddrlinux - $memaddrdtb\0" \
\
"bootcmd="CONFIG_BOOTCOMMAND"\0"
#define CONFIG_COMMON_ENV_SETTINGS CONFIG_COMMON_ENV_MISC \
CONFIG_COMMON_ENV_UBI
#endif /* __PLATINUM_CONFIG_H__ */

31
include/configs/platinum_picon.h Normal file
View file

@ -0,0 +1,31 @@
/*
* Copyright (C) 2014, Barco (www.barco.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PLATINUM_PICON_CONFIG_H__
#define __PLATINUM_PICON_CONFIG_H__
#define CONFIG_PLATINUM_PICON
#define CONFIG_PLATINUM_BOARD "Barco Picon"
#define CONFIG_PLATINUM_PROJECT "picon"
#define CONFIG_PLATINUM_CPU "imx6dl"
#define CONFIG_MX6
#include <configs/platinum.h>
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_HOSTNAME picon
#define CONFIG_SYS_PROMPT "picon > "
#define CONFIG_PLATFORM_ENV_SETTINGS "\0"
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \
CONFIG_PLATFORM_ENV_SETTINGS
#endif /* __PLATINUM_PICON_CONFIG_H__ */

38
include/configs/platinum_titanium.h Normal file
View file

@ -0,0 +1,38 @@
/*
* Copyright (C) 2014, Barco (www.barco.com)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PLATINUM_TITANIUM_CONFIG_H__
#define __PLATINUM_TITANIUM_CONFIG_H__
#define CONFIG_PLATINUM_TITANIUM
#define CONFIG_PLATINUM_BOARD "Barco Titanium"
#define CONFIG_PLATINUM_PROJECT "titanium"
#define CONFIG_PLATINUM_CPU "imx6q"
#define CONFIG_MX6
#define PHYS_SDRAM_SIZE (512 << 20)
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#include <configs/platinum.h>
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_HOSTNAME titanium
#define CONFIG_SYS_PROMPT "titanium > "
#define CONFIG_PLATFORM_ENV_SETTINGS "\0"
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \
CONFIG_PLATFORM_ENV_SETTINGS
#endif /* __PLATINUM_TITANIUM_CONFIG_H__ */

2
include/configs/wandboard.h
View file

@ -175,7 +175,7 @@
"if i2c probe 0x10; then " \
"setenv bootargs ${bootargs} " \
"video=mxcfb${nextcon}:dev=lcd,800x480@60," \
"if=RGB666; " \
"if=RGB666,bpp=32; " \
"if test 0 -eq ${nextcon}; then " \
"setenv fbmem fbmem=10M; " \
"else " \

55
include/power/pfuze100_pmic.h
View file

@ -16,14 +16,34 @@ enum {
PFUZE100_SW1ABVOL = 0x20,
PFUZE100_SW1ABSTBY = 0x21,
PFUZE100_SW1ABOFF = 0x22,
PFUZE100_SW1ABMODE = 0x23,
PUZE_100_SW1ABCONF = 0x24,
PFUZE100_SW1CVOL = 0x2e,
PFUZE100_SW1CSTBY = 0x2f,
PFUZE100_SW1COFF = 0x30,
PFUZE100_SW1CMODE = 0x31,
PFUZE100_SW1CCONF = 0x32,
PFUZE100_SW2VOL = 0x35,
PFUZE100_SW2STBY = 0x36,
PFUZE100_SW2OFF = 0x37,
PFUZE100_SW2MODE = 0x38,
PFUZE100_SW2CONF = 0x39,
PFUZE100_SW3AVOL = 0x3c,
PFUZE100_SW3ASTBY = 0x3D,
PFUZE100_SW3AOFF = 0x3E,
PFUZE100_SW3AMODE = 0x3F,
PFUZE100_SW3ACONF = 0x40,
PFUZE100_SW3BVOL = 0x43,
PFUZE100_SW3BSTBY = 0x44,
PFUZE100_SW3BOFF = 0x45,
PFUZE100_SW3BMODE = 0x46,
PFUZE100_SW3BCONF = 0x47,
PFUZE100_SW4VOL = 0x4a,
PFUZE100_SW4STBY = 0x4b,
PFUZE100_SW4OFF = 0x4c,
PFUZE100_SW4MODE = 0x4d,
PFUZE100_SW4CONF = 0x4e,
PFUZE100_SWBSTCON1 = 0x66,
PFUZE100_VREFDDRCON = 0x6a,
PFUZE100_VSNVSVOL = 0x6b,
@ -41,6 +61,8 @@ enum {
* Buck Regulators
*/
#define PFUZE100_SW1ABC_SETP(x) ((x - 3000) / 250)
/* SW1A/B/C Output Voltage Configuration */
#define SW1x_0_300V 0
#define SW1x_0_325V 1
@ -177,5 +199,38 @@ enum {
#define SWBST_MODE_AUTO (2 << 2)
#define SWBST_MODE_APS (2 << 3)
/*
* Regulator Mode Control
*
* OFF: The regulator is switched off and the output voltage is discharged.
* PFM: In this mode, the regulator is always in PFM mode, which is useful
* at light loads for optimized efficiency.
* PWM: In this mode, the regulator is always in PWM mode operation
* regardless of load conditions.
* APS: In this mode, the regulator moves automatically between pulse
* skipping mode and PWM mode depending on load conditions.
*
* SWxMODE[3:0]
* Normal Mode | Standby Mode | value
* OFF OFF 0x0
* PWM OFF 0x1
* PFM OFF 0x3
* APS OFF 0x4
* PWM PWM 0x5
* PWM APS 0x6
* APS APS 0x8
* APS PFM 0xc
* PWM PFM 0xd
*/
#define OFF_OFF 0x0
#define PWM_OFF 0x1
#define PFM_OFF 0x3
#define APS_OFF 0x4
#define PWM_PWM 0x5
#define PWM_APS 0x6
#define APS_APS 0x8
#define APS_PFM 0xc
#define PWM_PFM 0xd
int power_pfuze100_init(unsigned char bus);
#endif

11
include/splash.h
View file

@ -22,7 +22,18 @@
#ifndef _SPLASH_H_
#define _SPLASH_H_
enum splash_storage {
SPLASH_STORAGE_NAND,
SPLASH_STORAGE_SF,
};
struct splash_location {
char *name;
enum splash_storage storage;
u32 offset; /* offset from start of storage */
};
int splash_source_load(struct splash_location *locations, uint size);
int splash_screen_prepare(void);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN

2
tools/imximage.c
View file

@ -38,6 +38,7 @@ static table_entry_t imximage_boot_offset[] = {
{FLASH_OFFSET_SATA, "sata", "SATA Disk", },
{FLASH_OFFSET_SD, "sd", "SD Card", },
{FLASH_OFFSET_SPI, "spi", "SPI Flash", },
{FLASH_OFFSET_QSPI, "qspi", "QSPI NOR Flash",},
{-1, "", "Invalid", },
};
@ -52,6 +53,7 @@ static table_entry_t imximage_boot_loadsize[] = {
{FLASH_LOADSIZE_SATA, "sata", "SATA Disk", },
{FLASH_LOADSIZE_SD, "sd", "SD Card", },
{FLASH_LOADSIZE_SPI, "spi", "SPI Flash", },
{FLASH_LOADSIZE_QSPI, "qspi", "QSPI NOR Flash",},
{-1, "", "Invalid", },
};

2
tools/imximage.h
View file

@ -29,6 +29,7 @@
#define FLASH_OFFSET_ONENAND 0x100
#define FLASH_OFFSET_NOR 0x1000
#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_QSPI 0x1000
/* Initial Load Region Size */
#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
@ -39,6 +40,7 @@
#define FLASH_LOADSIZE_ONENAND 0x400
#define FLASH_LOADSIZE_NOR 0x0 /* entire image */
#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
#define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
#define IVT_HEADER_TAG 0xD1
#define IVT_VERSION 0x40

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tools/logos/compulab.bmp Normal file
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Width:  |  Height:  |  Size: 31 KiB

6
tools/mxsboot.c
View file

@ -142,6 +142,9 @@ static inline uint32_t mx28_nand_get_ecc_strength(uint32_t page_data_size,
if (page_oob_size == 218)
return 16;
if (page_oob_size == 224)
return 16;
}
return 0;
@ -269,6 +272,9 @@ static struct mx28_nand_fcb *mx28_nand_get_fcb(uint32_t size)
} else if (nand_oobsize == 218) {
fcb->ecc_block_n_ecc_type = 8;
fcb->ecc_block_0_ecc_type = 8;
} else if (nand_oobsize == 224) {
fcb->ecc_block_n_ecc_type = 8;
fcb->ecc_block_0_ecc_type = 8;
}
}