mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
commit
fc9b0b8043
10 changed files with 194 additions and 7 deletions
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@ -53,5 +53,10 @@ enum {
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MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
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MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
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MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
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MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
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MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
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MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
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};
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#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
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@ -20,6 +20,8 @@
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#include <fsl_esdhc.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <usb.h>
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#include <usb/ehci-fsl.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -238,6 +240,48 @@ static int setup_fec(void)
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}
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#endif
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#ifdef CONFIG_USB_EHCI_MX6
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#define USB_OTHERREGS_OFFSET 0x800
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#define UCTRL_PWR_POL (1 << 9)
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static iomux_v3_cfg_t const usb_otg_pads[] = {
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/* OTG1 */
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MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* OTG2 */
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MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
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};
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static void setup_usb(void)
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{
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imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
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ARRAY_SIZE(usb_otg_pads));
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}
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int board_usb_phy_mode(int port)
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{
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if (port == 1)
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return USB_INIT_HOST;
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else
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return usb_phy_mode(port);
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}
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int board_ehci_hcd_init(int port)
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{
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u32 *usbnc_usb_ctrl;
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if (port > 1)
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return -EINVAL;
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usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
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port * 4);
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/* Set Power polarity */
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setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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@ -256,6 +300,11 @@ int board_init(void)
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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#ifdef CONFIG_USB_EHCI_MX6
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setup_usb();
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#endif
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return 0;
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}
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@ -26,6 +26,8 @@
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include "../common/pfuze.h"
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#include <usb.h>
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#include <usb/ehci-fsl.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -212,6 +214,49 @@ int power_init_board(void)
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return 0;
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}
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#ifdef CONFIG_USB_EHCI_MX6
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#define USB_OTHERREGS_OFFSET 0x800
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#define UCTRL_PWR_POL (1 << 9)
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static iomux_v3_cfg_t const usb_otg_pads[] = {
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/* OGT1 */
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MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* OTG2 */
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MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
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};
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static void setup_usb(void)
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{
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imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
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ARRAY_SIZE(usb_otg_pads));
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}
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int board_usb_phy_mode(int port)
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{
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if (port == 1)
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return USB_INIT_HOST;
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else
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return usb_phy_mode(port);
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}
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int board_ehci_hcd_init(int port)
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{
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u32 *usbnc_usb_ctrl;
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if (port > 1)
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return -EINVAL;
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usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
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port * 4);
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/* Set Power polarity */
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setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
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return 0;
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}
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#endif
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int board_phy_config(struct phy_device *phydev)
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{
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/*
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@ -242,6 +287,10 @@ int board_early_init_f(void)
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/* Active high for ncp692 */
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gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
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#ifdef CONFIG_USB_EHCI_MX6
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setup_usb();
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#endif
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return 0;
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}
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@ -322,7 +371,6 @@ int board_mmc_init(bd_t *bis)
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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@ -544,10 +544,35 @@ struct dfu_entity *dfu_get_entity(int alt)
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int dfu_get_alt(char *name)
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{
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struct dfu_entity *dfu;
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char *str;
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list_for_each_entry(dfu, &dfu_list, list) {
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if (!strncmp(dfu->name, name, strlen(dfu->name)))
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return dfu->alt;
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if (dfu->name[0] != '/') {
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if (!strncmp(dfu->name, name, strlen(dfu->name)))
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return dfu->alt;
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} else {
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/*
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* One must also consider absolute path
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* (/boot/bin/uImage) available at dfu->name when
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* compared "plain" file name (uImage)
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*
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* It is the case for e.g. thor gadget where lthor SW
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* sends only the file name, so only the very last part
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* of path must be checked for equality
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*/
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str = strstr(dfu->name, name);
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if (!str)
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continue;
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/*
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* Check if matching substring is the last element of
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* dfu->name (uImage)
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*/
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if (strlen(dfu->name) ==
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((str - dfu->name) + strlen(name)))
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return dfu->alt;
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}
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}
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return -ENODEV;
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@ -971,7 +971,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
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qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
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qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
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QH_ENDPT1_EPS(USB_SPEED_HIGH));
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qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
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qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
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qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
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qh_list->qh_overlay.qt_token =
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@ -160,7 +160,7 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
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val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
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__raw_writel(val, phy_ctrl);
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return val & USBPHY_CTRL_OTG_ID;
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return 0;
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}
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/* Base address for this IP block is 0x02184800 */
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@ -193,6 +193,28 @@ static void usb_oc_config(int index)
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__raw_writel(val, ctrl);
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}
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int usb_phy_mode(int port)
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{
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void __iomem *phy_reg;
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void __iomem *phy_ctrl;
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u32 val;
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phy_reg = (void __iomem *)phy_bases[port];
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phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
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val = __raw_readl(phy_ctrl);
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if (val & USBPHY_CTRL_OTG_ID)
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return USB_INIT_DEVICE;
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else
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return USB_INIT_HOST;
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}
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int __weak board_usb_phy_mode(int port)
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{
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return usb_phy_mode(port);
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}
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int __weak board_ehci_hcd_init(int port)
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{
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return 0;
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@ -221,7 +243,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
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usb_power_config(index);
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usb_oc_config(index);
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usb_internal_phy_clock_gate(index, 1);
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type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
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usb_phy_enable(index, ehci);
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type = board_usb_phy_mode(index);
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
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@ -209,6 +209,20 @@
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#endif
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/* USB Configs */
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#define CONFIG_CMD_USB
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_MX6
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#define CONFIG_USB_STORAGE
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#endif
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#define CONFIG_SYS_FSL_USDHC_NUM 3
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#if defined(CONFIG_ENV_IS_IN_MMC)
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#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
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@ -198,6 +198,20 @@
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_CMD_USB
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_MX6
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#define CONFIG_USB_STORAGE
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#endif
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#define CONFIG_CMD_PCI
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#ifdef CONFIG_CMD_PCI
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#define CONFIG_PCI
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@ -280,7 +280,9 @@ struct usb_ehci {
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#define MXC_EHCI_IPPUE_DOWN (1 << 10)
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#define MXC_EHCI_IPPUE_UP (1 << 11)
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int usb_phy_mode(int port);
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/* Board-specific initialization */
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int board_ehci_hcd_init(int port);
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int board_usb_phy_mode(int port);
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#endif /* _EHCI_FSL_H */
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@ -11,6 +11,7 @@ clear
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COLOUR_RED="\33[31m"
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COLOUR_GREEN="\33[32m"
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COLOUR_ORANGE="\33[33m"
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COLOUR_DEFAULT="\33[0m"
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DIR=./
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@ -59,8 +60,15 @@ ums_test_file () {
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fi
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cp ./$1 $MNT_DIR
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umount $MNT_DIR
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while true; do
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umount $MNT_DIR > /dev/null 2>&1
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if [ $? -eq 0 ]; then
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break
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fi
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printf "$COLOUR_ORANGE\tSleeping to wait for umount...$COLOUR_DEFAULT\n"
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sleep 1
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done
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echo -n "TX: "
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calculate_md5sum $1
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