Commit graph

2774 commits

Author SHA1 Message Date
Mateusz Kulikowski
e162c6b1a7 usb: Rename ehci-fsl.h to ehci-ci.h
Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.

This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
2016-04-01 17:18:10 -04:00
Rai Harninder
ed2530d096 armv8/ls2080ardb: Enable VID support
This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.

Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:24 -07:00
Saksham Jain
85bb389654 SECURE BOOT: Change fsl_secboot_validate func to pass image addr
Use a pointer to pass image address to fsl_secboot_validate(),
instead of using environmental variable "img_addr".

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:23 -07:00
Saksham Jain
c4666cf695 SECURE BOOT: Halt execution when secure boot fail
In case of fatal failure during secure boot execution (e.g. header
not found), reset is asserted to stop execution. If the RESET_REQ
is not tied to HRESET, this allows the execution to continue.

Add esbh_halt() after the reset to make sure execution stops.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:23 -07:00
Saksham Jain
fcfdb6d580 armv8: ls2080rdb: ls2080qds: Add secure boot support
Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).

Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:20 -07:00
Saksham Jain
fd6dbc98a7 armv8: fsl-lsch3: Add new header for secure boot
For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.

Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:20 -07:00
Fabio Estevam
779594d335 mx6sabresd: Use VESA 1024x768 timings
VESA 1024x768 results in much more accurate timings.

Based on the patch from Soeren Moch for the tbs2910 board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-25 14:05:24 +01:00
Stuart Yoder
e91f1deca5 armv8: ls2080a: Update fdt path for fsl-mc node
The fsl-mc node has been moved under /soc, so update
the path references accordingly.  Backwards compatibility
is retained for /fsl-mc.

Delete backwards compatibility for the completely obsolete
/fsl,dprc@0.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-24 11:43:31 -07:00
Wenbin Song
ec44289db5 armv8/ls1043aqds: Return i2c mux to default chennel
Return i2c mux to the default channel after accessing retimer.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:15 -07:00
Wenbin Song
1be8d10be4 freescale: vid: Return i2c mux to default channel
IR chip is on one of the channels on multiplexed I2C-bus.
Reset to default channel after accessing.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:15 -07:00
Prabhakar Kushwaha
0f4b82a555 armv8: ls2085a: Remove phy configuration from QDS and RDB
As phy_connect and phy_config are being called from DPAA2 driver.
Remove calling of mentioned function from board file.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:14 -07:00
Shaohui Xie
abc7d0f75c armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Simon Glass
73223f0e1b Kconfig: Move CONFIG_FIT and related options to Kconfig
There are already two FIT options in Kconfig but the CONFIG options are
still in the header files. We need to do a proper move to fix this.

Move these options to Kconfig and tidy up board configuration:

   CONFIG_FIT
   CONFIG_OF_BOARD_SETUP
   CONFIG_OF_SYSTEM_SETUP
   CONFIG_FIT_SIGNATURE
   CONFIG_FIT_BEST_MATCH
   CONFIG_FIT_VERBOSE
   CONFIG_OF_STDOUT_VIA_ALIAS
   CONFIG_RSA

Unfortunately the first one is a little complicated. We need to make sure
this option is not enabled in SPL by this change. Also this option is
enabled automatically in the host builds by defining CONFIG_FIT in the
image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
be used in files that are built on the host but must also build for U-Boot
and SPL.

Note: Masahiro's moveconfig.py script is amazing.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add microblaze change, various configs/ re-applies]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-14 19:18:07 -04:00
Fabio Estevam
ae765f3a82 mx6slevk: Fix the power up of the Ethernet PHY
GPIO4_21 is the LAN8720 power pin, not the LAN8720 reset pin.

Fix that, so that we can have Ethernet functional again.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-13 09:50:02 -04:00
Fabio Estevam
9feec162af mx6qarm2: Update maintainer's emails
Use the new NXP emails.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-02 14:49:13 +01:00
Fabio Estevam
047cc75df6 MAINTAINERS: Update Peng Fan's email address
Use Peng Fan's new NXP email address in MAINTAINERS files.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2016-03-02 14:48:52 +01:00
Alison Wang
a08b1921b4 armv7: ls102xa: Move smmu and stream id initialization into the common soc code
The initialization for smmu and stream id is moved into the common soc
code.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:15 -08:00
Zhao Qiang
a12a0ef89e board: ls1043ardb: Modify pin-muxing code for USB and QE-HDLC
QE-HDLC and USB multi-use the pins, modify the pin-muxing code
for them, when set "hwconfig=qe-hdlc" in uboot, assign the pins
to QE-HDLC, if not, assgin it to USB

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:15 -08:00
Zhao Qiang
110171dcef board: ls1043rdb: Move USB muxing config to config_board_mux
Pin-muxing code should be in config_board_mux, move USB muxing
config to config_board_mux.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:15 -08:00
Zhao Qiang
d3e6d30cef board: ls1043ardb: Add micro QE support for ls1043ardb
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:14 -08:00
Qianyu Gong
5a7c40bea6 armv8/ls1043aqds: Add USB support for ls1043aqds
Add USB XHCI support for ls1043qds board.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:14 -08:00
Qianyu Gong
2459afb1a7 qe: move drivers/qe/qe.h to include/fsl_qe.h
As the QE firmware struct is shared with Fman, move the header file
out of drivers/qe/.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:51:13 -08:00
Alison Wang
70097027d2 arm: ls1021a: Add QSPI or IFC support in SD boot for LS1021AQDS board
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported
in SD boot now. For the customer's demand, QSPI needs to be supported
in SD boot too.

This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021aqds_sdcard_ifc_defconfig
is used to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig
is used to support QSPI in SD boot.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-02-24 08:40:56 -08:00
Tom Rini
595af9db24 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-02-21 07:56:16 -05:00
Fabio Estevam
2b8e8d2671 mx7dsabresd: Make 'ums' command functional
When running the 'ums' command we get:

=> ums 0 mmc 0
UMS: disk start sector: 0x0, count: 0xe18000
g_dnl_register: failed!, error: -22
ERROR: g_dnl_register failed
at common/cmd_usb_mass_storage.c:107/do_usb_mass_storage()

Fix this by initializing USB OTG1 port as USB device mode instead of host.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-02-21 11:13:27 +01:00
Fabio Estevam
88e826be45 mx7dsabresd: Use Adrian's NXP email address
Use the new NXP email address for the board maintainer.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-02-21 11:12:32 +01:00
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Peng Fan
fb0d042814 imx: mx6: implement board_mmc_get_env_dev
Implement board_mmc_get_env_dev for the boards.

Following is examples:
SD1/SD2/SD3: return devno;
SD2/SD3: return devno - 1;
SD2/SD4: if (devno == 2), return dev - 2; return dev - 1;

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-04 10:13:53 +01:00
Peng Fan
62d8cce9f3 imx: mx7dsabresd: move mmc_get_env_devno to soc code
Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to
match the one in common/env_mmc.c.
Introduce a weak function board_mmc_get_env_dev. Different
boards can implement this according to sdhc controller which
is used by the board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-04 10:13:45 +01:00
Ye Li
85eb095216 imx: mx6sxsabresd: Add MCIMX28LCD display support
The i.MX6SX SABRESD board supports MCIMX28LCD (800x480x24) at LCDIF1
port, enable this display feature by adding relevant BSP codes
and configurations.

Signed-off-by: Ye Li <ye.li@nxp.com>
2016-02-02 21:27:15 +01:00
Ye Li
214c3f0f99 imx: MX6DQ{P}/DL:SABRESD Fix bmode eMMC failure
The BOOTCFG value used by bmode for SABRESD eMMC boot are actually for SD card.
Fixed the value to correct one.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-02-02 21:22:04 +01:00
Fabio Estevam
529a671279 mx6slevk: Fix the reset delay for the the LAN8720 PHY
Since commit 59370f3fcd ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional.

This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.

According to the LAN8720 datasheet tpurstd (time that reset line should
stay asserted) is 25ms.

So do as suggested in order to have Ethernet working again.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-02-02 21:18:44 +01:00
Ye Li
cf94a3427a imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board
Initial version for mx6sx SABREAUTO board support with features:
PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.

Signed-off-by: Ye Li <ye.li@nxp.com>
2016-02-02 21:04:21 +01:00
Tom Rini
82d72a1b99 Merge branch 'master' of git://git.denx.de/u-boot-net 2016-01-28 18:42:10 -05:00
Bin Meng
9ccb309651 arm: ls1021atwr: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:44 -06:00
Bin Meng
c712df1d1d powerpc: p1010rdb: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:41 -06:00
Bin Meng
1adc09544f powerpc: mpc8548cds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:37 -06:00
Bin Meng
4521ae9dca powerpc: mpc8572ds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:33 -06:00
Bin Meng
98ae83b5e1 powerpc: c29xpcie: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:30 -06:00
Bin Meng
89c97842db powerpc: bsc9132qds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:27 -06:00
Tom Rini
cd85bec36d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-01-27 15:05:36 -05:00
Qianyu Gong
b0f20caf65 armv8/ls1043aqds: add QSPI boot support
Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:29:09 -08:00
Gong Qianyu
166ef1e90c armv8/ls1043aqds: add QSPI support in SD boot
QSPI and IFC are pin-multiplexed on LS1043A. So we use
ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:28:55 -08:00
Shaohui Xie
8c35cc3b7e armv8/ls1043aqds: Select lpuart pins of various muxes
Set Board Configuration Register to select the lpuart pins of various
muxes.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:13:12 -08:00
Aneesh Bansal
856b284617 secure_boot: change error handler for esbc_validate
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.

Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:13:03 -08:00
Aneesh Bansal
d041288586 secure_boot: enable chain of trust for ARM platforms
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
   bootdelay = 0 (To disable Boot Prompt)
   bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:49 -08:00
Aneesh Bansal
0a6b2714ad secure_boot: create function to determine boot mode
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-27 08:12:42 -08:00
Tom Rini
d82477748d Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2016-01-25 16:45:00 -05:00
Ying Zhang
2f66a828f7 powerpc/board/t4240rdb: Enable VID support
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory. These values
define the voltage requirements for the chip. u-boot reads
FUSESR and translates the values into the appropriate
commands to set the voltage output value of an external
voltage regulator.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 12:38:05 -08:00
Ying Zhang
cabe4d2f19 board/freescale/common: Check IR chip mode for VID support
IR chip on all the boards are required to be used in Intel mode
to support VID. VDD will not be adjusted if IR chip is used in
other modes.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 12:37:03 -08:00
Prabhakar Kushwaha
2c0d69713c powerpc: mpc85xx: Move set_liodns, setup_portals to common boot seq
Users migrating Freescale's PowerPC SoC U-Boot code to their custom
board, often overlook the need to execute set_liodns() and
setup_portals() being called by platform files.

So Move set_liodns() and setup_portals() to common u-boot boot
sequence

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 12:13:31 -08:00
Aneesh Bansal
b055a0fd86 SECURE BOOT: support for validation of dynamic image
Some images to be validated are relocated to a dynamic
address at run time. So, these addresses cannot be known
befor hand while signing the images and creating the header
offline.
So, support is required to pass the image address to the
validate function as an argument.
If an address is provided to the function, the address
field in Header is not read and is treated as a reserved
field.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:16 -08:00
Aneesh Bansal
6629261ddd SECURE BOOT: separate function created for signature
The code for image hash calculation, hash calculation from
RSA signature and comparison of hashes has been mobed to a
separate function.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:16 -08:00
Aneesh Bansal
94ba5e4140 SECURE BOOT: separate functions for reading keys
Separate functions are created for reading and checking the
sanity of Public keys:
- read_validate_single_key
- read_validate_ie_tbl
- read_validate_srk_table

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:16 -08:00
Aneesh Bansal
bc71f926e3 SECURE BOOT: change prototype of fsl_secboot_validate function
The prototype and defination of function fsl_secboot_validate
has been changed to support calling this function from another
function within u-boot.
Only two aruments needed:
1) header address - Mandatory
2) SHA256 string - optional

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:16 -08:00
Gong Qianyu
98d9aa4013 freescale/qixis: Add support for booting from SD/QSPI
1.Use "qixis_reset sd" to boot from SD
2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
3.Use "qixis_reset qspi" to boot from QSPI flash

On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
pin-multiplexed. So the switches are different between SD boot with
IFC support and SD boot with QSPI support. The default booting from
SD is with IFC support.

Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Shaohui Xie
58e4ad1dee armv8/ls1043aqds: Add support for >2GB memory
This patch also exposes the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:14 -08:00
Peng Fan
6e1a41cd6a imx: mx7dsabresd: support nand
Add pinmux settings.
Add related macro definitions.
Nand pin conflicts with emmc, so if want to enable nand, need to do
hardware rework. After hardware rework, define CONFIG_NAND_MXS in
board header file.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-24 12:09:44 +01:00
Fabio Estevam
4897d950b7 mx25pdk: Remove lowlevel_init.S file
As the lowlevel_init function is empty we should better
remove this assembly file entirely and use a dummy C
function instead.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-01-24 11:52:45 +01:00
Masahiro Yamada
61a4392a36 m68k: M54418TWR: drop board/freescale/m54418twr/config.mk
The board/freescale/m54418twr/config.mk defined TEXT_BASE, which has
the same value as CONFIG_SYS_TEXT_BASE.  The TEXT_BASE is referenced
by two files:
 - arch/m68k/cpu/mcf5445x/start.S and include/
 - include/configs/M54418TWR.h

Replace the references with CONFIG_SYS_TEXT_BASE and delete
board/freescale/m54418twr/config.mk.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Angelo Dureghello <angelo at sysam.it>
2016-01-20 10:19:34 -05:00
Masahiro Yamada
c6e18144b6 m68k: move CONFIG_SYS_TEXT_BASE to defconfig files
For historical reason, CONFIG_SYS_TEXT_BASE has been specified
in various ways:

[1] by board/${VENDOR}/${BOARD}/config.mk

[2] by CONFIG_SYS_EXTRA_OPTIONS
    (This was "options" field of boards.cfg before Kconfig conversion)

[3] by include/configs/${BOARD}.h

[4] by configs/${BOARD}_defconfig

Most of M68K boards use either [1] or [2], both of which we want to
deprecate.  Switch them into [4], which is the newest way (Kconfig).

We still allow [3] too, because it is still used by many boards and
we expect much time for conversion.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Angelo Dureghello <angelo at sysam.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-20 10:19:34 -05:00
Tom Rini
5b8031ccb4 Add more SPDX-License-Identifier tags
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19 08:31:21 -05:00
Ben Whitten
192bc6948b Fix GCC format-security errors and convert sprintfs.
With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.

Simple uses of sprintf are also converted to use strcpy.

Signed-off-by: Ben Whitten <ben.whitten@gmail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 22:11:34 -05:00
Stephen Warren
7c4213f6a5 block: pass block dev not num to read/write/erase()
This will allow the implementation to make use of data in the block_dev
structure beyond the base device number. This will be useful so that eMMC
block devices can encompass the HW partition ID rather than treating this
out-of-band. Equally, the existence of the priv field is crying out for
this patch to exist.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-13 21:05:18 -05:00
Fabio Estevam
c5f18a0b69 MAINTAINERS/mailmap: Update my email address
Update my email address to the NXP account.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-01-11 11:22:43 -05:00
Tom Rini
b685c7348c Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-01-08 10:18:18 -05:00
York Sun
2f231025bc MAINTAINERS, .mailmap: Update my email address
Change from yorksun@freescale.com to york.sun@nxp.com.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-01-08 10:15:46 -05:00
Ye.Li
7ea191aa10 pfuze: Fix unsigned variable for less-than-zero comparison
According to the Coverity result, a unsigned int variable is used fo less-
than-zero comparison, the result is never true. Need to fix the variable
type to signed int.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-01-07 17:48:25 +01:00
Fabio Estevam
a307760ab4 mx6sabresd: Simplify the Ethernet PHY configuration
As per the AR8031 datasheet:

"For a reliable power on reset, suggest to keep asserting the reset
low long enough (10ms) to ensure the clock is stable and clock-to-reset
1ms requirement is satisfied."

So do as suggested and also add a 100us delay after deasserting the
reset line to guarantee that the PHY ID can be read correctly and the
Atheros 8031 PHY driver can be loaded automatically.

This results in a simpler code.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-07 17:47:12 +01:00
Miao Yan
18d3f46995 qemu-ppce500: pass 'range_id' around in pci_map_region
In pci_map_region(), pass 'range_id' to fdt_read_range(),
otherwise the same address will be mapped again in other
calls to pci_map_region()

Signed-off-by: Miao Yan <yammiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2016-01-04 12:25:34 -05:00
Tom Rini
f1993ca066 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-01-03 10:32:24 -05:00
Peng Fan
ccf4326bac imx: mx6qsabreauto: support lvds display
Move setup_display from board_early_init_f to board_init.
Add more clock settings.
Add blacklight iomux setting.
Add display_info_t info for the lvds screen.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-01-03 16:03:14 +01:00
Mingkai Hu
1c5c6a5761 armv8/ls1043aqds/rcw: change core frequency to 1600MHz
Change RCW for SD boot and NAND boot.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:18 +08:00
Mingkai Hu
e2f019d783 armv8/ls1043ardb/rcw: change core frequency to 1600MHz
Change RCW for SD boot and NAND boot.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-17 08:52:18 +08:00
Aneesh Bansal
9711f52806 armv8/ls1043ardb: add SECURE BOOT target for NOR
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:35 +08:00
York Sun
c04921414c armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:33 +08:00
York Sun
c107c0c05c armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:33 +08:00
Yao Yuan
7ba0261810 arm: ls1021a: merge SoC specific code in a separate file
Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Shaohui Xie
e994dddbbe armv8/ls1043ardb: Add support for >2GB memory
This patch also expose the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:29 -08:00
Shaohui Xie
1aaf3f9ae4 freescale: fman: make sure phy-handle property is big endian
When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
York Sun
3901978d42 armv8/ls2080ardb: Update DDR settings for four chip-select case
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
York Sun
c4243ac9e2 armv8/ls2080aqds: Update DDR settings for four chip-select case
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
Peng Fan
53cc647dc6 imx: mx7dsabresd: Add QSPI support
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions

Default QSPI is not enabled, since we need hardware rework to use QSPI,
see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"

After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi
flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB
=> sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"

Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-12-11 22:12:23 +05:30
Fabio Estevam
29bc24ec4f mx6sxsabresd: Fix Ethernet PHY reset sequence
Since commit 59370f3fcd ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional.

This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.

Fix this by calling enable_fec_anatop_clock() earlier and also
by adding a 10ms reset delay as recommended in the AR8031 datasheet.

Suggested-by: Jörg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-12-07 14:55:24 +01:00
Prabhakar Kushwaha
5380335e66 board/ls2080qds: Fix typo in README for QSGMII riser card
DPMACx to PHY mapping for SGMII is mentioned as QSGMII.

So fix typo in README for QSGMII rise card.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Change from ls2085aqds to ls2080aqds]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:12 -08:00
Gong Qianyu
7023100971 armv8/ls1043ardb: add USB support
Add support for the third USB controller for LS1043A.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Shaohui Xie
02b5d2ed86 armv8/ls1043aqds: add LS1043AQDS board support
LS1043AQDS Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 DIMM
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two RGMII ports
 * XFI 10G port
 * SGMII
 * QSGMII with 4x 1G ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Prabhakar Kushwaha
06b5301043 armv8: ls2085a: Add support of LS2085A SoC
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:10:47 -08:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Prabhakar Kushwaha
1730a17db9 driver: net: fsl-mc: Create DPAA2 object at run-time
Freescale's DPAA2 ethernet driver depends upon the static DPL for the
DPRC, DPNI, DPBP, DPIO objects.

Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
25af413740 armv8: ls2085aqds: Print function name during SerDes error
Print function name along with SerDes Protocol during SerDes Protocol
not supported error.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Simon Glass
24b852a7a2 Move console definitions into a new console.h file
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-19 20:27:50 -07:00
Peng Fan
ebe517b63c imx: mx7dsabresd: support lcdif
Support LCDIF for mx7dsabresd board:
1. Add pinmux settings
2. Add VIDEO related macro definition and videomode env settings.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
2015-11-12 17:41:20 +01:00
Peng Fan
df67490488 imx: mx6ul_14x14_evk: support lcdif display
Support lcdif display:
1. Add pinmux and pad settings for LCDIF
2. Introduce setup_lcd to do the settings for LCDIF
3. Enable VIDEO related macros in board header files
4. Add a new env videomode which is needed by mxsfb.c. The
   settings for videomode in this patch is for TFT43AB.
5. Tested on mx6ul 14x14/9x9 evk.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-11-12 17:40:53 +01:00
Fabio Estevam
4bdcbe60a1 mx6ul_14x14_evk: Remove empty reset_cpu()
There is really no need to provide an empty reset_cpu() implementation,
so just remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-12 17:26:32 +01:00
Fabio Estevam
cec6f213b6 mx6sxsabresd: Remove empty reset_cpu()
There is really no need to provide an empty reset_cpu() implementation,
so just remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-12 17:26:31 +01:00
Fabio Estevam
c0039753cb mx6slevk: Remove empty reset_cpu()
There is really no need to provide an empty reset_cpu() implementation,
so just remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-12 17:26:31 +01:00
Fabio Estevam
26fbe9e531 mx6sabresd: Remove empty reset_cpu()
There is really no need to provide an empty reset_cpu() implementation,
so just remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-11-12 17:26:30 +01:00
Stefano Babic
5f5620ab26 Merge git://git.denx.de/u-boot 2015-11-12 17:13:26 +01:00
Fabio Estevam
9549867c86 ls1043ardb: Add missing config entries to MAINTAINERS
ls1043ardb_nand_defconfig and ls1043ardb_sdcard_defconfig are missing
in the MAINTAINERS file, so add them for completeness.

Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-11-10 16:52:58 +01:00
Yangbo Lu
bf50be835e mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter Card
When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card),
enable EVDD automatic control via SDHC_VS. This could support SD card
IO voltage switching for UHS-1 speed mode.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-02 08:50:29 -08:00
Yangbo Lu
cdc69550d2 mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter Card
If adapter card type identification is supported for platform, we would
enable dat[4:7] for eMMC4.5 Adapter Card.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-02 08:49:51 -08:00
Zhao Qiang
d468377672 t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdm
qe-tdm is muxed with diu, if hwconfig setted as qe-tdm,
assign muxed pins to qe-tdm, then delete diu node from
device tree.

Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-02 08:48:20 -08:00
tang yuantian
0210a36988 arm: ls1021atwr: optimize the deep sleep latency
It will take more than 1s when wake up from deep sleep. Most of the
time is spent on outputing information. This patch reduced the deep
sleep latency by:
1. avoid outputing system informaton
2. remove flush cache after DDR restore
3. skip reloading second stage uboot binary when SD boot

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-30 09:19:48 -07:00
Aneesh Bansal
6ec9aef2ce SECURE_BOOT: Correct reading of ITS bit
The ITS bit was being read incorrectly beacause of operator
precedence. The same ahs been corrected.

Signed-off-by: Lawish Deshmukh <lawish.deshmukh@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-30 09:19:47 -07:00
Adrian Alonso
78e9ca52ed mx7dsabresd: add secure boot support
Add secure boot support for mx7dsabresd target board

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-10-30 15:22:37 +01:00
Peng Fan
e469719c8b imx: mx6sabresd: add i.MX6DQP Sabresd support
Add i.MX6DQP-Sabresd board support:
1. set fdt_file according to board_rev which is set at runtime.
2. Add mx6dqp_ddr_ioregs and calibration value for this board.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-30 15:15:36 +01:00
tang yuantian
4632ad773e arm: ls1021a: Add sata support on qds and twr board
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:02 -07:00
Gong Qianyu
c7ca8b07fc armv8/ls1043ardb: Add sd boot support
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:02 -07:00
Yangbo Lu
8ef0d5c438 armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb
This patch adds esdhc support for ls1043ardb.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Shaohui Xie
e82973414d armv8/ls1043a: Add Fman support
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Gong Qianyu
3ad4472923 armv8/ls1043ardb: Add nand boot support
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Mingkai Hu
f3a8e2b7d4 armv8/ls1043ardb: Add LS1043ARDB board support
LS1043ARDB Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 SDRAM (32bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * XFI 10G port
 * QSGMII with 4x 1G ports
 * Two RGMII ports

PCIe:
 * PCIe2 (Lanes C) to mini-PCIe slot
 * PCIe3 (Lanes D) to PCIe slot

USB 3.0: two super speed USB 3.0 type A ports

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
2015-10-29 10:34:01 -07:00
Mingkai Hu
9f3183d2d6 armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Shaohui Xie
8225b2fd87 net: Move some header files to include/
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Mingkai Hu
435acd83b2 armv7/ls1021a: move ns_access to common file
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:58 -07:00
Aneesh Bansal
7bcb0eb285 Pointers in ESBC header made 32 bit
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:57 -07:00
Alison Wang
947cee1127 arm: ls1021a: Add QSPI or IFC support in SD boot
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in
SD boot now. For the customer's demand, QSPI needs to be supported in SD
boot too.

This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is
used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is
used to support QSPI in SD boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26 09:09:57 -07:00
Anthony Felice
4b8cdd484c vf610twr: Fix typo in DRAM init
This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-16 07:21:09 -04:00
Anthony Felice
42e550d44b vf610twr: Fix typo in DRAM init
This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-10-16 09:33:26 +02:00
Albert ARIBAUD \\(3ADEV\\)
3f353ceccb vf610: refactor DDRMC code
The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-10-02 10:42:31 +02:00
Peng Fan
60dba18801 imx: mx7dsabresd: drop code for CONFIG_CMD_BMODE
We use outer pmic reset and drop internal reset signal, bmode will
not work as expected, so drop boot mode code for 7dsabresd board.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Adrian Alonso <aalonso@freescale.com>
2015-09-24 11:32:18 +02:00
Peng Fan
0b530b140a imx: boards: Add maintainers info
Add MAINTAINERS info for mx6slevk_spl, mx6ul_9x9_evk and mx6qpsabreauto.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-24 11:28:59 +02:00
Peng Fan
8e4ba5e0ff imx: mx7dsabresd: drop SYS_SOC from board Kconfig
We have defined this kconfig entry in arch/arm/cpu/armv7/mx7/Kconfig,
no need to redefine it in board Kconfig.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-20 09:57:00 +02:00
Fabio Estevam
07af555513 mx6ul_14x14_evk: Remove get_board_rev()
get_board_rev() is not actually providing the board revision.

It just returns the CPU revision instead.

As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:48:00 +02:00
Fabio Estevam
d547e7ab16 mx6ul_14x14_evk: Staticize when possible
Make the internal symbols static when possible.

This prevents sparse build warnings.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
e9c8f0982d mx6ul_14x14_evk: Remove dead code
iox74lv_set() is not used anywhere, so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
e0ece17304 mx7dsabresd: Remove get_board_rev()
get_board_rev() is not actually providing the board revision.

It just returns the CPU revision instead.

As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
0df2f01d42 mx7dsabresd: Include USB header
Include <usb/ehci-fsl.h> in order to fix the following sparse warning:

board/freescale/mx7dsabresd/mx7dsabresd.c:538:5: warning: symbol 'board_ehci_hcd_init' was not declared. Should it be static?

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
b7d4db2f96 mx7dsabreasd: Remove dead code
iox74lv_set() is not used anywhere, so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Fabio Estevam
72e49e0364 mx7dsabresd: Staticize when possible
Make the internal symbols static when possible.

This prevents sparse build warnings.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:47:59 +02:00
Peng Fan
4fae48e8a9 imx: mx7dsabresd set wdog SRS bit
We use trigger pmic reset to reset the board, so set bit SRS to
disable internal WDOG_RESET_B_DEB to make reset stable.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-20 09:40:19 +02:00
Fabio Estevam
d6be30fe95 mx6ul_14x14_evk: Add a README file
Add a README file to help users getting started with the board.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-13 10:54:37 +02:00
Peng Fan
f20562e4c4 mx6: remove SYS_SOC from board Kconfig
Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: "Eric Bénard" <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2015-09-13 10:37:29 +02:00
Peng Fan
d9cbb264e8 imx: mx6ul: support mx6ul 9x9 evk board
This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk,
the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are:
1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC.
2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk
   supports 512MB DDR3
3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package.

This patch add the following:
1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size()
2. Introduce a macro is_mx6ul_9x9_evk using
   CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL
   part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work,
   so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with
   mx6ul_14x14_evk. And we have no way to dymaically checking this chip
   is 9x9 or 14x14.
3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations.
   POWER related configurations also effect for mx6ul_14x14_evk. But
   power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to
   do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk.
4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM
   configurations.
5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file
   according to board_rev and board_name.
6. Add TARGET_MX6UL_9X9_EVK Kconfig entry

Boot Log:
U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53)
reading u-boot.img
reading u-boot.img

U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 41C
Reset cause: POR
Board: MX6UL 9x9 EVK
I2C:   ready
DRAM:  256 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:   FEC1
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-13 10:32:44 +02:00
Adrian Alonso
1a8150d4b1 imx: mx7dsabresd: Add support for MX7D SABRESD board
* Add i.MX7D SABRESD target board support with enabled modules:
  UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.

  Build target: mx7dsabresd_config

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
2015-09-13 10:11:54 +02:00
Tom Rini
9809ccdd4c Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-09-02 11:30:46 -04:00
Tom Rini
0ffadab1b9 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-09-02 10:39:28 -04:00
Peng Fan
e7d3b21bb7 imx: mx6slevk: add SPL support
Add SPL boot support for mx6slevk board.
1. Introduce a configuration file mx6slevk_spl_defconfig.
2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE.
3. Include imx6_spl.h and related SPL macro in mx6slevk.h.
4. select SUPPORT_SPL for TARGET_MX6SLEVK.
5. Add SPL board code to do related initialization.

Boot Log:

U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000)

CPU:   Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 50C
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:13 +02:00
Peng Fan
f2ff834365 imx: mx6: ddr init MMDC according to ddr_type
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.

Initialize ddr_type for different boards which enable SPL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
0d4cdb5609 imx: mx6ul_14x14_evk add ENET support
Add enet support for mx6ul_14x14_evk board:
1. add pinmux settings
2. implement board_eth_init
3. implement board_phy_config

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:11 +02:00
Peng Fan
6d97dc10a8 imx: clock support enet2 anatop clock support
To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
   To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:29:14 +02:00
Zhuoyu Zhang
03c22449c5 arm/ls102xa:add hwconfig setting to support disable unused devices
DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.

For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma"
in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to
save more power.

Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:49:20 -05:00
York Sun
ec93af0dec armv8/ls2085a_emu: Drop DDR3 emulation target
The emulator with DDR3 model was used during model bringup. DDR4
controllers are used with ls2085a. Drop the DDR4 target defconfig
and enable DDR4 in ls2085a_emu_defconfig.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-09-01 21:39:21 -05:00
Claudiu Manoil
ebe4c1e646 ls102xa: etsec: Use proper settings for BE BDs
Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.

Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:39:03 -05:00
Prabhakar Kushwaha
cf7ee6c4e3 armv8: ls2085qds: Add support of X-QSGMII-16PORT riser card
The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
interfaces implemented in PCIe form factor board.
It supports followings
 - Card can operate with up to 4 QSGMII lane simultaneously
 - Card can operate with up to 8 SGMII lane simultaneously

Add support of X-QSGMII-16PORT riser card.
This patch also take care of back-ward compatiblity with old SGMII rise cards
used on LS2085QDS Platform.

Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:38:46 -05:00
Priyanka Jain
7fb79e6552 armv8/ls2085aqds: enable 32KHz rtc output
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:37:42 -05:00
Shengzhou Liu
47deb4b4a9 powerpc/t1023rdb: change default core frequency to 1200MHz
Per new requirement, change default core frequency
from previous 1400MHz to 1200MHz to save power.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 20:58:58 -05:00
York Sun
293194c8be powerpc/defconfig: Rename defconfig file for T1040QDS/T1024QDS DDR4 targets
Previously the DDR4 targets were named with _D4. Rename them with
_DDR4 for easy identification.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-09-01 20:42:54 -05:00
Peng Fan
125914d4be fsl: common: pfuze: no use original pfuze code if DM_PMIC
If enable DM PMIC and REGULATOR, we should not use original power
framework. So need to comment out the pfuze code for original power
framework, when CONFIG_DM_PMIC_PFUZE100 defined.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-12 11:05:11 +02:00
Alison Wang
8f0c7cbb0d armv7/ls1021a: allow OCRAM access permission as R/W in SPL
On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:37 -07:00
chenhui zhao
933db81c04 armv7/ls1021atwr: program the regulator for deep sleep
Program the external regulator to switch off voltage in deep sleep.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:36 -07:00
Tang Yuantian
99e1bd4241 armv7/ls1021atwr: added deep sleep support in uboot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:36 -07:00
Tom Rini
7a1af7a79b Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-08-02 07:40:37 -04:00
Peng Fan
f0ff57b0b2 imx: mx6ul_14x14_evk add basic board support
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
   supports sd for usdhc2, but can do hardware rework to make usdhc2 support
   emmc.

Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0
 - invalid sensor device
 Reset cause: POR
 Board: MX6UL 14x14 EVK
 I2C:   ready
 DRAM:  512 MiB
 MMC:   FSL_SDHC: 0, FSL_SDHC: 1
 *** Warning - bad CRC, using default environment

 In:    serial
 Out:   serial
 Err:   serial
 Net:   CPU Net Initialization Failed
 No ethernet found.
 Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:09 +02:00
Peng Fan
361b715bbf imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
   and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.

Build target: mx6qpsabreauto_config

Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)

CPU:   Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  0 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-08-02 10:47:52 +02:00
Peng Fan
e6fc8995d6 imx: mx6sabresd/sabreauto runtime setting fdt_file
Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.

Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:47:05 +02:00
Priyanka Jain
f2af1c37a0 powerpc/T104xRDB: Remove vbank check redundant code
sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:56:11 -07:00
Shengzhou Liu
e04dd12bf1 powerpc/t1023rdb: eMMC boot without external SD card
eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:19 -07:00
Shengzhou Liu
ff7ea2d18b powerpc/t1023rdb: add support for T1023RDB RevC
Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Aneesh Bansal
73cc2f50eb powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.

The targets for P5020 and P5040 are added in the same manner.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Aneesh Bansal
467a40dfe3 powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Priyanka Jain
fa9ccff835 powerpc/t104x, t102x: Update CPC debug register value in PBI commands
Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:15 -07:00
Shaohui Xie
f57709ab18 powerpc/t4rdb: fix cpld reset altbank
cpld reset altbank should always reset to bank4 no matter what
current bank is.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:15 -07:00
Ying Zhang
01a6113d2a powerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issue
Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.

In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:15 -07:00
gaurav rana
e622d9ed3b powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms
defconfig files are added and SFP version for these platforms
is updated.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:14 -07:00
Priyanka Jain
4b6067ae9d powerpc/T104xD4RDB: Add T104xD4RDB boards support
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
    T1040D4RDB is re-designed T1040RDB board with following changes :
    - Support of DDR4 memory
    - Support of 0x66 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 1 SGMII on DTSEC3
    - Support of QE-TDM

    Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
    SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
    - Support of DDR4 memory
    - Support for 0x86 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
    - Support of DIU

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:40:57 -07:00
Fabio Estevam
42acd1874f mx6sxsabresd: Use 'int' for return values
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should be of type 'int' instead of 'unsigned int' in order to
correctly handle negative numbers.

Fix the variable type.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-07-26 12:12:04 +02:00
Fabio Estevam
e4b984d75e mx6sabresd: Use 'int' for return values
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should of type 'int' instead of 'unsigned int' in order to correctly
handle negative numbers.

Fix the variable type.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-07-26 12:12:04 +02:00
Haikun.Wang@freescale.com
5989df7e2c armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLD
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:39 -07:00
Haikun Wang
e71a980a4d armv8/ls2085aqds: DSPI pin muxing configure through QIXIS
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:39 -07:00
Alison Wang
88c857df8c arm/ls102xa: Add little-endian mode support for audio IPs
As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:38 -07:00
Prabhakar Kushwaha
9527931507 board/ls2085rdb: Export functions for standalone AQ FW load apps
Export functions required by Aquntia PHY firmware load application.
functions are memset, strcpy, mdelay, mdio_get_current_dev,
phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:37 -07:00
Prabhakar Kushwaha
5c05508971 armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvr
The agreed split of the top of memory is 256M for debug server and 256M
 for MC. This patch implements the split.

 In addition, the MC mem must be 512MB aligned, so the amount of memory
 to hide must be 512MB to achieve that alignment.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:36 -07:00
Bhupesh Sharma
a2dc818f21 armv8/ls2085a: Expose all DDR region(s) to Linux
This patch allows u-boot to expose the complete DDR region(s) to Linux
(after subtracting the memory hidden via MEM_TOP_HIDE mechanism).

This allows the u-boot to support the 48-bit VA support provided by
ARM64 Linux in flavors 3.18 and above, by passing the appropriate
'memory' DTS nodes.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:35 -07:00
York Sun
fc7b3855e1 armv8/ls2085ardb: Fix SPD address error on early boards
Board rev C and earlier has duplicated SPD address on 2nd DDR
controller slots. It is fixed on rev D and later. SPD addresses
need to be updated accordingly.

Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
2015-07-20 11:44:35 -07:00
Prabhakar Kushwaha
ff1b8e3f55 armv8/ls2085a: Avoid hard-coding for board name print
LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE,
LS2080A, LS2085AE and LS2085A personlities.

Instead of hard-coding, board name should change as per selected
personality.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:35 -07:00
Prabhakar Kushwaha
27df54b163 armv8/ls2085RDB: Update board version print logic
As per updated board document, no need to substract 1 from arch[BRD]
bit field. Default value + 'A' represents the board revision.

So update board version print logic to reflect the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Jaiprakash Singh
b8baf460ee board/fsl/common: Fix eeprom system version endianness
SYSTEM ID EPPROM always store SYSTEM version info in big endian format.
SoC with ARM or PowerPC core should read/write version info from eeprom
in BIG endian format.

So use cpu-specific APIs to read SYSTEM version.

Signed-off-by: Jaiprakash Singh <b44839 at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Prabhakar Kushwaha
d7b76e89ed armv8/ls2085qds: Update SFP TX bit as "0" to enable XFI
FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports.

Signed-off-by: Dai Haruki <Dai.Haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Prabhakar Kushwaha
94540c5604 armv8/ls2085aqds: Add support of SerDes protocol 0x49
SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2.

Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of
ls2085aqds platform.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:33 -07:00
Yangbo Lu
5a4d744c90 armv8/ls2085ardb: add hwconfig setting for eSDHC
Add hwconfig setting for eSDHC since it shares some pins with other
IP block.

Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:33 -07:00
Prabhakar Kushwaha
3484d95307 armv8/ls2085ardb: Add eth & phy firmware loading support
Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.

Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:33 -07:00
Tom Rini
9bea236b34 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-05-26 10:38:01 -04:00
York Sun
a88cc3bd90 arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h
ccsr_ddr structure is already defined in fsl_immap.h. Remove
this duplicated define. Move fixed timing into ls1021atwr.h.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
2015-05-20 10:34:09 -07:00
Peng Fan
3fd10f3e25 pmic: pfuze100 fix typo
Change PUZE_100_SW1ABCONF to PFUZE100_SW1ABCONF

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-05-19 15:13:38 +02:00
Jan Kiszka
104d6fb6cd ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions
CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: York Sun <yorksun@freescale.com>
CC: Steve Rae <srae@broadcom.com>
CC: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:13 -07:00
Shaohui Xie
38289c6945 powerpc/t4240qds: Update RCW, defconfig and maintainer
1. board/freescale/t4qds/t4_rcw.cfg
1.8GHz support is requested as default frequency, so update the rcw.

2. remove un-used configs
configs/T4160QDS_SPIFLASH_defconfig
configs/T4240QDS_SPIFLASH_defconfig
SPI boot is not available on T4QDS, so the configs should be removed.

3. board/freescale/t4qds/MAINTAINERS
Updated MAINTAINERS accordingly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: revise subject]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:26:01 -07:00
Shengzhou Liu
c0379b19e2 t2080rdb/rcw: update ddr frequency from 1600MT/s to 1867MT/s
T2080RDB RevC uses new SODIMM 1867MT/s instead of previous 1600MT/s.
So update RCW to support new DDR frequency 1867MT/s by default.
Reserve the old 1600MT/s in comment for users in needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:25:53 -07:00
Yangbo Lu
5a8dbdc6b4 mmc: fsl_esdhc: Add adapter card type identification support
Add adapter card type identification support by reading
FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
define CONFIG_FSL_ESDHC_ADAPTER_IDENT.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
[York Sun: resolve conflicts in README.fsl-esdhc]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:25:19 -07:00
Shengzhou Liu
fd3a78a538 board/t2080rdb: reset cs4315 phy
CS4315 PHY doesn't support phy-reset by software, it
needs to reset it by hardware via CPLD control.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:25:12 -07:00
Tang Yuantian
1a56fcea9f fsl/deepsleep: avoid the DDR restore from being optimized out
Function dp_ddr_restore is to restore the first 128-byte space
of DDR. However those codes may be optimized out by compiler
since the destination address is at 0x0. In order to avoid
compiler optimization, we restore the space from high address,
which is not at 0x0, to low address.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:25:06 -07:00
Shengzhou Liu
ea753267d5 board/t102x: use fdt_setprop_string instead of fdt_setprop
Use fdt_setprop_string instead of fdt_setprop to fix string length.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:24:50 -07:00
Shengzhou Liu
e8a7f1c32b powerpc/t1023rdb: Add T1023 RDB board support
T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC.

T1023RDB board Overview
-----------------------
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - one 1G RGMII port on-board(RTL8211F PHY)
  - one 1G SGMII port on-board(RTL8211F PHY)
  - one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR:  128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC card and eMMC on-board
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging

As well updated T1024RDB to add T1023RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix defconfig files]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:24:31 -07:00
Chunhe Lan
373762c34c powerpc/t4rdb: Add SD boot support for T4240RDB board
This patch adds SD boot support for T4240RDB board. SPL
framework is used. PBL initializes the internal RAM and
copies SPL to it. Then SPL initializes DDR using SPD and
copies u-boot from SD card to DDR, finally SPL transfers
control to u-boot.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: Fix T4240RDB_SDCARD_defcofig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:24:04 -07:00
York Sun
7fc63cca61 mpc85xx/T4240EMU: Remove T4240EMU board
T4240 SoC has been available for a long time. Emulator support
is no longer needed.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-05-04 09:23:46 -07:00
Tom Rini
e536ab8849 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-04-28 12:15:13 -04:00
Tom Rini
3f6dcdb9cd Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-04-24 13:43:24 -04:00
Scott Wood
32eda7cc94 armv8/ls2085ardb: Enable NAND SPL support
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command. Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:51 -07:00
Scott Wood
548cf52fd5 freescale/qixis: Add support for booting from NAND
Use "qixis_reset nand" to reset the board to boot from NAND.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:51 -07:00
Scott Wood
b2d5ac5985 armv8/ls2085aqds: NAND boot support
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Jaiprakash Singh
39b0bbbb23 driver/ifc: Add 64KB page support
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.

FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Prabhakar Kushwaha
e60476a01e board/ls2085qds: Add support ethernet
Add support of ethernet:
 - eth.c: mapping lane to slot for (0x2A, 0x07)
 - ls2085a.c: To enable/disable dpmac and get link type

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Stefan Agner
8b4f9afac0 ARM: vf610: Enable external 32KHz oscillator
Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2015-04-23 14:56:08 -04:00
Sanchayan Maity
c7ea243cc0 ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2015-04-23 14:56:08 -04:00
angelo@sysam.it
5296cb1d99 m68k: add architecture-specific u-boot.lds
Add architecture-specific u-boot.lds and remove all board-specific
u-boot.lds.

All the .text customization that was board-specific have been
moved inside the related include/configs, inside a
LDS_BOARD_TEXT define.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2015-04-23 14:56:07 -04:00
York Sun
e2b65ea975 armv8/ls2085ardb: Add support of LS2085ARDB platform
The LS2085ARDB is a evaluation platform that supports LS2085A
family SoCs. This patch add sbasic support for the platform.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-04-23 08:55:58 -07:00
York Sun
7288c2c2b0 armv8/ls2085aqds: Add support of LS2085AQDS platform
The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2015-04-23 08:55:58 -07:00
Scott Wood
b991b981e0 fsl-lsch3: Introduce place for common early SoC init
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:56 -07:00
pankaj chauhan
05d2e21be5 armv8/ls2085a: Add support for reset request
Add support for reset_cpu() by asserting RESET_REQ_B.

Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:55 -07:00
York Sun
207774b213 armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>
2015-04-23 08:55:55 -07:00
Fabio Estevam
cba4c255fc mx6sabresd: Remove uneeded ifdef
RTT_NOM_120OHM is not defined, so remove its ifdef.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-04-22 16:02:46 +02:00
Fabio Estevam
407be42d73 mx6sabresd: Fix SPL memory description
mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus
and 2GiB, so fix the width and density fields accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-04-22 16:02:46 +02:00
gaurav rana
1c29ad7bc0 iMX: Fix compilation error when enabling SECURE_BOOT
Move the compilation of file fsl_validate.c in MACRO CONFIG_CMD_ESBC_VALIDATE.
This file should be compiled only when the above MACRO is defined

This caused a break in compilation of iMX platforms when compiling for SECURE_BOOT

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
2015-04-22 16:02:46 +02:00
Prabhakar Kushwaha
a2a55e518f driver/fsl-mc: Add support of MC Flibs
Freescale's Layerscape Management Complex (MC) provide support various
objects like DPRC, DPNI, DPBP and DPIO.
Where:
	DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO
	DPBP: Management of buffer pool
	DPIO: Used for used to QBMan portal
	DPNI: Represents standard network interface

These objects are used for DPAA ethernet drivers.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:27:35 -07:00
Bhupesh Sharma
422cb08acb armv8/fsl-lsch3: Add Freescale Debug Server driver
The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:

MC DDR region start = Top of DDR - area reserved by Debug Server FW

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:26:29 -07:00
Zhao Qiang
1fb5ff9ae7 QE/DeepSleep: add QE deepsleep support for arm
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:20 -07:00
Zhao Qiang
ae42eb035e QE/DeepSleep: add QE deepsleep support for mpc85xx
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Minghuan Lian
d42bd3453a pci/layerscape: remove unnecessary pcie_layerscape.h
The patch uses the common function name ft_pci_setup to replace
ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
all the functions have been declared in common.h.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
gaurav rana
98cb0efde8 Add bootscript support to esbc_validate.
1. Default environment will be used for secure boot flow
 which can't be edited or saved.
2. Command for secure boot is predefined in the default
 environment which will run on autoboot (and autoboot is
 the only option allowed in case of secure boot) and it
 looks like this:
 #define CONFIG_SECBOOT \
 "setenv bs_hdraddr 0xe8e00000;"                 \
 "esbc_validate $bs_hdraddr;"                    \
 "source $img_addr;"                             \
 "esbc_halt;"
 #endif
3. Boot Script can contain esbc_validate commands and bootm command.
 Uboot source command used in default secure boot command will
 run the bootscript.
4. Command esbc_halt added to ensure either bootm executes
 after validation of images or core should just spin.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Alison Wang
997c67d98b ls102xa: ddr4: Use LPUART as console output to verify DCU driver
On QDS board with DDR4 DIMM, LPUART is used as console
output to verify DCU driver. This patch adds
ls1021aqds_ddr4_nor_lpuart_defconfig for this support.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Yao Yuan
09227dd9df ls1021atwr: add hwconfig setting to do pin mux
Freescale LS1021ATWR share some pins. Hwconfig option is used to
allows users to choose the pin functions.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: revised commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Alison Wang
036f3f3379 arm/ls102xa:Add support of conditional workaround implementation as per SoC ver
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Shengzhou Liu
4913229ed6 powerpc/t2080rdb: update ddr to support 1866MT/s
Support SODIMM D3XP12081XL10AA 1866MT/s on T2080RDB.
Enable CONFIG_CMD_MEMTEST as well.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Ying Zhang
e5abb92c0b board/t208xrdb: VID support
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:29 -07:00
Tom Rini
1d2f74690c Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-04-13 10:52:46 -04:00
Fabio Estevam
a80a65e997 mx53loco: Disable printing cpuinfo
Since commit 32df39c741 ("mx5: fix get_reset_cause") we have the following
boot messages on a mx53qsb:

U-Boot 2015.04-rc5-00029-gd68df02 (Apr 06 2015 - 11:15:39)

CPU:   Freescale i.MX53 rev2.1 at 800 MHz
Reset cause: POR
Board: MX53 LOCO
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
CPU:   Freescale i.MX53 rev2.1 at 1000 MHz
Reset cause: unknown reset
Net:   FEC [PRIME]

The CPU and Reset cause lines appear twice.

Initially mx53 boots at 800MHz, then at a later point the PMIC is configured via
I2C to raise the CPU voltage so that it can run at 1GHz.

To avoid such misleading double printings, disable printing cpu info for now.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2015-04-08 10:45:50 +02:00
angelo@sysam.it
944ab340b6 m68k: fix 3 broken boards
Fix eb_cpu5282 and eb_cpu5282_internal unresolved external error.
These boards have video but don't need any ppc related
video_setmem().

Fix M53017EVB moving away embedded env to a different offset,
as in M52277EVB.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2015-03-28 12:07:46 -04:00
Tom Rini
1c6f6a6ef9 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-03-05 20:50:30 -05:00
gaurav rana
e04916a721 SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.
esbc_validate command uses various IP Blocks: Security Monitor, CAAM block
and SFP registers. Hence the respective CONFIG's are enabled.

Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-05 12:04:59 -08:00
gaurav rana
47151e4bcc SECURE BOOT: Add command for validation of images
1. esbc_validate command is meant for validating header and
   signature of images (Boot Script and ESBC uboot client).
   SHA-256 and RSA operations are performed using SEC block in HW.
   This command works on both PBL based and Non PBL based Freescale
   platforms.
   Command usage:
   esbc_validate img_hdr_addr [pub_key_hash]
2. ESBC uboot client can be linux. Additionally, rootfs and device
   tree blob can also be signed.
3. In the event of header or signature failure in validation,
   ITS and ITF bits determine further course of action.
4. In case of soft failure, appropriate error is dumped on console.
5. In case of hard failure, SoC is issued RESET REQUEST after
   dumping error on the console.
6. KEY REVOCATION Feature:
   QorIQ platforms like B4/T4 have support of srk key table and key
   revocation in ISBC code in Silicon.
   The srk key table allows the user to have a key table with multiple
   keys and revoke any key in case of particular key gets compromised.
   In case the ISBC code uses the key revocation and srk key table to
   verify the u-boot code, the subsequent chain of trust should also
   use the same.
6. ISBC KEY EXTENSION Feature:
   This feature allows large number of keys to be used for esbc validation
   of images. A set of public keys is being signed and validated by ISBC
   which can be further used for esbc validation of images.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-05 12:04:59 -08:00
vijay rai
2372e283e5 mpc85xx/t104xrdb : remove raw timing parameter
This board uses DDR DIMM. Reading SPD provides more flexibility.
Raw timing parameter code should be removed after debugging.

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-05 12:03:22 -08:00
Tom Rini
02ebe6f702 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-03-05 07:22:18 -05:00
Stefano Babic
32df39c741 mx5: fix get_reset_cause
commit d9f43c8f5c sets
get_reset_cause() as static, but this conflicts with mx5
where its prototype is in sys_proto.h.

Drop it from sys_proto.h and drop print_cpuinfo from mx53_loco,
factorizing the call for this board.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <jason.hui@linaro.org>
2015-03-05 10:29:27 +01:00
Sinan Akman
19e5118d1c mpc837xerdb: "fix Calling __hwconfig without a buffer" warning
Signed-off-by: Sinan Akman <sinan@writeme.com>
2015-03-02 15:11:36 -05:00
Fabio Estevam
16edd347f0 mx6slevk: Provide a proper pad configuration for OTG1_ID pin
Pass the same pad configuration as done in the kernel so that OTG1_ID pin can
properly work in device mode.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-03-02 11:55:26 +01:00
Fabio Estevam
86a390d305 mx25pdk: Turn on the LCD supply
Currently there is no support for MC34704 PMIC in the mainline kernel.

Turn on the LCD supply via bootloader for the time being, so that we could
use the LCD in the kernel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-03-02 09:57:05 +01:00
Stefano Babic
b9cb64825b Merge branch 'master' of git://git.denx.de/u-boot 2015-03-02 09:42:53 +01:00
Alison Wang
8133574ea4 arm: ls1021x: Add support for initializing CAAM's stream id
There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id
for using the same SMMU3 on LS1021A.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:11:05 -08:00
J. German Rivera
7b3bd9a798 drivers/mc: Migrated MC Flibs to 0.5.2
Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory
fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree
from "fsl,dprcr" to "fsl-mc". Print MC version info when
appropriate.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:20 -08:00
York Sun
2aa44a2498 ARMv8/LS2085A: Enable auto precharge for DP-DDR
DP-DDR benefits from auto precharge because of its specific
application.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:22 -08:00
York Sun
32da3398b5 armv8/ls2085a: Enable cluster timebase for all clusters
LS2085A and its variants can have up to four clusters. It is safe
to enable timebase for all even some may be disabled.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:08:50 -08:00
Peng Fan
af38bf6b38 imx:mx6slevk implement power init board
Implement power_init_board and related I2C interface configuration.

After adding this, uboot can successfully detect and configure pmic.

"
U-Boot 2015.01-00281-ge29eddf (Feb 12 2015 - 09:24:01)

CPU:   Freescale i.MX6SL rev1.0 at 396 MHz
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-02-23 09:11:41 +01:00
Stefano Babic
e72d344386 Merge branch 'master' of git://git.denx.de/u-boot 2015-02-13 11:17:01 +01:00
Peng Fan
258c98f8d3 imx:mx6 set normal APS and standby PFM mode
To normal mode, use APS switching mode.
To standy mode, use PFM switching mode.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
2015-02-11 12:38:48 +01:00
Peng Fan
7428f55c94 pmic:pfuze implement pmic_mode_init
This patch is to implement pmic_mode_init function, and add prototype
in header file.

This function is to set switching mode for pmic buck regulators to
improve system efficiency.

Mode:
OFF: The regulator is switched off and the output voltage is discharged.
PFM: In this mode, the regulator is always in PFM mode, which
     is useful at light loads for optimized efficiency.
PWM: In this mode, the regulator is always in PWM mode operation
     regardless of load conditions.
APS: In this mode, the regulator moves automatically between
     pulse skipping mode and PWM mode depending on load conditions.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
2015-02-11 12:27:46 +01:00
Tom Rini
307367eaff Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-02-10 10:40:43 -05:00
Fabio Estevam
aee0013e53 mx53loco: Fix boot hang during reboot stress test
Currently by running the following test:

=> setenv bootcmd reset
=> save
=> reset

, we observe a hang after approximately 20-30 minutes of stress reboot test.

Investigation of this issue revealed that when a single DDR chip select is used,
the hang does not happen. It only happens when the two chip selects are active.

MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence":

"The controller must keep the memory lines quiet (except for CK) for the ZQ
calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256
for other ZQCL and 64 for ZQCS)."

According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL:

"Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines.
Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)"

So make sure to activate one chip select at time (CS0 first and then CS1 later),
so that the required JEDEC delay is respected for each chip select.

With this change applied the board has gone through three days of reboot stress
test without any hang.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-02-10 12:48:50 +01:00
Ye.Li
5f22d88f82 imx: mx6qsabreauto: Change to use common GPMI IO clock function
Since a clock function setup_gpmi_io_clk is implemented for GPMI
IO clock settings, change to use this common function in GPMI setup.

Signed-off-by: Ye.Li <B37916@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-02-10 12:48:49 +01:00
tang yuantian
41ba57d0c7 fsl/ls1021qds: Add deep sleep support
Add deep sleep support on Freescale LS1021QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
[York Sun: Fix conflict in fdt.c]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-24 09:12:32 -06:00
Alison Wang
55d53ab45e arm: ls102xa: Add LPUART support for LS1021ATWR board
This patch adds LPUART support for LS1021ATWR board.
For ls1021atwr_nor_lpuart_defconfig, LPUART is used as the console.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:15 -06:00
Alison Wang
8fc2121a10 arm: ls102xa: Add LPUART support for LS1021AQDS board
This patch adds LPUART support for LS1021AQDS board.
For ls1021aqds_nor_lpuart_defconfig, LPUART is used as the console.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:15 -06:00
Alison Wang
7df50fd323 arm: ls102xa: Update snoop settings for CCI-400
CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
S0 will cause CAAM self test failure. This patch is to enable snooping
for S0 slave interface. These CCI-400 operations are moved to
board_early_init_f() to be initialized earlier. For S4 slave interface,
issuing of snoop requests and DVM message requests are enabled.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Xiubo Li
dd04832d52 ls102xa: dcu: Add platform support for DCU on LS1021AQDS board
This patch adds the CH7301 HDMI options and the common configuration
for DCU on LS1021AQDS board.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Cc: Jason Jin <Jason.Jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Alison Wang
0f5e5579f2 ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as default
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:14 -06:00
Masahiro Yamada
168dcc6cef powerpc: mpc85xx: remove P2020DS board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-01-23 16:53:17 -05:00
Masahiro Yamada
891235366d powerpc: mpc85xx: remove P2020COME board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Ira W. Snyder <iws@ovro.caltech.edu>
2015-01-23 16:53:12 -05:00
Masahiro Yamada
743d48151d powerpc: mpc85xx: remove P1_P2_RDB boards
These boards are still non-generic boards:
P1011RDB, P1022RDB, P2010RDB, P2020RDB

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2015-01-23 16:53:06 -05:00
Masahiro Yamada
8d1e3cb140 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Dave Liu <daveliu@freescale.com>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
2015-01-23 16:53:00 -05:00
Tom Rini
ec0cc98f2c Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-01-22 20:04:17 -05:00
Peng Fan
1565d54a76 imx:mx6sxsabresd board spl support
Add board level spl support for mx6sxsabresd board.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-01-22 09:56:06 +01:00
Codrin Ciubotariu
db4a1767c0 board/T1040rdb: Add VSC9953 support for T1040rdb board
This patch configures and initializes the L2 switch on T1040rdb board.
The external L2 switch ports may be connected to PHYs only over
QSGMII, for T1040rdb.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
2015-01-21 09:23:36 -06:00
Codrin Ciubotariu
a83fccc2c9 board/T1040qds: Add VSC9953 support for T1040qds board
This patch configures and initializes the L2 switch on T1040QDS board.
The L2 switch ports must be initialized according to the SerDes
protocols.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
2015-01-21 09:23:36 -06:00
Codrin Ciubotariu
9b478bef27 board/T104xrdb: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYs
Freescale's T1040qds board may be configured to have up to
5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports,
2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2),
connected to other two ports from an intergrated
VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link
ports have no PHYs attatched, so they don't have a
corresponding MDIO.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-21 09:23:35 -06:00
Codrin Ciubotariu
d9fb29c7e3 board/T1040qds: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYs
Freescale's T1040qds board may be configured to have up to
5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports,
2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2),
connected to other two ports from an intergrated
VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link
ports have no PHYs attatched, so they don't have a
corresponding MDIO.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-21 09:23:35 -06:00
Codrin Ciubotariu
ea191e6df2 board/T1040qds: Fix lane-to-slot mapping for SerDes protocol 0x89
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-21 09:23:35 -06:00
Sinan Akman
b9315890f6 MAINTAINERS: add me as the maintainer of mpc837xerdb
Signed-off-by: Sinan Akman <sinan@writeme.com>
Cc: Tom Rini <trini@ti.com>
2015-01-20 10:19:57 -05:00
Simon Glass
22d69fd7a8 imx: ls102xa: Remove reference to gdata
The global_data pointer (gd) has already been set before board_init_f()
is called. We should not assign it again. We should also not use gdata since
it is going away.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-20 10:15:46 -05:00
Fabio Estevam
834670eae0 mx6sxsabresd: Remove unneeded board_late_init()
Since commit 1f98e31bc0 ("imx: mx6sxsabresd: Use the pfuze common init
function") board_late_init() became empty, so we can safely remove this unneeded
function.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-01-19 09:04:42 +01:00
tang yuantian
7d0e97a294 mpc85xx/t1040qds: convert deep sleep to generic board interface
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:31:36 -08:00
tang yuantian
2c537642e9 mpc85xx/t102xqds: convert deep sleep to generic board interface
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:31:26 -08:00
Shengzhou Liu
e26416a3f1 powerpc/t1024rdb: Add support for T1024RDB-PB
T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY.
rcw_0x095 is used for 10G XFI + 3x PCIex1
rcw_0x135 is used for 2.5G SGMII + 2x PCIex1

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:31:20 -08:00
tang yuantian
f49b8c1b5d mpc85xx/t102xrdb: convert deep sleep to generic board interface
A new deep sleep interface is introduced to support generic
board structure. Converts it to use new interface.

Besides, added SPI/SD/NAND boot deep sleep support.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:31:06 -08:00
gaurav rana
68caf1dd1e powerpc: SECURE BOOT- Add secure boot target for T1042RDB
Secure boot target is added for T1042RDB platform.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:30:39 -08:00
Chunhe Lan
3bcf047da8 powerpc/t4240rdb: Add alternate SerDes 2 protocol to align with RCW
SerDes 2 protocol 56 is not valid any longer due to
the new RCW; protocol 55 is used instead, so add
SerDes 2 protocol 55 to align with RCW.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:29:59 -08:00
gaurav rana
a56e723811 powerpc/mpc85xx: SECURE BOOT- Add secure boot target for P5040DS
Secure boot target is added for P5040DS platform.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:27:15 -08:00
Po Liu
3ca49c425f powerpc/c29xpcie: Add secure boot support
Add NOR and SPI flash secure boot target for C29XPCIE board.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
Signed-off-by: Mingkai.Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-16 09:27:06 -08:00
Masahiro Yamada
d928664f41 powerpc: 74xx_7xx: remove 74xx_7xx cpu support
All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2

Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
2015-01-16 10:24:39 -05:00
Masahiro Yamada
b3a2bbe1a4 mpc8260: remove MPC8266ADS board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rune Torgersen <runet@innovsys.com>
2015-01-05 12:08:54 -05:00
Tom Rini
b4a0b4006f Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-02 07:42:58 -05:00
Peng Fan
be2fde60b0 imx:mx6slevk add spi nor boot support
Add spi nor boot support for mx6slevk board.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:54:01 +05:30
Peng Fan
fad7d735a0 imx:mx6sxsabresd add qspi support
Configure the pad setting and enable qspi clock to support qspi
flashes access.

Add QSPI related macro in configuration header file.

Note:
mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M.
The LUT initialization qspi_set_lut function uses 32BIT addr,
however CONFIG_SPI_FLASH_BAR  and 24BIT addr should be used to
access bigger than 16MB size flash, and BRRD/BRWR should also
be supported. Future patches will fix this.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Fabio Estevam
87e47e9058 mx6slevk: Remove get_board_rev()
get_board_rev() just returns the cpu revision, which does not make it really
useful for distinguishing between revisions of the board.

Let's get rid of get_board_rev() as it is not being used with its correct
meaning.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-30 14:10:39 +01:00
Fabio Estevam
76494f7ac3 mx51evk: Fix MX51EVK_USB_CLK_EN_B definition
As per the mx51evk schematics MX51EVK_USB_CLK_EN_B is GPIO2_1, not GPIO2_2.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-19 15:32:14 +01:00
Peng Fan
fb00bda705 imx:mx6qarm2 add board level support for usb
Add pinmux settings and implement board_ehci_hcd_init

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2014-12-19 15:32:13 +01:00
Peng Fan
5a3d63c5cd imx:mx6sabresd add board level support for usb
Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2014-12-19 15:32:13 +01:00
Tang Yuantian
0023352855 mpc85xx/t104xrdb: convert deep sleep to generic board interface
A new interface is introduced to support generic board structure.
Converts it to use new interface.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:17:12 -08:00
Tom Rini
fc9b0b8043 Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-12-11 18:40:49 -05:00
Tom Rini
2c49323d5d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-12-11 18:28:09 -05:00
Xiubo Li
660673af4f ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:22 -08:00
Xiubo Li
e87f3b308c ARM: ls102xa: allow all the peripheral access permission as R/W.
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.

For now we configure all the peripheral access permissions as R/W.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:12 -08:00
Tang Yuantian
a7787b7850 fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:18 -08:00
Yao Yuan
bca11bd7c3 ls1021aqds: add hwconfig setting to do pin mux
The Freescale LS1021AQDS share some pins, so Add the hwconfig option
that allows the user to choose which the function he wants.

The main pin mux IP is:
eSDHC, SAI, IIC2, RGMII, CAN, SAI.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:32 -08:00
Alison Wang
8ab967b6c6 arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:24 -08:00
Alison Wang
d612f0ab34 arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:14 -08:00
Alison Wang
8415bb68c8 arm: ls102xa: Add SD boot support for LS1021ATWR board
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:39:32 -08:00
Alison Wang
86949c2b7c arm: ls102xa: Add SD boot support for LS1021AQDS board
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:39:22 -08:00
Alison Wang
2565d18de0 ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macro
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.

Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:39:06 -08:00
Chenhui Zhao
afff13790e ls1021aqds: set the default I2C channel before DDR init
When resuming from deep sleep, the I2C channel may not be
in the default channel. So, switch to the default channel
before accessing DDR SPD.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:36:13 -08:00
Minghuan Lian
da419027af arm: ls102xa: Update PCIe dts node status
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:35:56 -08:00
Tom Rini
9b416a9f4c Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-12-10 09:07:25 -05:00
Minghuan Lian
af7219de2c powerpc/hydra: fix judging condition of RGMII selection
BRDCFG1_EMI1_SEL_MASK has been changed to 0x78, which contains
selection bits and connected status bit. So the Corresponding mux
value of RGMII is changed to BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:17 -08:00
Chunhe Lan
b41f126340 powerpc/hydra: Update MDIO mux fixups
The new device trees use a more generic interface for
supporting muxing mdio buses. The mux property is thus
specified in "reg", rather than "fsl,hydra-mdio-muxval".

In order to support using old device trees, we keep the
old fixup in there. Linux will therefore see the both
properties, but will ignore fsl,hydra-mdio-muxval.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Shengzhou Liu
10227aaa24 board/t1024qds: add retimer support on t1024qds
Initialize retimer for XFI on t1024qds.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Shengzhou Liu
5818643bf4 t1024qds: increase IO drive strength
Increase IO drive strength to fix FCS error on RGMII ports
on T1024QDS.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:16 -08:00
Shengzhou Liu
355b385847 board/t1024qds: update pin multiplexing
Add multiplexing support among SPI flash, TDM riser card and SDXC.
it routes SPI pins to SPI flash by default.
Route SPI pins to SD slot if "adaptor=sdxc" is set in hwconfig.
Route SPI pins to TDM riser card and do fixup for dts if "pin_mux=tdm"
is set in hwconfig.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
48c6f328f0 powerpc/t1024rdb: Add T1024 RDB board support
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.

T1024RDB board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - one 10Gbps XFI interface
- PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors.
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD
- eSPI: 64MB N25Q512 SPI flash.
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- USB: Two  Type-A USB2.0 ports with internal PHY
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC
- I2C: Four I2C controllers
- UART: Two UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
	   Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
aba8004818 powerpc/t1024qds: Add T1024 QDS board support
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.

T1024QDS board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - Three 1G/2.5Gbps SGMII ports
  - Four 1Gbps QSGMII ports
  - one 10Gbps XFI or 10Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
  - Chrontel CH7201 for HDMI connection.
  - TI DS90C387R for direct LCD connection.
  - Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
  - 32-bit RISC controller for flexible support of the communications peripherals
  - Serial DMA channel for receive and transmit on all serial channels
  - Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
	   Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
06b3acf184 powerpc/t2080: updating rcw for silicon v1.1
T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0,
and also update core frequency to 1.8GHz for v1.1.
We reserve the support for T2080 v1.0 and enable v1.1 by default.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Suresh Gupta
e2544e7a54 B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
respectively in hwconfig.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Shaohui Xie
b24f6d401c powerpc/b4860qds: add workaround for XFI
XFI does not work stable on current board, it's due to heat sink issue,
to make it work stable the board needs additional heat sink, enable two
XFI lanes only. Right now we do not have such an erratum for the issue,
so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it.
The workaround will only be used in XFI protocols and only if the
hwconfig indicates that XFI is prefered.

A new VSC3308 config function is used instead of re-use the original
function, to avoid making the function complex and ugly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:13 -08:00
Suresh Gupta
cd79e5f414 B4860QDS: Enable SFP or AMC on basis of hwconfig string
SerDes2 lanes EFGH either go to SFP or AMC riser card slot2.
By default AMC will be configured even if no hwconfig is specified.

To enable XFI via SFP use the below hwconfig:
	fsl_b4860_serdes2:sfp_amc=sfp

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@ffeescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:13 -08:00
Shaohui Xie
90e80dc6b6 powerpc/b4860qds: dtb fixup for xfi
Since xfi has no phy, we delete the property "phy-handle" and use
a "fixed-link" property for a xfi port.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:13 -08:00
Shaohui Xie
89b94d851d powerpc/b4860qds: add xfi support
We need following changes to make xfi work on B4:
1. set cross-point switch VSC3308 to use sfp config when running xfi;
2. add 10G interface check for xfi;
3. set phy address for xfi so the 10G ports can be registered by mdio;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:13 -08:00
Shaveta Leekha
8c328c21b7 B4860: Add alternate LC VCO serdes protocols support in board file
Add the support of newly added LC VCO SerDes protocols
for configuration of IDT and VSC crossbar

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:12 -08:00
Shaveta Leekha
f1d8074c08 B4860QDS: SGMII related updates
- Enable SGMII support for 0x8d Serdes 2 protocol.
    - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol.
    - Updated debug statement
    - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1)
    - Rename onboard PHY address defines for more readability
    - Add these new Defines in B4860QDS.h file

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:12 -08:00
Shaveta Leekha
f7c28aa7ce powerpc/b4860: Enable law creation of MAPLE
B4860, B4440, B4420 and B4220 have MAPLE, so enable law creation
for them only. Remove static LAW creation for MAPLE.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:12 -08:00
Ying Zhang
3ad2737ee3 powerpc/t208xqds: VID support
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:09 -08:00
Prabhakar Kushwaha
31530e0b8a board/t104xrdb: Conditional workaround of errata A-008044
Workaround of Errata A-008044 was implemented without errata number and it is
enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0.

So put errata number and make it conditional.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:09 -08:00
Prabhakar Kushwaha
9f074e67f5 powerpc/mpc85xx:Put errata number for T104x NAND boot issue
When device is configured to load RCW from NAND flash IFC_A[16:31] are driven
low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using
IFC_A[16:31] lines are not accessible.

Workaround is already in-place.
Put the errata number to adhere errata handling framework.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:08 -08:00
York Sun
ed9e4e4272 mpc85xx/t208xqds: Adjust DDR timing parameters
Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of
1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in
case such DIMM comes available.

Also update single-rank 1866 timing. Enable interactive debugging as well.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-12-05 08:06:08 -08:00
Stefan Roese
7731745c13 arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)
As checkpatch complaines about these camel-case defines, lets change
them to only use upper-case characters.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-01 10:20:20 +01:00
Tom Rini
85bafb6da4 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-11-26 11:23:26 -05:00
Tom Rini
21008ad638 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Conflicts:
	drivers/mmc/fsl_esdhc.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-26 11:22:29 -05:00
Tom Rini
1fc4e6f486 Merge git://git.denx.de/u-boot-fdt 2014-11-26 11:21:14 -05:00
Alison Wang
0ab172353e arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing
EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or
SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1
as other functionality except RGMII. The workaround is to select
ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-24 09:27:24 -08:00
Alison Wang
5175a2885f arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR board
SystemID information could be read through I2C1 from EEPROM
on LS1021ATWR board.

As LS1 is a little-endian processor, getting the version ID by
be32_to_cpu() is wrong. Fix it by using e.version directly.
This change will be compatible for both ARM and PowerPC.

As there is an errata that I2C1 could not work in SD boot,
reading EEPROM through I2C1 is disabled too in SD boot.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-24 09:27:23 -08:00
Alison Wang
c207ff6129 arm: ls102xa: Remove bit reversing for SCFG registers
SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.

Address: 157_0000h base + 200h offset = 157_0200h
Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R                                   SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31

This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-24 09:27:23 -08:00
Jason Jin
644bc7ec5c arm: ls102xa: Add snoop disable for slave port 0, 1 and 2
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-24 09:27:23 -08:00
Tom Rini
dee332ffb7 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-11-24 12:02:12 -05:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
Fabio Estevam
7bf38161af mx53ard: Fix error handling in board_mmc_init()
When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-21 16:47:55 +01:00
Fabio Estevam
1abd714de2 mx53evk: Fix error handling in board_mmc_init()
When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-21 16:47:55 +01:00
Fabio Estevam
c5ba77ac05 mx53smd: Fix error handling in board_mmc_init()
When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-21 16:47:55 +01:00
Fabio Estevam
a49c44dd8b mx6qarm2: Fix error handling in board_mmc_init()
When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-21 16:47:54 +01:00
Fabio Estevam
d6af507d5a mx51evk: Fix error handling in board_mmc_init()
When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-21 16:47:54 +01:00
Simon Glass
933cdbb479 fdt: Try to use fdt_address_cells()/fdt_size_cells()
Use these new functions where possible. They default to a value of 2 so we
cannot use them in some places where we need a default value of 1.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-11-21 04:43:18 +01:00
Simon Glass
e895a4b06f fdt: Allow ft_board_setup() to report failure
This function can fail if the device tree runs out of space. Rather than
silently booting with an incomplete device tree, allow the failure to be
detected.

Unfortunately this involves changing a lot of places in the code. I have
not changed behvaiour to return an error where one is not currently
returned, to avoid unexpected breakage.

Eventually it would be nice to allow boards to register functions to be
called to update the device tree. This would avoid all the many functions
to do this. However it's not clear yet if this should be done using driver
model or with a linker list. This work is left for later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2014-11-21 04:43:15 +01:00
Ye.Li
593243d3a2 imx: imx6q/dlsabreauto: Add PMIC Pfuze100 support
Add the pfuze100 initialization in power_init_board for imx6q/dl
sabreauto board.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-20 10:52:32 +01:00
Ye.Li
1f98e31bc0 imx: mx6sxsabresd: Use the pfuze common init function
Modify the pfuze init for mx6sxsabresd to use the shared
"pfuze_common_init" function. And move this initialization to
power_init_board.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-20 10:51:45 +01:00
Ye.Li
f0fabb7945 imx: mx6sabresd: Use the pfuze common init function
Modify the pfuze init for mx6sabresd to use the shared
"pfuze_common_init" function. And move this initialization to
power_init_board.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-20 10:51:45 +01:00
Ye.Li
5051ff5fb0 imx: mx6sabre common: Factorize the Pfuze init function
Since the Pfuze initializations are similar on various mx6 SABRE
boards. Factorize the initialization to a common function in file
board/freescale/common/pfuze.c. So that all SABRE boards BSP can
share the function.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-20 10:50:20 +01:00
Ye.Li
d0fbca2a3a imx: mx6sxsabresd: Add board support for USDHC2 and USDHC3
Add full support for USDHC2, USDHC3, USDHC4 on mx6sx sabresd board.
The default boot socket is USDHC4, so the MMC environment device and
mmcdev variable are set to this device.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-20 10:45:14 +01:00
Fabio Estevam
ae80eecceb mx6sabresd: Access SRC_SBMR1 register via structure
In U-boot it is preferred to access the register via structure pointer, so
convert it such style.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-20 10:30:21 +01:00
Fabio Estevam
31b9023d84 mx6sabresd: Add mx6sabresd_spl_defconfig to MAINTAINERS entry
Let's add mx6sabresd_spl_defconfig entry into MAINTAINERS, so that we avoid
getting a warning that the mx6sabresd_spl is not maintained.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-20 10:30:20 +01:00
Fabio Estevam
d7bc7e6031 mx6sxsabresd: Simplify the return value of setup_fec()
We can simply the return the value from enable_fec_anatop_clock() to make the
code smaller and simpler.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-20 10:30:20 +01:00
Fabio Estevam
da5019e2b3 mx6slevk: Simplify the return value of setup_fec()
We can simply the return the value from enable_fec_anatop_clock() to make the
code smaller and simpler.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-20 10:30:20 +01:00
Fabio Estevam
c9c41d0e2b mx6sabresd: State that only mx6q is supported in SPL
Make clear that current SPL code only supports the mx6q variant.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-20 10:30:20 +01:00
Fabio Estevam
1769502b53 mx53loco: Fix error handling in board_mmc_init()
When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-20 10:30:20 +01:00
Fabio Estevam
cdbdde3f56 mx6qsabreauto: Add parallel NOR flash support
mx6sabreauto boards come with 32 MiB of parallel NOR flash.

Add support for it:

U-Boot 2015.01-rc1-18107-g1543636-dirty (Nov 14 2014 - 11:11:04)

CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
Flash: 32 MiB
NAND:  0 MiB

Due to pin conflict with I2C3, only define configure I2C3 IOMUX when flash is
not used.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-20 10:30:19 +01:00
Fabio Estevam
53b7f18044 mx6: Use a common SPL configuration file
Many boards use a minimal .cfg file in the SPL case.

Introduce spl_sd.cfg so that we can reuse it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-11-20 10:30:18 +01:00
Fabio Estevam
6e9b6bb5a0 mx6sabresd: Move the DCD settings to spl code
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.

Move the configuration to the spl code.

CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-20 10:13:54 +01:00
Peng Fan
05095535f6 imx:mx6sxsabresd fix pfuz probe failed
The PFUZ probe failed with the following msg:
" wait_for_sr_state: failed sr=81 cr=a0 state=2020
  i2c_init_transfer: failed for chip 0x8 retry=0
  wait_for_sr_state: failed sr=81 cr=a0 state=2020
  i2c_init_transfer: failed for chip 0x8 retry=1
  wait_for_sr_state: failed sr=81 cr=a0 state=2020
  i2c_init_transfer: failed for chip 0x8 retry=2
  i2c_init_transfer: give up i2c_regs=021a0000
  Can't find PMIC:PFUZE100 "

board_early_init_f is too early to call i2c related setting, because
init_func_i2c is called after board_early_init_f being invoked. Thus
move setup_i2c into board_init.

Also PFUZ is connected to I2C bus 0, so change "1" -> "0".

Using this patch PFUZ can be correctly probed:
"PMIC:  PFUZE100 ID=0x11"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-11-20 10:13:53 +01:00
Shaohui Xie
3ce21c87c1 powerpc/t2080qds: fix for 1000BASE-KX
1000BASE-KX(1G-KX) uses SGMII protocol but the serdes lane runs in 1G-KX
mode. By default, the lane runs in SGMII mode, when a MAC uses a lane
in 1G-KX mode, corresponding bit in PCCR1 for the lane needs to be set,
and needs to fixup dtb accordingly for kernel to do proper initialization.

Hwconfig "fsl_1gkx" is used to indicate a MAC runs in 1G-KX mode, FM1 MAC
1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
MAC runs in 1G-KX mode, set its' corresponding env in "fsl_1gkx",
'fm1_1g1' stands for FM1-MAC1, 'fm1_1g2' stands for FM1-MAC2, etc.

If all MAC 1/2/5/6/9/10 run in 1G-KX mode, the hwconfig should has below
setting:

fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: Fix compiling warning]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-19 18:16:50 -08:00
Zhao Qiang
eaa859e7d2 qe: add qe support for ls1021a-twr board
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-19 12:56:09 -08:00
Zhao Qiang
63e75fd7a3 qe: add qe support to ls1021aqds
add qe support to ls1021aqds

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-19 12:56:04 -08:00
shaohui xie
f0644da50e powerpc/t2080qds: fixup dtb for 10g-kr
XFI ports on t2080qds can work with fiber cable and direct attach
cable(copper). We use hwconfig to define cable type for XFI, and fixup
dtb based on the cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:<10g_mac_name>

the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4.
fm1_10g1 stands for FM1-MAC9, fm1_10g2 stands for FM1-MAC10, fm1_10g3
stands for FM1-MAC1, fm1_10g4 stands for FM1-MAC2. The four
<10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports, if
a given 10G port will use the copper cable for 10GBASE-KR, set the
<10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-19 10:32:03 -08:00
Shengzhou Liu
e9caf76032 board/t2080qds: add readme for t2080qds
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-19 10:28:22 -08:00
Tom Rini
2086e388d5 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-11-14 16:39:32 -05:00
Peng Fan
a511a3e0e8 imx:mx6sxsabresd add board level support for usb
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6sxsabresd board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to make host port work in HOST mode.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <B37916@freescale.com>
2014-11-14 20:58:19 +01:00
Peng Fan
3b9c1a5dc0 imx:mx6slevk add board level support for usb
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to let host port work in host mode.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <B37916@freescale.com>
2014-11-14 20:56:58 +01:00
Ashish Kumar
7ac1a24a85 powerpc/BSC9131RDB: Enable creation of dynamic partitions for NAND
* fdt_fixup_mtdparts is called from ft_board_setup
 * Run "mtdparts default" to create NAND partition on uboot
 * Use mtdparts to create partitions dynamically rather
    than using static partitions in device tree

Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-14 11:12:14 -08:00
Ashish Kumar
42a9e2fe1b powerpc/BSC9132QDS: Enable creation of dynamic partition for NAND and NOR
* fdt_fixup_mtdparts is called from ft_board_setup
 * run "mtdparts default" to create NAND, NOR partition on uboot
 * Use mtdparts to create partitions dynamically rather
    than using static partitions in device tree

Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-14 11:12:14 -08:00
Priyanka Jain
0921de6744 t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg
-A_007662 states that for x1 link width, PCIe2 controller trains in
 Gen1 speed while configured for Gen2 speed.
 Workaround:Set the width to x1 and speed to Gen2 by writing to
 CCSR registers in PBI phase

-A_008007 states that PVR register may show random value.
 Workaround: Reset PVR register using DCSR space in PBI phase

Add PBI based software workaround for A_007662 and A_008007
in t104x_pbi.cfg. This is required for SPL-based bootloaders
like NAND-boot, SD-boot, SPI-boot

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-14 11:12:14 -08:00
Chunhe Lan
ab06b236f7 powerpc/t4rdb: Add support of CPLD
This support of CPLD includes

    - Files and register definitions
    - Command to switch alternate bank
    - Command to switch default bank

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-14 11:12:14 -08:00
Fabio Estevam
3302c275b3 mx6sabresd: Staticize when possible
Annotate 'static' when appropriate for the variables used locally.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-13 18:06:18 +01:00
Fabio Estevam
952fdc4e83 mx6sabresd: Fix error handling in board_mmc_init()
When an invalid USDHC port is passed we should return -EINVAL instead of 0.

Also, return the error immediately on fsl_esdhc_initialize() failure.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-13 18:06:13 +01:00
John Tobias
75f2ba4220 imx6: SPL support for iMX6 SabreSD
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port (Switch 1 or 2 of SW6)

Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-11-13 16:25:10 +01:00
John Tobias
340d1d3a0e imx6: add data configuration file for SPL
It's a trim version of mx6q_4x_mt41j128.cfg. It just removed
the related settings for DDR

Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
2014-11-13 16:23:55 +01:00
Ye.Li
83bb3215df imx: mx6q/dlsabreauto: And NAND flash support
The i.MX6Q/DL sabreauto board has one NAND socket, set the
CONFIG_NAND_MXS and relevant NAND configurations to enable the
MXS NAND flash driver.
Add board level codes to set IOMUX and clock for GPMI-NAND and
BCH module.

Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-13 16:23:55 +01:00
Fabio Estevam
4ccaf5ddeb mx53loco: Change 'fdt_file' dynamically
Since kernel 3.15 there are two dtb's for the imx53-qsb board:

imx53-qsb.dtb - For the boards with DA9053 PMIC
imx53-qsrb.dtb - For the boards with MC34708 PMIC

Change the 'fdt_file' dynamically, so that the correct dtb can be used depending
on the board variant.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2014-11-13 16:22:26 +01:00
Fabio Estevam
f4a7bf5a37 mx28evk: README: Revision C is also supported
Adjust the text to mention that rev C of the board is also supported.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-11-12 09:05:57 +01:00
Tom Rini
625509ab0e Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-11-05 12:48:09 -05:00
Ye.Li
8fe280f330 imx: mx6 sabreauto: Add board support for USB EHCI
On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both USB port failed to work.
This patch fix the problem by adding the board support codes.

Since the power control uses the GPIO pin from port expander MAX7310,
the PCA953X driver is enabled for accessing the MAX7310.

The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
handle GPR register setting.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-03 11:21:49 +01:00
Ye.Li
36255d6779 imx: mx6slevk: Add support for USDHC1 and USDHC3 slots
There are three SD/MMC sockets on mx6slevk boards. Implements the
full support for them.
The default boot socket is USDHC2, so the MMC environment is set
to that device.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-11-03 11:21:49 +01:00
Fabio Estevam
ca9d817ab5 mx6sabresd: Add Seiko WVGA panel support
Add support for the 4.3'' Seiko WVGA parallel display.

In order to direct the splash screen to the Seiko display:

=> setenv panel SEIKO-WVGA
=> save
=> reset

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-10-30 10:11:39 +01:00
Georges Savoundararadj
2e07c249a6 kconfig: arm: introduce symbol for ARM CPUs
This commit introduces a Kconfig symbol for each ARM CPU:
CPU_ARM720T, CPU_ARM920T, CPU_ARM926EJS, CPU_ARM946ES, CPU_ARM1136,
CPU_ARM1176, CPU_V7, CPU_PXA, CPU_SA1100.
Also, it adds the CPU feature Kconfig symbol HAS_VBAR which is selected
for CPU_ARM1176 and CPU_V7.

For each target, the corresponding CPU is selected and the definition of
SYS_CPU in the corresponding Kconfig file is removed.

Also, it removes redundant "string" type in some Kconfig files.

Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-10-29 09:02:09 -04:00
Tom Rini
0cf8761549 Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx 2014-10-27 11:03:00 -04:00
Anatolij Gustschin
0694f805ed powerpc: mpc5121ads: update board config info in README
The config targets described in README are not present
any more, update the info to currently used targets.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2014-10-27 14:35:55 +01:00
Tom Rini
0ce4af99c0 Merge branch 'master' of git://git.denx.de/u-boot-imx 2014-10-27 09:08:42 -04:00
Fabio Estevam
510922ac61 mx6qsabreauto: Add HDMI support
Let HDMI splash screen support work by default.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-10-21 14:04:39 +02:00
Eric Nelson
3acb011c3c ARM: i.MX: provide declaration for board_spi_cs_gpio
Provide a public declaration of the board_spi_cs_gpio()
callback for i.MX SPI chip selects to prevent the warning
"Should it be static?" when compiling with "make C=1".

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2014-10-21 10:47:14 +02:00
Ruchika Gupta
ba4740205d ls102x: Add support for secure boot and enable blob command
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:21:26 -07:00
Ruchika Gupta
4ba4a095da ls102x: configs - Add hash command in freescale LS1 platforms
Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-16 14:17:32 -07:00
Albert ARIBAUD
4b19b7448e Merge remote-tracking branch 'u-boot-imx/master'
The single file conflict below is actually trivial.

Conflicts:
	board/boundary/nitrogen6x/nitrogen6x.c
2014-10-08 21:20:49 +02:00
Anthony Felice
c19a8bc571 vf610twr: Tune DDR initialization settings
Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.

Changed register settings to comply with JEDEC required values.

Changed timing parameters because they included full clock
periods that were doing nothing.

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-10-07 13:08:31 +02:00
Ye.Li
661139faf7 imx: mx6dlarm2: Add support for i.MX6Q/DL arm2 LPDDR2 boards
Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2
arm2 board. Since the LPDDR2 arm2 board has different DDR size, use
CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-30 12:21:14 +02:00
Ye.Li
b357503f1c imx: mx6dlarm2: Add support for i.MX6DL arm2 DDR3 board
This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.

The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.

Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-30 12:21:14 +02:00
Tom Rini
2c2277f15c Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-09-26 09:57:52 -04:00
Tom Rini
2c3dc792b6 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-09-26 09:51:18 -04:00
York Sun
c7eae7fcb1 board/ls1021aqds: Add DDR4 support
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
2014-09-25 09:12:12 -07:00
York Sun
8bfa301b0a ARMv8/ls2085a: Enable secondary cores
Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.

Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-25 08:36:19 -07:00
York Sun
d9c68b1444 ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory block
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:18 -07:00
Masahiro Yamada
c79cba37b3 cosmetic: replace MIN, MAX with min, max
The macro MIN, MAX is defined as the aliase of min, max,
respectively.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-24 18:30:29 -04:00
Masahiro Yamada
535aad29f2 MAINTAINERS: comment out blank M: field
Since commit ddaf5c8f30
(patman: RunPipe() should not pipe stdout/stderr unless asked),
Patman spits lots of "Invalid MAINTAINERS address: '-'"
error messages for patches with global changes.
It takes too long for Patman to process them.

Anyway, "M:    -" does not carry any important information.
Rather, it is just like a place holder in case of assigning
a new board maintainer.  Let's comment out.

This commit can be reproduced by the following command:

find . -name MAINTAINERS | xargs sed -i -e '/^M:[[:blank:]]*-$/s/^/#/'

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-24 18:30:28 -04:00
Masahiro Yamada
e5a504eb3d MAINTAINERS: comment out invalid maintainers
The "S:    Orphan" in MAINTAINERS means that the maintainer in the
"M:" field is unreachable (i.e. the email address is not working).
(Refer to the definition of "Orphan" adopted in U-Boot
in the log of commit 31f1b654b2,
"boards.cfg: move boards with invalid emails to Orphan")

For patch files adding global changes, scripts/get_maintainer.pl
adds bunch of such invalid email addresses, which results in
tons of annoying bounce emails.

This commit can be reproduced by the following command:

find . -name MAINTAINERS | xargs sed -i -e '
/^M:[[:blank:]]/ {
      N
      /S:[[:blank:]]Orphan/s/^/#/
}
'

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-09-24 18:30:28 -04:00
Priyanka Jain
5273aa3834 board/t1040qds: Add sgmii ports support in 0xA7 protocol
T1042QDS (T1042 is T1040 Personality without L2 switch) supports following
sgmii interfaces with serdes protocol 0xA7
-SGMII-MAC3 on Lane B - slot 7
-SGMII-MAC5 on Lane H - slot 7
-SGMII2.5G-MAC1 on Lane C - slot 6
-SGMII2.5G-MAC2 on Lane D - slot 5

Add support of above sgmii interfaces

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2014-09-24 13:12:16 -07:00
Priyanka Jain
92f7fed4f7 powerpc/t104xrdb: Set DDR ODT to 75ohm
DDR-ODT require cfg_dram_type switch set properly as per DDR type.
T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type
should be set to OFF for DDR3L
Update t104xrdb/README for switch setting

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-24 13:11:32 -07:00
vijay rai
363fb32aca powerpc/t104xrdb: Add T1042RDB board support
T1042RDB is a Freescale reference board that hosts the T1042 SoC
(and variants). The board is similar to T1040RDB, T1042 is a reduced
personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).

T1042RDB is configured with serdes protocol 0x86 which can support
following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
DTSEC1, DTSEC2 are not connected on board.

This Patch
- add T1042RDB support
- updates README file for T1042RDB details and update commands for switching
  to alternate banks from vBank0 to vBank4 and vice versa

This patch also does minor clean ups for fdt defines for T1042RDB and
T1042RDB_PI board

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-24 13:02:03 -07:00
vijay rai
d087e0e262 powerpc/t104xrdb: Add Support of rcw for T1042RDB in u-boot
This patch adds support of rcw for T1042RDB, it makes following changes :
- Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB
- Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates
  comments for valid serdes protocol which is 0x06
- Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-24 13:01:35 -07:00
Prabhakar Kushwaha
1b35721f61 board/ls2085a: Update env_addr after NOR flash relocation
LS2085a has 2 regions in system memory map. Region1 is default map from
where system boots. Once u-boot is moved to DDR, IFC is re-mapped to
Region2.

So, update gd->env_addr to reflect correct address.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-24 12:33:18 -07:00
Nikita Kiryanov
155fa9af95 spi: mxc: fix sf probe when using mxc_spi
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:

cs = (cs | gpio << 8)

This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".

This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.

Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.

Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-09-24 17:25:39 +05:30
Nitin Garg
7972913512 imx: ddr: Move mx6q_4x_mt41j128.cfg to mx6sabresd board
Provide cgtqmx6eval board its own variant of ddr
setup config file. Move board/freescale/imx/ddr/
mx6q_4x_mt41j128.cfg to board/freescale/mx6sabresd/
as this is was designed for the mx6sabresd board.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-09-22 16:09:56 +02:00
Stefano Babic
42817eb85d Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-09-22 15:51:01 +02:00
Tom Rini
e38b15b061 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-09-17 18:01:04 -04:00
Stefano Babic
0fdfafd225 imx: Fix warning by building vf610twr_nand
commit d6d07a9b... arm: vf610: add NAND support for vf610twr
generates the following warnings:

WARNING: no status info for 'vf610twr_nand'
WARNING: no maintainers for 'vf610twr_nand'WARNING: no status info for
'vf610twr_nand'

This is due to the fact that vf610twr_nand_defconfig has no Maintainer.
This patch proposed Alison as Maintainer and fix it.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Alison Wang <b18965@freescale.com>
CC: Stefan Agner <stefan@agner.ch>
2014-09-17 11:01:56 +02:00
Masahiro Yamada
016a954ee9 kconfig: armv8: move CONFIG_ARM64 to Kconfig
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-16 12:24:00 -04:00
Fabio Estevam
067a659317 mx6qsabreauto: Staticize when possible
Turn all local symbols into static in order to make sparse happy.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-09-16 13:37:01 +02:00
Fabio Estevam
bcaa075a63 mx6sxsabresd: Staticize i2c_pad_info1
i2c_pad_info1 is only used locally, so it can be made static.

Fix the following sparse warning:

board/freescale/mx6sxsabresd/mx6sxsabresd.c:160:22: warning: symbol 'i2c_pad_info1' was not declared. Should it be static?

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-09-16 13:36:05 +02:00
Stefan Agner
d6d07a9bec arm: vf610: add NAND support for vf610twr
This adds NAND support for the Vybrid tower system (TWR-VF65GS10)
provided by the vf610_nfc driver. Full 16-Bit bus width is
supported. Also an aditional config vf610twr_nand is introduced
which gets the environment from NAND. However, booting U-Boot from
NAND is not yet possible due to missing boot configuration block
(BCB).

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-16 13:25:45 +02:00
Masahiro Yamada
461be2f96e kconfig: remove redundant "string" type in arch and board Kconfigs
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.

We can delete the ones in arch and board Kconfig files.

This commit can be easily reproduced by the following command:

find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
    N
    s/\n[[:space:]]*string//
}
'

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-13 16:43:55 -04:00
Fabio Estevam
f4fb5ef045 mx6dlsabresd: Use its own DCD table
Currently mx6dlsabresd shares the same DCD settings with the nitrogen board.

Provide a DCD configuration file specific to mx6dlsabresd with the settings
recommended by the Freescale hardware team.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-09-09 16:55:22 +02:00
Wang Huan
b4ecc8c6f8 ls102xa: dcu: Add platform support for DCU on LS1021ATWR board
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:36 -07:00
Wang Huan
4081bf4f90 video: dcu: Add Sii9022A HDMI Transmitter support
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:35 -07:00
Wang Huan
c8a7d9dab0 arm: ls102xa: Add basic support for LS1021ATWR board
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
 One DDR controller
 DUART1 is used as the console

For the detail board information, please refer to README.

Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:35 -07:00
Wang Huan
550e3dc090 arm: ls102xa: Add basic support for LS1021AQDS board
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
 One DDR controller
 DUART1 is used as the console

For the detail board information, please refer to README.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-08 10:30:34 -07:00
Claudiu Manoil
93f26f130e net: Merge asm/fsl_enet.h into fsl_mdio.h
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.

To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2014-09-08 10:30:33 -07:00
Tom Rini
5a1095a830 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-08-29 11:06:51 -04:00
York Sun
8af353bb0e powerpc/t4qds: Move doc/README.t4240qds under board/freescale/t4qds
Board specific README file should be moved to board folder.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Shaohui Xie
9bf499ace8 powerpc/T4240QDS/eth: some fix for XFI
XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.

So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. For fiber cable, there is NO PHY, while
for copper cable, we need to use internal PHY which exist in Serdes to
do auto-negotiation and link training, which implemented in kernel.
We use hwconfig to define cable type for XFI, and fixup dtb based on the
cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:<10g_mac_name>

the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The
four <10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports,
if a given 10G port will use the copper cable for 10GBASE-KR, set the
<10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2

For fiber cable:

1. give PHY address to a XFI port, otherwise, the XFI ports will not be
available in U-boot, there is no PHY physically for XFI when using fiber
cable, this is just to make U-boot happy and we can use the XFI ports
in U-boot.
2. fixup dtb to use fixed-link in case of fiber cable which has no PHY.
Kernel requests that a MAC must have a PHY or fixed-link.

When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface.

Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56
is not valid any longer.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Fabio Estevam
d145878d59 mx6sxsabresd: Add Ethernet support
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.

Add support for one FEC port initially.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:15:23 +02:00
Fabio Estevam
080d72f233 mx6sxsabresd: Convert to the new Kconfig style
mx6sxsabresd was not in the master branch when the conversion to the new Kconfig
style happened, so convert it now so that it can build again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:11:12 +02:00
Fabio Estevam
eb5c18078d mx6sxsabresd: Update DDR initialization
Use the latest DDR initialization values suggested by the FSL hardware team.

While at it, add some comments for clarification.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 12:41:41 +02:00
Fabio Estevam
5494b92dea mx31pdk: Change maintainer
Currently I don't have access to a mx31pdk board.

Magnus was the original maintainer of the board and accepted to take back
this role.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Magnus Lilja <lilja.magnus@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-20 12:14:31 +02:00
Tang Yuantian
ce249d956c powerpc/t104xrdb: support deep sleep in SPI/SD boot
Add deep sleep support in SPI/SD boot. The destination address
second stage uboot image is loaded to is changed because
currently this address will be used by kernel which means
we can't reserve it for resume.

Entry point to kernel is still placed in second stage uboot.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-12 12:26:47 -07:00
Jason Jin
cf8ddacffc powerpc/t1042RDB: Add Video - HDMI support
T1042 has internal display interface unit (DIU) for driving video.
T1042RDB supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder

Chrontel, CH7301C encoder which is I2C programmable is used
as HDMI connector on T1042RDB.
This patch add support to
-enable Video interface for T1042RDB
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1042
-program HDMI encoder via I2C on board

This patch refer to the upstream diu patch
(337b0c52b3) for T1040qds.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
[York Sun: resolve conflict and move changes to T104xRDB.h]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-12 12:26:47 -07:00
Wang Dongsheng
c53711bb62 fsl/diu: ch7301 encoder split off from t1040qds/diu.c
The ch7301 encoder not only used in t1040qds platform, so we split
it for t1042rdb and LSx platform.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-12 12:26:46 -07:00
Stefano Babic
e82abaeb7f Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	boards.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-08-11 10:21:03 +02:00
Fabio Estevam
676ac24e07 pmic: pmic_pfuze100: Use a shorter name for PMIC name
It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already
know it is a PMIC.

Call it simply 'PFUZE100' instead.

Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:41 +02:00
Stefano Babic
c23154aab5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-08 10:18:40 +02:00
Masahiro Yamada
93d4334f7f Add board MAINTAINERS files
We have switched to Kconfig and the boards.cfg file is going to
be removed. We have to retrieve the board status and maintainers
information from it.

The MAINTAINERS format as in Linux Kernel would be nice
because we can crib the scripts/get_maintainer.pl script.

After some discussion, we chose to put a MAINTAINERS file under each
board directory, not the top-level one because we want to collect
relevant information for a board into a single place.

TODO:
Modify get_maintainer.pl to scan multiple MAINTAINERS files.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:06 -04:00
Masahiro Yamada
dd84058d24 kconfig: add board Kconfig and defconfig files
This commit adds:
 - arch/${ARCH}/Kconfig
    provide a menu to select target boards
 - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig
    set CONFIG macros to the appropriate values for each board
 - configs/${TARGET_BOARD}_defconfig
    default setting of each board

(This commit was automatically generated by a conversion script
based on boards.cfg)

In Linux Kernel, defconfig files are located under
arch/${ARCH}/configs/ directory.
It works in Linux Kernel since ARCH is always given from the
command line for cross compile.

But in U-Boot, ARCH is not given from the command line.
Which means we cannot know ARCH until the board configuration is done.
That is why all the "*_defconfig" files should be gathered into a
single directory ./configs/.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:01 -04:00
Fabio Estevam
0a11d6f29c mx6: Remove duplication of iomuxc structure
There is no need to keep iomuxc_base_regs structure as it serves the exact same
purpose of the iomuxc structure, which is to provide access to the GPR
registers.

The additional fields of iomuxc_base_regs are not used. Other advantage of
'iomuxc' is that it has a shorter name and the variable declarations can fit
into a single line.

So remove iomuxc_base_regs structure and use iomuxc instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Fabio Estevam
fa8cf3176c mx6sxsabresd: Add PFUZE100 PMIC support
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-23 12:25:40 +02:00
Shaohui Xie
e55782eccc powerpc/t4240qds: fix offset of serdes when checking reference clock
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
9d0456822c powerpc/mpc85xx: Check return value of find_tlb_idx
find_tlb_idx() is called in board_early_init_r() on multiple boards.
The return value is not checked before being used to disable a TLB.
In normal case the return value wouldn't be -1. In case of a mis-
configuration during porting to a new board, checking the return value
may be helpful to reveal some user errors.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
vijay rai
6666017f44 powerpc/t1040qds: Initialize EPHY2 clock to RGMII only
Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Lijun Pan
d0bc51407c powerpc/mpc85xx: Remove P1023 RDS support
Since P1023RDS is no longer supported/manufactured by Freescale,
we clean up P1023RDS related code.
Since P1023RDB is still supported by Freescale,
we keep P1023RDB releated code.

Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Masahiro Yamada
61f06b143e m68k: fix an undefined behavior warning of M5253DEMO board
The latest GCC is so clever that it reports more warnings
than old ones did:

 ------------------------------>8------------------------------

  board/freescale/m5253demo/flash.c: In function 'flash_get_offsets':
  board/freescale/m5253demo/flash.c:65:23: warning: iteration 2047u
  invokes undefined behavior [-Waggressive-loop-optimizations]
      info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
                         ^
  board/freescale/m5253demo/flash.c:64:3: note: containing loop
     for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
     ^

 ------------------------------8<------------------------------

The cause of the warning is like this:

The for statement iterates 2048 times in flash_get_offsets() func.
(Notice CONFIG_SYS_SST_SECT is defined as 2048)

The last iteration does
  info->start[2048] = info->start[2047] + CONFIG_SYS_SST_SECTSZ;
causing an undefined behavior.

(Please note the array size of info->start is 2048.
CONFIG_SYS_MAX_FLASH_SECT is defined as 2048 for this board.)

This commit fixes that so as not to overrun the info->start array.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jason Jin <Jason.jin@freescale.com>
2014-07-22 09:46:48 -04:00
Stefano Babic
dab5e3469d Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>

Conflicts:
	boards.cfg
2014-07-16 08:51:30 +02:00
Fabio Estevam
14a1613140 mx6sx: Add initial support for mx6sxsabresd board
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
York Sun
f749db3a75 ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting
  Support DDR3 and DDR4 as separated targets
  Management Complex (MC) is enabled
  Support for GIC 500 (based on GICv3 arch)

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2014-07-04 19:48:41 +02:00
Albert ARIBAUD
d6694aff56 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-06-30 23:00:34 +02:00
Albert ARIBAUD
ed1d98d801 Merge branch 'u-boot/master' into 'u-boot-arm/master' 2014-06-25 10:39:58 +02:00
Masahiro Yamada
e6af385989 freescale: m5253demo: fix unused-but-set-variable warnings
Fix the following warning messages:

In function 'flash_erase': 180:21:
warning: variable 'last' set but not used [-Wunused-but-set-variable]
In function 'write_buff':  322:10:
warning: variable 'port_width' set but not used [-Wunused-but-set-variable]

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2014-06-19 11:18:43 -04:00
Fabio Estevam
a81c90f4c8 mx28evk: Add documentation on how to boot from SPI NOR
Explain the necessary steps in order to boot from SPI NOR.

Based on a earlier submission from Mårten Wikman.

Signed-off-by: Mårten Wikman <marten.wikman@novia.fi>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-06-17 16:39:10 +02:00
Simon Glass
6469a34678 mx31ads: Fix the U-Boot binary output
Correct the binary output so that image_binary_size is really at the
end of the image.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-11 16:25:39 -04:00
Chao Fu
cb6d04d606 arm: vf610: Add QSPI support for VF610TWR
Add QSPI support for VF610TWR, such as clock and iomux.

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
2014-06-09 09:18:15 +02:00
Tom Rini
3e1fa221f9 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-06-05 17:38:30 -04:00
Masahiro Yamada
26bf6d77a6 nand_spl: remove P1023RDS_NAND support
Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-06-05 17:01:58 -04:00
poonam aggrwal
fa6e742825 powerpc/B4420: Fixed incomplete handling for 0x9d serdes2
Crossbars and IDT were not getting configured for Serdes2 protocol
0x9d for B4420.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Chunhe Lan
e6c334a7a4 powerpc/t4rdb: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
only using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
VCO, this need to use alternate serdes protocols. Alternate
option has the same functionality as the original option; the
only difference being LC VCO rather than Ring VCO.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:56:13 -07:00
Shengzhou Liu
40483e1e1d board/t2080qds: some update for ddr
- add support for 2nd DIMM slot.
- make it work with DIMM which is less than 2GB.

Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:56:06 -07:00
Shaohui Xie
94752f60eb powerpc/t4qds: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
VCO. Only the protocols using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:55:59 -07:00
Shengzhou Liu
9752eb6426 board/t208x: update t2080qds/t2080rdb for errata A-007186
As errata A-007186, we need to use the alternate serdes
protocol instead of those impacted protocols.

- add support for serdes protocols: 0x1b, 0x50, 0x5e,
  0x64, 0x6a, 0xd2, 0x67, 0x70.
- update t2080_rcw.cfg to adapt to new rcw_66_15 for
  t2080qds and t2080rdb.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:55:39 -07:00
Masahiro Yamada
facb6725c3 powerpc: mpc8260ads: remove orphan board
This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denx <wd@denx.de>
2014-05-30 14:03:24 -04:00
Fabio Estevam
66ca09fc41 mx6sabred: Add PFUZE100 PMIC support
mx6sabresd boards have a PFUZE100 PMIC connected to I2C2 bus.

Add support for it

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-05-28 17:35:39 +02:00
Fabio Estevam
186feb0b4d mx6sabreauto: Add the mx6dual-lite variant
Tested by booting a mainline kernel via TFTP.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-05-28 17:23:24 +02:00
Stefan Agner
56d83d1c04 arm: vf610: add DDR_SEL_PAD_CONTR register
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-05-25 15:46:12 +02:00
Albert ARIBAUD
05d134b084 Merge remote-tracking branch 'u-boot/master'
Conflicts:
	boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
2014-05-20 10:05:42 +02:00
Prabhakar Kushwaha
bc2d40ca10 board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL
In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:27 -05:00
Tang Yuantian
0f1fa36fff powerpc/t104xrdb: Toggle deep sleep management signals after resume
T104xrdb has several sleep management signals that are used for deep
sleep. They are enabled by OS to enter deep sleep and should be
disabled by u-boot when cores wake up.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Ebony Zhu
477c894ff4 board/freescale: Move CRC32 offset in NXID v1 data format
According to AN3638, CRC of NXID v1 is at the end of the
256-byte I2C memory. The wrong CRC32 offset prevents Uboot
from reading system information from EEPROM. No NXID v0 is
being used on Freescale boards.

Signed-off-by: Ebony Zhu <b45385@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:05 -05:00
Albert ARIBAUD
6a2f30a03a Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-05-16 17:56:50 +02:00
Albert ARIBAUD
41623c91b0 arm: move exception handling out of start.S files
Exception handling is basically identical for all ARM targets.
Factorize it out of the various start.S files and into a
single vectors.S file, and adjust linker scripts accordingly.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-05-15 16:24:53 +02:00
Stefano Babic
e7f9350525 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-05-15 10:27:32 +02:00
York Sun
bffac7aef5 powerpc/freescale: Change the return value of mac_read_from_eeprom()
The return value has not been checked by its caller, until recent change
of using generic board architecture. The error of this function is not
critical enough to hang the system. Printing the warning message is enough
to catch user's attention. U-boot should continue to boot to give user
a chance to fix the EEPROM. Chaning the return value to 0 to avoid hanging
in the board_init_r().

Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-13 08:31:22 -07:00
Alexander Graf
b539534d12 PPC 85xx QEMU: Always assume 1 core
We only need u-boot to bother about a single core in the QEMU machine.
Everything that would require additional knowledge of more cores gets
handled by QEMU and passed straight into the payload we execute.

Because of this setup, it would be counterproductive to enable SMP support
in u-boot. We would have to rip CPUs out of already existing spin tables
and respin them from u-boot. It would be a pretty big mess.

So only assume we have a single core. This fixes errors about CONFIG_MP
being disabled.

Signed-off-by: Alexander Graf <agraf@suse.de>
2014-05-13 08:26:55 -07:00
Chunhe Lan
0b2e13d9cc powerpc/85xx: Add T4240RDB board support
T4240RDB board Specification
----------------------------
Memory subsystem:
   6GB DDR3
   128MB NOR flash
   2GB NAND flash

Ethernet:
   Eight 1G SGMII ports
   Four 10Gbps SFP+ ports

PCIe:
   Two PCIe slots

USB:
   Two USB2.0 Type A ports

SDHC:
   One SD-card port

SATA:
   One SATA port

UART:
   Dual RJ45 ports

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
2014-05-13 08:24:32 -07:00
Shaveta Leekha
652e29b4a0 board/b4qds: VID support
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.

B4860QDS has a PowerOne ZM7300 programmable digital Power
Manager which is programmed as per the value read from
the fuses.

Reference for this code is taken from t4qds VID implementation.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2014-05-13 08:20:31 -07:00
Shaveta Leekha
4150f24290 board/freescale/common: ZM7300 driver
Adds Support for PowerOne ZM7300 voltage regulator.
This device is available on some Freescale Boards like B4860QDS
and has to be programmed to adjust the voltage on the board.

The device is accessible via I2C interface.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
2014-05-13 08:20:31 -07:00
Fabio Estevam
694c3bc107 mx6slevk: Add SPI NOR flash support
mx6slevk has a m25p32 SPI NOR flash connected to ESCSPI port.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-04-28 14:00:16 +02:00
Shaohui Xie
b6036993eb powerpc/T4QDS: add two stage boot of nand/sd
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:53 -07:00
Shaohui Xie
cb753850e8 powerpc/t4240: updated RCW and PBI for rev2.0
Updated the RCW for rev2.0 which uses new frequency settings as below:

Clock Configuration:
CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz,
CCB:733.333 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz
FMAN1: 733.333 MHz
FMAN2: 733.333 MHz
QMAN:  366.667 MHz
PME:   533.333 MHz

Remove workaround of IFC bus speed and SERDES A-006031 of rev1.0.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:53 -07:00
Shengzhou Liu
ef531c7357 board/t2080rdb: some update for t2080rdb
- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
  ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
  previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Shengzhou Liu
4d66668300 board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
to u-boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Shengzhou Liu
b19e288f47 board/t208xqds: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
control to u-boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Shaohui Xie
b0615f0bd2 powerpc/t1040rdb: added a break in switch case
There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it
will fall into case PHY_INTERFACE_MODE_RGMII.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
Prabhakar Kushwaha
18c0144542 board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
      - Add spl.c which defines board_init_f, board_init_r
      - update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Prabhakar Kushwaha
c5dfe6ec58 board/b4qds:Add support of 2 stage NAND boot-loader
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
  - Add spl.c which defines board_init_f, board_init_r
  - update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:51 -07:00
Zhao Qiang
6259e29134 T1040QDS/U-QE: Add u-qe support to t1040qds
Add u-qe support for t1040qds

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Tang Yuantian
5303a3dea9 mpc85xx: Add deep sleep support on T104xRDB
Add deep sleep support on T104xRDB platforms.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Tang Yuantian
48f6a9a2bf mpc85xx: Add deep sleep support on T1040QDS
Add deep sleep support on T1040QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
Prabhakar Kushwaha
55153d6c30 board/t104xrdb: Add support of CPLD
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

This support of CPLD includes
 - files and register defintion
 - Commands to swtich alternate bank and default bank

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
c60dee03c0 mpc85xx/T1040QDS_D4: Add DDR4 support
T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Prabhakar Kushwaha
6b50f62cc4 board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ.  It violates the IEEE specs.

So Slow MDC clock to comply IEEE specs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Alexander Graf
fa08d39517 PPC 85xx: Add qemu-ppce500 machine
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.

It also provides more PCI slots and is supposed to be enumerated by
device tree only.

This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:45 -07:00
Eric Benard
d84187ac75 mx6sabresd: use common detect_hdmi
Signed-off-by: Eric Bénard <eric@eukrea.com>
2014-04-15 12:23:57 +02:00
Eric Benard
053b795e30 mx6sabresd: use common board_video_skip
Signed-off-by: Eric Bénard <eric@eukrea.com>
2014-04-15 12:23:56 +02:00
Marcel Ziswiler
0883b0b58e arm: vf610: fix double iomux configuration for vf610twr board
Get rid of double VF610_PAD_DDR_A15__DDR_A_15 iomux configuration.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-04-07 20:15:52 +02:00
Stefano Babic
1cad23c5f4 Merge branch 'master' of git://git.denx.de/u-boot-arm into master
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-04-04 11:35:30 +02:00
Marek Vasut
31c832f93c arm: mx5: Avoid hardcoding memory sizes on MX53QSB
The DRAM size can be easily detected at runtime on i.MX53. Implement
such detection on MX53QSB and adjust the rest of the macros accordingly
to use the detected values.

An important thing to note here is that we had to override the function
for trimming the effective DRAM address, get_effective_memsize(). That
is because the function uses CONFIG_MAX_MEM_MAPPED as the upper bound of
the available DRAM and we don't have gd->bd->bi_dram[0].size set up at
the time the function is called, thus we cannot put this into the macro
CONFIG_MAX_MEM_MAPPED . Instead, we use custom override where we use the
size of the first DRAM block which we just detected.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2014-03-31 18:28:51 +02:00
Marek Vasut
e919aa23ef ARM: mx6: Add PCIe on SabreSDP
Add support for PCIe on MX6 SabreSDP board and enable the support
in the config file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Liu Ying <Ying.Liu@freescale.com>
2014-03-31 18:28:50 +02:00
Masahiro Yamada
ba650e9b52 m68k: Remove M5271EVB and idmr board support
CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it
as 1000000 and idmr.h defines it as (50000000 / 64).

When compiling these two boards, a warning message is displayed:

  time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000
  and should not be defined by platforms" [-Wcpp]

There are no board maintainers for them so this commit just
deletes them.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jason Jin <Jason.jin@freescale.com>
2014-03-10 11:38:13 -04:00
Priyanka Jain
96ac18c9cc powerpc/t104xrdb: Update DDR initialization related settings
Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
 two Chip selects.
-Update board_specific_parameters udimm structure with settings
 derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
 but on T104xRDB, on setting this , DDR instability is observed.
 Board-level debugging is in progress.

Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2014-03-07 14:53:48 -08:00
Priyanka Jain
337b0c52b3 powerpc/t1040qds: Add Video - HDMI support
T1040 has internal display interface unit (DIU) for driving video.
T1040QDS supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder

Chrontel, CH7301C encoder which is I2C programmable is used as
HDMI connector on T1040QDS.
This patch add support to
-enable Video interface for T1040QDS
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1040
-program HDMI encoder via I2C on board

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:53:40 -08:00
Shengzhou Liu
8d67c3685e powerpc/t2080rdb: Add T2080PCIe-RDB board support
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.

T2080PCIe-RDB Feature Overview
------------------------------
Processor:
 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
 - Single memory controller capable of supporting DDR3 and DDR3-LP devices
 - 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
 - Two 10M/100M/1G RGMII ports on-board
 - Two 10Gbps SFP+ ports on-board
 - Two 10Gbps Base-T ports on-board
Accelerator:
 - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
 - SerDes-2 Lane G-H: to SATA1 & SATA2
IFC/Local Bus:
 - NOR:  128MB 16-bit NOR flash
 - NAND: 512MB 8-bit NAND flash
 - CPLD: for system controlling with programable header on-board
eSPI:
 - 64MB N25Q512 SPI flash
USB:
 - Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
 - One PCIe x4 gold-finger
 - One PCIe x4 connector
 - One PCIe x2 end-point device (C293 Crypto co-processor)
SATA:
 - Two SATA 2.0 ports on-board
SDHC:
 - support a TF-card on-board
I2C:
 - Four I2C controllers.
UART:
 - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:53:13 -08:00
Shengzhou Liu
6b7679c8d2 powerpc/t208xqds: fixup for t208xqds
Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0.
Fix EMI2 for t2080qds, which was caused by adding t2081qds.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:52:41 -08:00
Shaveta Leekha
7af9a07403 powerpc/b4860: Add workaround for errata A006384 and A006475
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration

Both these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:52:01 -08:00
Shaveta Leekha
c4930b1a0e B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to work
Change setting of SerDes2 refclk2 to have the default value as it is
coming on board that is 156.25MHz, for XFI to work.
Also change PLL_NUM variable to the one defined in config_mpc85xx.h
for B4860 and B4420.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:50:56 -08:00
poonam aggrwal
c7d506d4ee 85xx/b4860: Alternate serdes protocols for B4860/B4420
On B4860 and B4420, some serdes protocols can be used with LC VCO as
well as Ring VCO options.

Addded Alternate options with LC VCO for such protocols.
For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO.

The alternate option has the same functionality as the original option;
the only difference being LC VCO rather than Ring VCO.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:50:00 -08:00
Shaveta Leekha
fb07c0a16d board/b4860qds: Add support to make PCIe SATA work on B4860QDS
1) SerDes2 Refclks have been set properly to make
     PCIe SATA to work as it work on SerDes refclk of 100MHz
  2) Mask the SerDes's device reset request before changing
     the Refclks for SerDes1 and SerDes2 for PLL locks to
     happen properly, device reset request bit unmasked
     after SerDes refclks configuration

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:49:45 -08:00
Shaveta Leekha
5e5097c110 board/b4860qds: Add support to make Aurora work on B4860QDS
1) Add new SerDes1 protocols having Aurora in them
2) Add VSC cross point connections for Aurora to work with
   CPRI and SGMIIs
3) Configure VSC crossbar switch to connect SerDes1
   lanes to aurora on board, by checking SerDes1 protocols
4) SerDes1 Refclks have been set properly to make
   Aurora, CPRI and SGMIIs to work together properly

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:49:16 -08:00
Masahiro Yamada
e0708fb539 board: config.mk: delete unused sinclude directive
config.tmp is not there.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-03-04 12:15:31 -05:00
Alexey Brodkin
1ace402239 sizes.h - consolidate for all architectures
Copied from Linux sources "include/linux/sizes.h" commit
413541dd66d51f791a0b169d9b9014e4f56be13c

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch]
Signed-off-by: Tom Rini <trini@ti.com>
2014-03-04 12:15:01 -05:00
Tom Rini
eeb72e6761 Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	arch/arm/cpu/armv7/config.mk
	board/ti/am43xx/mux.c
	include/configs/am43xx_evm.h

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-26 16:49:58 -05:00
Albert ARIBAUD
d0b5d9da5d arm: make _end compiler-generated
This prevents references to _end from generating absolute
relocation records.

This change is binary invariant for ARM targets.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-02-26 21:18:09 +01:00
Tom Rini
a7e8c15f71 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-02-25 13:55:49 -05:00
Ying Zhang
c9e1f58818 powerpc: p1010rdb: Enable p1010rdb to start from NAND/SD/SPI flash with SPL
In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:23:32 -08:00
Shengzhou Liu
254887a57e powerpc/t2081qds: Add T2081 QDS board support
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:23:01 -08:00
York Sun
e38661634b common: Add get_effective_memsize() to memsize.c
This function has been around for powerpc. It is used for systems with
memory more than CONFIG_MAX_MEM_MAPPED. In case of non-contiguous memory,
this feature can limit U-boot to one block without going over the limit.

Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-02-21 11:06:13 -05:00
Albert ARIBAUD
3e11350255 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	Makefile
	drivers/net/npe/Makefile

These two conflicts arise from commit 0b2d3f20
("ARM: NET: Remove the IXP NPE ethernet driver") and are
resolved by deleting the drivers/net/npe/Makefile file
and removing the CONFIG_IXP4XX_NPE line from Makefile.
2014-02-20 13:16:05 +01:00
Masahiro Yamada
365475e6d1 Move #ifdef(CONFIG_DISPLAY_CPUINFO) from caller to callee
- When CONFIG_DISPLAY_CPUINFO is not enabled,
   print_cpuinfo() should be defined as an empty function
   in a header, include/common.h

 - Remove #ifdef CONFIG_DISPLAY_CPUINFO .. #endif
   from caller, common/board_f.c and arch/arm/lib/board.c

 - Remove redundant prototypes in arch/arm/lib/board.c,
   arch/arm/include/asm/arch-am33x/sys_proto.h and
   board/nokia/rx51/rx51.h, keeping the one in include/common.h

 - Add #ifdef CONFIG_DISPLAY_CPUINFO to the func definition
   where it is missing

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-02-19 11:10:05 -05:00
Masahiro Yamada
7c8278a866 kbuild: add dummy obj-y to create built-in.o
We are going to switch over to Kbuild in upcoming commits.

Each makefile must have non-empty obj- or obj-y
to generate built-in.o on Kbuild.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-02-19 11:07:50 -05:00
Albert ARIBAUD
e7538fee99 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-02-19 12:04:45 +01:00
Stefano Babic
17998eff90 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-02-11 12:55:32 +01:00
Fabio Estevam
4702c62dce mx6qsabreauto: Update imximage.cfg
Use the latest DDR and clock settings as the one from Freescale BSP.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-02-11 11:24:12 +01:00
Priyanka Jain
714fd406da powerpc/t104xrdb: Add basic ethernet support
This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both T1040RDB and T1042RDB_PI

T1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5
    1 SGMII on DTSEC3

T1042RDB_PI is configured as serdes protocol 0x06 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change in commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:49 -08:00
Prabhakar Kushwaha
5b7672fc49 boards/t1040qds: Adds ethernet support for T1040
Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
    Define MDIO related configs
    Added eth.c file
    Update t1040.c to support RGMII and SGMII
    Update t1040qds.c to support ethernet
    Define the PHY address

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: remove dash from commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:48 -08:00
Prabhakar Kushwaha
e7222b5f49 powerpc/mpc85xx:Fix README to show correct flash memory map
Due to increased size of u-boot, FMAN ucode start address has been shifted
by 256KB causing a overlap with rootfs start address.

Update rootfs start address to reflect correct memory map.

Also fix minor typo in README

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-03 08:38:48 -08:00
Haijun.Zhang
f28bea0003 eSDHC: Calculate envaddr accroding to the address format
On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need to convert the block address format
to byte address format to calculate the envaddr.

If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.

Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-22 08:56:44 -08:00
Prabhakar Kushwaha
e222b1f36f powerpc/mpc85xx:Increase binary size for P, B & T series boards.
u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.

So, Increase the u-boot binary size to 768KB.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-01-21 14:06:30 -08:00
Shengzhou Liu
3fdc827ca8 t2080qds/ddr: update ddr parameters
- Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
- Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are
  unrelated to DDR3/3L.

Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 14:02:21 -08:00
Po Liu
eb6b458cef powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
Using the TPL/SPL method to booting from 8k page NAND flash.
	- Add 256kB size SRAM tlb for second step booting;
	- Add spl.c for TPL image boot;
	- Add spl_minimal.c for minimal SPL image;
	- Add C29XPCIE_NAND configure;
	- Modify C29XPCIE.h for nand config and enviroment;

Signed-off-by: Po Liu <Po.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:42:40 -08:00
Shengzhou Liu
1576b558b9 powerpc/t2080qds: some update for t2080qds
- add more serdes protocols support.
- fix some serdes lanes route.
- fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d.
- correct boot location info for SD/SPI boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:37:41 -08:00
Priyanka Jain
2eb3ac7fe8 powerpc/t1040qds: Update DDR initialization related settings
Update following DDR related settings for T1040QDS
-Correct number of chip selects to two as t1040qds supports
 two Chip selects.
-Update board_specific_parameters udimm structure with settings
 derived via calibration.
-Reduced I2C speed to 50KHz as DDR-SPD does not get reliably
 read at 400KHz.

Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and
1600MT/s.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-21 13:35:20 -08:00
Albert ARIBAUD
bf46e7d8d1 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-01-15 15:18:04 +01:00
Fabio Estevam
5f98d0b5d3 mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency
that will be generated.

No changes are made to mx6slevk, which uses the default 50MHz fec clock.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-01-15 10:33:25 +01:00
Albert ARIBAUD
e6fe4bd989 Merge 'u-boot-imx/master' into 'u-boot-arm/master' 2014-01-14 11:50:54 +01:00
Fabio Estevam
12c20c0c9b mx6slevk: Return from cpu_eth_init() directly
There is no need to print an error message when cpu_eth_init() fails because
net/eth.c already prints it.

In order to simplify the code, just return the value from cpu_eth_init(bis)
directly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-13 11:52:28 +01:00
Fabio Estevam
92c707a580 mx6sabresd: Return from cpu_eth_init() directly
There is no need to print an error message when cpu_eth_init() fails because
net/eth.c already prints it.

In order to simplify the code, just return the value from cpu_eth_init(bis)
directly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-13 11:52:27 +01:00
Fabio Estevam
579be2f760 mx6qsabreauto: Return from cpu_eth_init() directly
There is no need to print an error message when cpu_eth_init() fails because
net/eth.c already prints it.

In order to simplify the code, just return the value from cpu_eth_init(bis)
directly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-13 11:52:27 +01:00
Fabio Estevam
1037dc0a2b mx6qarm2: Remove unneeded error message when cpu_eth_init() fails
There is no need to print an error message when cpu_eth_init() fails because
net/eth.c already prints it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-01-13 11:52:27 +01:00
Tom Rini
7f673c99c2 Merge branch 'master' of git://git.denx.de/u-boot-arm
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.

Conflicts:
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
2014-01-10 10:56:00 -05:00
Albert ARIBAUD
a891601ce5 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	include/micrel.h

The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
2014-01-06 08:49:58 +01:00
Prabhakar Kushwaha
8c618dd66a board/t1040qds: Enable memory reset control
Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start
accessing it.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-01-02 14:10:14 -08:00
Shaohui Xie
3bce144b46 powerpc/b4860/pbl: fix rcw cfg
The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2014-01-02 14:10:14 -08:00
Prabhakar Kushwaha
fbe76ae4e3 board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL
CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary
review purpose.

So, use CONFIG_SPL_NAND_BOOT config.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-01-02 14:10:13 -08:00
Prabhakar Kushwaha
be3d87ea44 board/t1040qds: Fix typo in t1040_pbi.cfg file
T1040QDS has 256KB SRAM. Comment is showing wrong information.

So update the comment.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-01-02 14:10:12 -08:00
Fabio Estevam
119e990986 mx6sabresd: Fix LVDS width and color format
mx6sabresd boards have a 18-bit LVDS data width and the correct color format
is RGB666.

Suggested-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-12-17 18:38:42 +01:00
Fabio Estevam
be4ab3dd05 mx6sabresd: Allow probing HSYNC, VSYNC and DISP_CLK signals
HSYNC, VSYNC and DISP_CLK are very useful display signals for debugging.

Configure them as active pins.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-12-17 18:38:42 +01:00
Liu Ying
1230743731 MX6 SabreSD: Use readl() to read the CCM_CCGR3 register
Align with the context to use readl() to read the CCM_CCGR3
register with memory barrier instead of __raw_readl().

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-12-17 18:38:42 +01:00
Eric Nelson
b47abc36aa i.MX6 (DQ/DLS): use macros for mux and pad declarations
This allows the use of either or both declarations from
the files mx6q_pins.h and mx6dl_pins.h.

All board files should include <asm/arch/mx6-pins.h>
with one of the following defined in boards.cfg
    MX6Q   - for boards targeting i.MX6Q or i.MX6D
    MX6DL  - for boards targeting i.MX6DL
    MX6S   - for boards targeting i.MX6S
    MX6QDL - for boards that support any of the above with
             run-time detection

Pad declarations will be MX6_PAD_x for single-variant boards
and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both
processor classes.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-12-17 17:12:34 +01:00
Fabio Estevam
570aa2fac3 imx: Explicitly pass the I2C bus number in pmic_init()
The pmic_init() function has the I2C or SPI bus number that is connected to the
PMIC.

Instead of passing I2C_PMIC, explicitly pass the I2C bus number via I2C_x
definition.

The motivation for doing this is to avoid people just doing a copy and paste
of I2C_PMIC into their board file when another I2C bus is actually used to
interface to their PMIC.

This also makes more obvious which is the I2C bus connected to the PMIC, without
having to search in the source code for the meaning of the 'I2C_PMIC' number.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-12-17 16:54:16 +01:00
Masahiro Yamada
878a095e44 Makefile: delete unnecessary CPPFLAGS settings
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-12-13 09:18:45 -05:00
Claudiu Manoil
5037947a02 powerpc/p1_p2_rdb_pc: Fix warnings for __iomem pointers
Add the __iomem address space marker for the tsec pointers
to struct tsec_mii_mng memory mapped register regions.
This solves the sparse warnings for mixig normal pointers with
__iomem pointers for tsec.

p1_p2_rdb_pc.c:373:24: warning: incorrect type in assignment (different
address spaces)
p1_p2_rdb_pc.c:373:24:    expected struct tsec_mii_mng [noderef]
<asn:2>*regs
p1_p2_rdb_pc.c:373:24:    got struct tsec_mii_mng *<noident>

Use TSEC_GET_MDIO_REGS_BASE() for the remaining mdio 'regs'
initializations to remove the __iomem warnings and for consistency.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-11 11:12:29 -08:00
Tom Rini
4b210ad342 Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	board/samsung/trats2/trats2.c
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-12-10 17:15:18 -05:00
Albert ARIBAUD
f15ea6e1d6 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	arch/arm/cpu/armv7/rmobile/Makefile
	doc/README.scrapyard

Needed manual fix:
	arch/arm/cpu/armv7/omap-common/Makefile
	board/compulab/cm_t335/u-boot.lds
2013-12-10 22:23:59 +01:00
Albert ARIBAUD
47ed5dd031 arm: keep all sections in ELF file
Current LDS files /DISCARD/ a lot of sections when linking ELF
files, causing diagnostic tools such as readelf or objdump to
produce partial output. Keep all section at link stage, filter
only at objcopy time so that .bin remains minimal.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-12-07 06:53:58 +01:00
Po Liu
380b8f307c powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROM
Currently, there is only one EEPROM on c29xpcie board which is AT24C1024.
We program the SPD data at beginning of the AT24C1024.But the AT24C1024
has a 16-bit sub-address mode. This patch is tomake it work when getting
SPD in a 16-bit sub-address EEPROM.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-04 14:54:32 -08:00
Fabio Estevam
8bfa9c692e mx6sabresd: Add SPI NOR support
mx6sabre board has a m25p32 SPI NOR connected to ECSPI1 port.

Add support for it.

This patch allows the SPI NOR flash to be succesfully detected:

=> sf probe
SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-11-28 08:28:53 +01:00
Fabio Estevam
b48e3b0410 mx6sabresd: Fix wrong colors in LVDS splash
Currently HDMI splash screen is selected by default on mx6sabresd boards.

As LVDS is also enabled, this causes incorrect colors to be displayed im the
LVDS panel.

Fix this by selecting the LVDS panel as the default splash output and only keep
HDMI or LVDS turned on at the same time.

Acked-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-11-28 08:28:53 +01:00
Fabio Estevam
4e785c6ae9 mx31pdk: Fix pmic_init() argument
On mx31pdk board the PMIC is connected via SPI interface, so it does not make
sense to pass I2C_PMIC into the pmic_init() interface.

Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-11-27 09:39:21 +01:00
Fabio Estevam
56f9cfbb48 mx51evk: Fix pmic_init() argument
On mx51evk board the PMIC is connected via SPI interface, so it does not make
sense to pass I2C_PMIC into the pmic_init() interface.

Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-11-27 09:39:21 +01:00
Shengzhou Liu
f7f155e1e1 t2080qds/ramboot: enable PBL tool for t2080qds
Add the default RCW(SerDes 0x66_0x16) and PBI configure file for
T2080QDS board, so we can use PBL tool to generate the ramboot
image to support boot from NAND/SPI/SD.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-11-25 12:36:55 -08:00
Shengzhou Liu
c4d0e81156 powerpc/t2080qds: add support for t2080qds board
The T2080QDS is a high-performance computing evaluation, development and
test platform supporting the T2080 QorIQ Power Architecture processor.

T2080QDS feature overview
Processor:
 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
 - Single memory controller capable of supporting DDR3 and DDR3-LV devices
 - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
Ethernet interfaces:
 - Two 1Gbps RGMII on-board ports
 - Four 10Gbps XFI on-board cages
 - 1Gbps/2.5Gbps SGMII Riser card
 - 10Gbps XAUI Riser card
Accelerator:
 - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
 - 16 lanes up to 10.3125GHz
 - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
 - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
 - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
 - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
 - Two SATA 2.0 ports on-board
SRIO:
 - Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
 - Supports SD/SDHC/SDXC/eMMC Card
I2C:
 - Four I2C controllers.
UART:
 - Dual 4-pins UART serial ports
System Logic:
 - QIXIS-II FPGA system controll
Debug Features:
 - Support Legacy, COP/JTAG, Aurora, Event and EVT

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: removed Makefile blank line at EOF,
           fix conflicts with moving DDR driver]
Acked-by: York Sun <yorksun@freescale.com>
2013-11-25 12:36:11 -08:00
York Sun
0b66513b27 Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:47 -08:00
York Sun
9a17eb5b7e Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
5614e71b49 Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:43 -08:00
Masahiro Yamada
e2906a5943 Makefile: rename all libraries to built-in.o
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:32 -05:00
Masahiro Yamada
1b2226e0ce Makefile: specifiy an explicite object name rather than $(BOARD).o
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:30 -05:00
Masahiro Yamada
620110afe5 board: Do not add -DCONFIG_SYS_TEXT_BASE in board config.mk
Board config.mk do not need to add -DCONFIG_SYS_TEXT_BASE
to CPPFLAGS because the top level config.mk does instead.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:29 -05:00
Priyanka Jain
0d7ba2ea43 powerpc/t104xrdb: Add T1042RDB_PI board support
T1042RDB_PI is Freescale Reference Design Board supporting the T1042
QorIQ Power Architecture™ processor. T1042 is a reduced personality
of T1040 SoC without Integrated 8-port Gigabit. The board is designed
with low power features targeted for Printing Image Market.

T1042RDB_PI is  similar to T1040RDB board with few differences like
it has video interface, supports T1042 personality

 T1042RDB_PI board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
    	management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Two on-board RGMII 10/100/1G ethernet ports.
 - SERDES Connections, 8 lanes supporting:
      — PCI
      — SATA 2.0
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
     - NAND flash: 1GB 8-bit NAND flash
     - NOR: 128MB 16-bit NOR Flash
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
     - PHY #0 remains powered up during deep-sleep
 - CPLD
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Video
     - DIU supports video at up to 1280x1024x32bpp
     - HDMI connector
 - Power Supplies
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     - Two type A ports with 5V@1.5A per port.
 - SDHC
     - SDHC/SDXC connector
 - SPI
     - On-board 64MB SPI flash
 - I2C
     - Device connected: EEPROM, thermal monitor, VID controller, RTC
 - Other IO
    - Two Serial ports
    - ProfiBus port
    - Four I2C ports

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2013-11-13 12:41:28 -08:00
Priyanka Jain
062ef1a662 powerpc/t104xrdb: Add T1040RDB board support
T1040RDB is Freescale Reference Design Board supporting
the T1040 QorIQ Power Architecture™ processor.

 T1040RDB board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
       management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
    - PCI
    - SGMII
    - QSGMII
    - SATA 2.0
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
    - NAND flash: 1GB 8-bit NAND flash
    - NOR: 128MB 16-bit NOR Flash
 - Ethernet
    - Two on-board RGMII 10/100/1G ethernet ports.
    - PHY #0 remains powered up during deep-sleep
 - CPLD
 - Clocks
    - System and DDR clock (SYSCLK, “DDRCLK”)
    - SERDES clocks
 - Power Supplies
 - USB
    - Supports two USB 2.0 ports with integrated PHYs
    - Two type A ports with 5V@1.5A per port.
 - SDHC
    - SDHC/SDXC connector
 - SPI
    - On-board 64MB SPI flash
 - I2C
    - Devices connected: EEPROM, thermal monitor, VID controller
 - Other IO
    - Two Serial ports
    - ProfiBus port

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefile]
Acked-by: York Sun <yorksun@freescale.com>
2013-11-13 12:41:28 -08:00
Shengzhou Liu
62af7615eb powerpc/p1010rdb: update readme for p1010rdb-pa and p1010rdb-pb
- Remove duplicate doc/README.p1010rdb
- Rename README to README.P1010RDB-PA
- Add new README.P1010RDB-PB

P1010RDB-PB is a variation of previous P1010RDB-PA board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-11-13 11:12:48 -08:00
Prabhakar Kushwaha
439fbe75a0 powerpc/t1040: enable PBL tool for T1040
Use a default RCW of protocol 0x66.
A PBI configure file which uses CPC as 256KB SRAM. It can be used by
PBL tool on T1040 to build a pbl boot image.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-11-13 11:08:08 -08:00
Eric Nelson
10fda48779 i.MX6DQ/DLS: replace pad names with their Linux kernel equivalents
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-11-13 10:19:50 +01:00
Stefan Roese
c2cde27d58 mx6: titanium: Move BSP code to barco board directory
Since the titanium board is not a Freescale board, move its
BSP code from the freescale board directory to the newly created
barco board directory.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Korsgaard <peter.korsgaard@barco.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Peter Korsgaard <peter.korsgaard@barco.com>
2013-11-13 10:09:10 +01:00
Fabio Estevam
90fb985863 titanium: Return the error when cpu_eth_init() fails
When cpu_eth_init() fails we should not return success.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefan Roese <sr@denx.de>
2013-11-13 10:09:10 +01:00
Masahiro Yamada
0f0f75774e cosmetic: remove empty lines at the top of file
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-08 09:41:37 -05:00
Masahiro Yamada
6e527f67df freescale: p1_p2_rdb_pc: rename COBJS-y to obj-y
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-06 08:50:28 -05:00
Tom Rini
8cbbb1098d board: powerpc: convert more makefiles to Kbuild style
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
2013-11-01 11:42:13 -04:00
Masahiro Yamada
377e1048d3 board: powerpc: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
2013-11-01 11:42:12 -04:00
Masahiro Yamada
a79854a90f board: arm: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Tom Rini <trini@ti.com>
2013-11-01 11:42:12 -04:00
Masahiro Yamada
64bd89e437 m68k: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jason Jin <Jason.jin@freescale.com>
2013-11-01 11:42:12 -04:00
Valentin Longchamp
935b402eae fsl/mpc85xx: define common serdes_clock_to_string function
This allows to share some common code for the boards that use a corenet
base SoC.

Two different versions of the function are available in
fsl_corenet_serdes.c and fsl_corenet2_serdes.c files.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix t1040qds.c]
Acked-by: York Sun <yorksun@freescale.com>
2013-10-24 09:36:18 -07:00
Po Liu
9c25ee6d3a powerpc/c29xpcie: add DDR ECC on off config setting
c29xpcie REV_A board DDR ECC chip has bad impedance in hardware,
force that kind of board to be DDR ECC off when booting.
Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on
in uboot enviroment.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-10-24 09:34:56 -07:00
Prabhakar Kushwaha
787964b811 boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLD
NAND,CPLD AMASK register is programmed for 64K size.

so Update TLB & LAW size accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:15:17 -07:00
Shengzhou Liu
e512c50bc9 powerpc/p1010rdb: add p1010rdb-pb support with updating p1010rdb-pa
- Rename old P1010RDB board as P1010RDB-PA.
- Add support for new P1010RDB-PB board.
- Some optimization.

For more details, see board/freescale/p1010rdb/README.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix conflicts in boards.cfg]
Acked-by: York Sun <yorksun@freescale.com>
2013-10-16 16:15:17 -07:00
Shengzhou Liu
ad89da0c33 board/p1010rdb: add pin mux and sdhc support in any boot
Since pins multiplexing, SDHC shares signals with IFC, with this patch:
To enable SDHC in case of NOR/NAND/SPI boot
   a) For temporary use case in runtime without reboot system
      run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
   b) For long-term use case
      set 'esdhc' in hwconfig and save it.
To enable IFC in case of SD boot
   a) For temporary use case in runtime without reboot system
      run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
   b) For long-term use case
      set 'ifc' in hwconfig and save it.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-10-16 16:15:17 -07:00
Shengzhou Liu
5536aeb09b powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROM
Some boards use System EEPROM with 128-bytes instead of 256-bytes.
Since we regard 256-bytes EEPROM as standard EEPROM with default
value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can
redefine MAX_NUM_PORTS in board-specific file to override the
default MAX_NUM_PORTS.

This patch doesn't impact on previous existing boards.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-10-16 16:15:17 -07:00
Shengzhou Liu
41c686d975 powerpc/p1010rdb: remove unused cpld_show
Function cpld_show() was for debug and not called, so clean it.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-10-16 16:15:16 -07:00
Prabhakar Kushwaha
7d436078fe powerpc/t1040qds: Add T1040QDS board
T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.

 T1040QDS board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
    	management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
      — PCI Express: supporting Gen 1 and Gen 2;
      — SGMII
      — QSGMII
      — SATA 2.0
      — Aurora debug with dedicated connectors
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
     - NAND flash: 8-bit, async, up to 2GB.
     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
     - GASIC: Simple (minimal) target within Qixis FPGA
     - PromJET rapid memory download support
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
     - PHY #0 remains powered up during deep-sleep
 - QIXIS System Logic FPGA
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Power Supplies
 - Video
     - DIU supports video at up to 1280x1024x32bpp
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     — Two type A ports with 5V@1.5A per port.
     — Second port can be converted to OTG mini-AB
 - SDHC
     - SDHC port connects directly to an adapter card slot, featuring:
     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
     — Supporting eMMC memory devices
 - SPI
    -  On-board support of 3 different devices and sizes
 - Other IO
    - Two Serial ports
    - ProfiBus port
    - Four I2C ports

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: York Sun <yorksun@freescale.com>
2013-10-16 16:15:16 -07:00
Priyanka Jain
0dd38a35f4 powerpc: Fix CamelCase warnings in DDR related code
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl

Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2013-10-16 16:15:16 -07:00
Shaohui Xie
83d925668f powerpc/B4860: enable PBL tool for B4860
Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-10-16 16:13:12 -07:00
Shaohui Xie
ef9a1f9a4f powerpc/t4240: updated rcw_cfg to align with default hardware configuration
Default configuration has been changed, the most important one is DDR
ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to
change from 24x to 12x to keep the DDR frequency. There are also some
other optimise to align with default configuration.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-10-16 16:13:12 -07:00
Ying Zhang
62c6ef336d powerpc: p1_p2_rdb_pc: add TPL for p1_p2_rdb_pc nand boot
Enable TPL for p1_p2_rdb_pc nand boot.

Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-10-16 16:13:12 -07:00
Ying Zhang
d34e56241d powerpc : p1_p2_rdb_pc : Enable p1_p2_rdb_pc to start from eSPI with SPL
Enable p1_p2_rdb_pc to start from eSPI with SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-10-16 16:13:12 -07:00
Ying Zhang
3e6e69834a powerpc: p1_p2_rdb_pc: Enable p1_p2_rdb_pc to boot from SD Card with SPL
Enable p1_p2_rdb_pc to start from eSDHC with SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-10-16 16:13:12 -07:00
Zhao Qiang
ffee1dde3c SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII mode
Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.

QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
	1. Confirm whether QSGMII Riser Card is used.
	2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.

However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16 16:13:11 -07:00
Zhao Qiang
d56898249c Corenet/p5040/SGMII:fix the problem for SGMII5/6
SGMII5/6 and SGMII7/8 are not on the same slot on P5040
according to the serdes protocol.
So it is not proper to organize SGMII5/6 and SGMII7/8
on one bus and SGMII5/6 can't work.
So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for
SGMII5/6

Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16 16:13:11 -07:00
Po Liu
0e61077b21 powerpc/c29xpcie: modify DDR parameter to make DDR more stable
DDR parameters clk_adjust were changed. This can make the DDR
run more stable. The new value were gotten by the DDR testing
tool.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-10-16 16:13:11 -07:00
Wolfgang Denk
d4c8aa9cb4 Coding Style cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
93e1459641 Coding Style cleanup: replace leading SPACEs by TABs
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-14 16:06:54 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Tom Rini
6297872cd5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-10-02 11:45:22 -04:00
Fabio Estevam
a05f4ab6cc mx35pdk: Fix error handling in board_late_init()
If smc911x_initialize() fails we should return the error immediately.

While at it, also check the error from cpu_eth_init().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-09-27 13:53:35 +02:00
Fabio Estevam
2cba60ac84 mx28evk: Propagate the error if cpu_eth_init() fails
If cpu_eth_init() fails we should return the error immediately.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-27 13:53:35 +02:00
Fabio Estevam
71d8b019d0 mx28evk: Fix checkpatch warning
Fix the following checkpatch warning:

$ ./tools/checkpatch.pl -F board/freescale/mx28evk/mx28evk.c
CHECK: Alignment should match open parenthesis
#109: FILE: freescale/mx28evk/mx28evk.c:109:
+	writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
+					&clkctrl_regs->hw_clkctrl_enet);

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20 17:55:37 +02:00
Fabio Estevam
31f07964c8 mx6slevk: Add Ethernet support
mx6slevk has a SMSC8720 connected in RMII mode.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20 17:55:37 +02:00
Fabio Estevam
e12408cc95 mx6qsabreauto: Return error if cpu_eth_init() fails
Currently board_eth_init() always return 0, but we should propagate the error
when cpu_eth_init() fails.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20 17:55:36 +02:00
Fabio Estevam
cb427fe1c4 mx6sabresd: Return error if cpu_eth_init() fails
Currently board_eth_init() always return 0, but we should propagate the error
when cpu_eth_init() fails.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20 17:55:36 +02:00
Fabio Estevam
59f46f4a73 mx6sabresd: Reset counter to prevent error message
If a HDMI cable is not connected, the following message is seen on boot:

CPU:   Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR
Board: MX6-SabreSD
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
No panel detected: default to HDMI
unsupported panel HDMI

Reset the 'i' variable to fix the 'unsupported panel' message.

This follows the same idea of commit 47ac53d7ae (imx: nitrogen6x/mx6qsabrelite:
Fix bug in board_video_skip).

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20 17:55:36 +02:00
Fabio Estevam
1601ba4d1e mx6sabresd: Avoid hang when HDMI cable is not connected
Since commit d9b894603 (mx6sabresd: Add LVDS splash screen support) the
following hang happens if the HDMI cable is not connected or the 'panel'
variable is not set:

U-Boot 2013.10-rc2-12978-g47ac53d-dirty (Sep 11 2013 - 15:07:38)

CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: POR
Board: MX6-SabreSD
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
...

Provide a check to 'dev->detect' in order to prevent the hang.

Reported-by: Pardeep Kumar Singla <b45784@freescale.com>
Suggested-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-20 17:55:36 +02:00
Robert P. J. Day
1bce2aeb6f Cosmetic: Fix a number of typos, no functional changes.
Fix various misspellings of things like "environment", "kernel",
"default" and "volatile", and throw in a couple grammar fixes.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2013-09-20 10:30:54 -04:00
Stefano Babic
c4a7ece020 Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	MAINTAINERS
	boards.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-09-13 12:10:07 +02:00
Fabio Estevam
d9b8946035 mx6sabresd: Add LVDS splash screen support
mx6sabresd boards can be connected to a Hannstar XGA LVDS panel.

Add support for displaying U-boot splashscreen on it.

By default, HDMI splash is selected.

In order to use splash via LVDS, do the following in the U-boot prompt:

setenv panel Hannstar-XGA
save

and reboot.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-09-10 19:12:55 +02:00
Marek Vasut
7b8657e2bd ARM: mxs: Receive r0 and r1 passed from BootROM
Make sure value in register r0 and r1 is preserved and passed to
the board_init_ll() and mxs_common_spl_init() where it can be
processed further. The value in r0 can be configured during the
BootStream generation to arbitary value, r1 contains pointer to
return value from CALL'd function.

This patch also clears the value in r0 before returning to BootROM
to make sure the BootROM is not confused by this value.

Finally, this patch cleans up some comments in the start.S file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-09-10 19:12:54 +02:00
Ying Zhang
81b867aa44 SPL: P1022DS: switch to new multibus/multiadapter support
- Added section "u_boot_list" in arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
- Use the function i2c_init_all instead of i2c_init

Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-09-09 07:43:43 +02:00
Shengzhou Liu
e1a2a34019 powerpc/p1010rdb: fix calculating ddr_freq_mhz
There was a bug for calculating ddr_freq_mhz,
it should be divided by 1000000 rather than 0x1000000.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:46:58 -07:00
Shaohui Xie
1c68d01eea powerpc/t4240: add QSGMII interface support
Also some fix for QSGMII.
1. fix QSGMII configure of Serdes2.
2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN.
3. fix dtb for QSGMII interface.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:46:48 -07:00
Shaohui Xie
ae3dcd0488 powerpc/t4240: fix lanes routing for QSGMII protocols
When using QSGMII protocols, the first lane and third lane on each slot
need to be swapped.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:46:39 -07:00
Shaohui Xie
7d0d355fee powerpc/common/vsc3316: remove const from vsc3316_config parameter define
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 10:46:26 -07:00
York Sun
bf90256623 SPDX-License-Identifier: clean up license header
This patch cleans up license header in these files:
	board/freescale/p1022ds/spl.c
	drivers/mmc/fsl_esdhc_spl.c
	drivers/mtd/spi/fsl_espi_spl.c

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-20 10:15:37 -07:00
Prabhakar Kushwaha
997399fa42 powerpc: Fix CamelCase checkpatch warnings
85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
because of this code checkpatch script generates "WARNING: Avoid CamelCase".

Convert variables name to normal naming convention and modify board, driver
files with updated the new structure.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:57:51 -07:00
Ying Zhang
5d97fe2a04 powerpc: p1022ds: add TPL for p1022ds nand boot
TPL is introduced in the patch "NAND: TPL : introduce the TPL
based on the SPL", here enable TPL for p1022ds nand boot.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:57:51 -07:00
Ying Zhang
382ce7e909 powerpc : p1022ds : Enable p1022ds to start from eSPI with SPL
Enable p1022ds to start from eSPI with SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:47:59 -07:00
Ying Zhang
7c8eea59b8 powerpc: p1022ds: Enable P1022DS to boot from SD Card with SPL
Enable p1022ds to start from eSDHC with SPL.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:47:38 -07:00
Tom Rini
e20cc2ca15 Merge branch 'master' of git://88.191.163.10/u-boot-arm
Fixup an easy conflict over adding the clk_get prototype and USB_OTG
defines for am33xx having moved.

Conflicts:
	arch/arm/include/asm/arch-am33xx/hardware.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-08-18 14:14:34 -04:00
Po Liu
2810312043 powerpc/c29xpcie: add readme document for c29xpcie
Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-08-14 10:58:34 -07:00
York Sun
3aab0cd852 powerpc/mpc85xx: Cleanup license header in source files
Fix the license header introduced by the following patches

Add TWR-P10xx board support
Add T4240EMU target
IDT8T49N222A configuration code
Add C29x SoC support
Add support for C29XPCIE board

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-12 15:04:24 -07:00
Mingkai Hu
a8d9758d01 powerpc/c29xpcie: add support for C29XPCIE board
C29XPCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module. It
includes C293PCIE board, C293PCIE board and C291PCIE board.

 - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
 - 512MB soldered DDR3 32bit memory
 - CPLD System Logic
 - 64MB x16 NOR flash and 4GB x8 NAND flash
 - 16MB SPI flash

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Singed-off-by: Po Liu <Po.Liu@freescale.com>
[yorksun: Fixup include/configs/C29XPCIE.h]
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:42 -07:00
Shaveta Leekha
cb033741f4 board/b4860qds: Add support for configuring SerDes1 Refclks
1) Add support in B4860 board files for using IDT driver where
   IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer
   that generate different refclks for SerDes modules, used this driver
   for reconfiguring SerDes1 Refclks(based on SerDes1 protocols)
   for CPRI to work. CPRI works on 122.88MHz and default refclks coming
   on board are not suitable for it
2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file
   to b4860qds board file, as SerDes1 Refclk1 would come from
   PHY MUX in case of certain protocols, that have been checked here.
   This change would make on board SGMIIs to work
3) Add I2C addresses for IDT8T49N222A devices in board/include file
4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:41 -07:00
Shaveta Leekha
a5b225181e board/freescale/common: IDT8T49N222A configuration code
Add code for configuring IDT8T49N222A device for various output refclks
    - The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer with
      alarm and monitoring functions suitable for networking and
      communications applications. It is able to generate wide range of output
      frequencies.
    - In B4860QDS, it has been used to generate different refclks to SerDes modules
    - Programming of these devices are performed by I2C interface.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
Priyanka Jain
f9d379a707 board/bsc9132qds: Configure DSP DDR controller
BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side
DDR. They are mapped to PowerPC and DSP CCSR space respectively.
BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC
and other to DSP side controller.

Configure DSP DDR controller similar to PowerPC side DDR controller as
memories are exactly similar.

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
Priyanka Jain
64501c6698 board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
Haijun.Zhang
45fdb627b3 p1020rdb-pd: platform support
Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB.
DDR changed from DDR2 1G to DDR3 2G.
NAND: 128 MiB
Flash: 64 MiB

Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:40 -07:00
York Sun
c63e137014 powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
5ecf41cc3d powerpc/t4240qds: Adjust DDR timing for RDIMM
RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for
dual rank. Single- and quad-rank are not tested due to availability.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
1cb19fbb31 powerpc/T4240EMU: Add T4240EMU target
Add emulator support for T4240. Emulator has limited peripherals and
interfaces. Difference between emulator and T4240QDS includes:
	ECC for DDR is disabled due the procedure to load images
	No board FPGA (QIXIS)
	NOR flash has 32-bit port for higher loading speed
	IFC and I2C timing don't really matter, so set them fast
	No ethernet

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
f165bc3528 powerpc/corenet: Move RCW print to cpu.c
The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
Xie Xiaobo
49f5befafd powerpc/85xx: Add TWR-P10xx board support
TWR-P1025 Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (on board DDR)
   64Mbyte 16bit NOR flash
   One microSD Card slot

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC3: Connected to Atheros AR8035 GETH PHY

UART:
   Two UARTs are routed to the FDTI dual USB to RS232 convertor

USB: Two USB2.0 Type A ports

I2C:
   AT24C01B 1K Board EEPROM (8 bit address)

QUICC Engine:
   Connected to DP83849i PHY supply two 10/100M ethernet ports
   QE UART for RS485 or RS232

PCIE:
   One mini-PCIE slot

Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
[yorksun: Fixup include/configs/p1_twr.h]
Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:25 -07:00
Stefano Babic
326ea986ac Merge git://git.denx.de/u-boot-arm
Conflicts:
	board/freescale/mx6qsabrelite/Makefile
	board/freescale/mx6qsabrelite/mx6qsabrelite.c
	include/configs/mx6qsabrelite.h

Signed-off-by: Stefano Babic <sbabic@denx.de>
2013-07-31 11:30:38 +02:00
Pardeep Kumar Singla
58cc978777 mx6qsabresd: Add splash screen support via HDMI
Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
2013-07-27 10:49:45 +02:00
Fabio Estevam
f8b1e86d47 mx6qsabrelite: Remove mx6qsabrelite code in favor of nitrogen6x
mx6qsabrelite and nitrogen6q boards are hardware compatible, so let's avoid the
code duplication and only use the nitrogen6x source code to make board code
maintainance easier.

Tested booting a mainline device tree kernel on a mx6qsabrelite board.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-07-26 16:44:29 +02:00
Tom Rini
c2120fbfbc Merge branch 'master' of git://git.denx.de/u-boot-i2c
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.

Conflicts:
	board/sandburst/common/ppc440gx_i2c.c
	board/sandburst/common/ppc440gx_i2c.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:50:24 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Alison Wang
1221b3d74a vf610: Add I2C support for Vybrid VF610 platform
This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.

Signed-off-by: Alison Wang <b18965@freescale.com>
2013-07-23 08:34:57 +02:00
Heiko Schocher
00f792e0df i2c, fsl_i2c: switch to new multibus/multiadapter support
- added to fsl_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
2013-07-23 08:34:53 +02:00
Heiko Schocher
ea818dbbcd i2c, soft-i2c: switch to new multibus/multiadapter support
- added to soft_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
2013-07-23 05:54:29 +02:00
Wolfgang Denk
f4ea9f86d1 PPC MPC83xx: Fix MPC8323ERDB build warning
Fix:

mpc8323erdb.c: In function 'mac_read_from_eeprom':
mpc8323erdb.c:198:3: warning: dereferencing type-punned pointer will
break strict-aliasing rules [-Wstrict-aliasing]

Signed-off-by: Wolfgang Denk <wd@denx.de>
cc: Timur Tabi <timur@tabi.org>
cc: Kim Phillips <kim.phillips@freescale.com>
2013-07-15 18:03:15 -04:00
Tom Rini
fbbbc86e8e Merge branch 'master' of git://git.denx.de/u-boot-arm
Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.

Conflicts:
	arch/arm/dts/exynos5250.dtsi

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-12 10:36:48 -04:00
Albert ARIBAUD
e6c7f86f03 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-06-28 17:51:13 +02:00
Fabio Estevam
17f3f36652 mx28evk: Move README file inside board directory
Board specific READMEs should be located inside the respective board directory.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-06-26 17:40:39 +02:00
Pierre Aubert
c174797061 imx: Add support for the SabreSD shipped with i.MX6DL
The SabreSD platform is available with i.MX6Q or i.MX6DL. This patch adds the
support of the i.MX6DL. The config file and the board directory are renamed
to remove the reference to the MX6Q.

Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-06-26 17:34:11 +02:00
Tom Rini
348e47f766 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-06-22 07:38:12 -04:00
Albert ARIBAUD
47bd65ef05 arm: make __rel_dyn_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain relocation symbols yet remain
unchanged.

__rel_dyn_start and __rel_dyn_end each requires
its own output section; putting them in relocation
sections changes their flags and breaks relocation.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:29 +02:00
Albert ARIBAUD
d026dec875 arm: make __image_copy_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain __image_copy_{start,end} yet
remain unchanged.

Also, __image_copy_end needs its own section; putting
it in relocation sections changes their flags and makes
relocation break.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:05:05 +02:00
Albert ARIBAUD
09d81184e1 remove all references to .dynsym
Discard all .dynsym sections from linker scripts
Remove all __dynsym_start definitions from linker scripts
Remove all __dynsym_start references from the codebase

Note: this touches include/asm-generic/sections.h, which
is not ARM-specific, but actual uses of __dynsym_start
are only in ARM, so this patch can safely go through
the ARM repository.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-21 23:04:05 +02:00
Chunhe Lan
5707233880 powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (Fixed DDR on board)
   64MB NOR flash
   128MB NAND flash

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC2: Connected to Atheros AR8035 GETH PHY

PCIe:
   Three mini-PCIe slots

USB:
   Two USB2.0 Type A ports

I2C:
   AT24C08 8K Board EEPROM (8 bit address)

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:53 -05:00
York Sun
5bdeff3214 powerpc/pixis: Fix pixis help message
"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:52 -05:00
Prabhakar Kushwaha
505c293ffd board/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI define
PCIe TLB should be created with CONFIG_PCI defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:50 -05:00
Liu Gang
69fdf90010 powerpc/t4qds: Slave module for boot from SRIO and PCIE
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:49 -05:00
Liu Gang
5870fe44b2 powerpc/b4860qds: Slave module for boot from SRIO and PCIE
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
	1. Set all the cores in holdoff status.
	2. Set the boot location to one PCIE or SRIO interface by RCW.
	3. Set a specific TLB entry for the boot process.
	4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	5. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	6. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	7. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:48 -05:00
Prabhakar Kushwaha
f64bd7c038 powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL
e500v2 processor does not support 8K page size TLB entries.

So create new TLB entry only during NAND SPL boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 17:08:47 -05:00
Andy Fleming
8bd00c9494 85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT
All the other constants use lowercase 'x' in "MPC85xx", so we
duplicate that here.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:09 -05:00
Priyanka Jain
1d2949aeb3 board/bsc9131rdb: Update default boot environment settings
BSC9131RDB has 1GB DDR.
Out of this, only 880MB is passed on to Linux via bootm_size.
Remaining
-16MB is reserved for PowerPC-DSP shared control area
-128MB is reserved for DSP private area.

Also 256MB, out of this 880MB is required for data communication between
PowerPC and DSP core.
For this bootargs are modified to pass parameter to create 1 hugetlb
page of 256MB via default_hugepagesz, hugepagesz and hugepages

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:08 -05:00
Priyanka Jain
765b0bdb89 board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:08 -05:00
Priyanka Jain
087cf44fcd board/bsc9131rdb: Add targets for Sysclk 100MHz
BSC9131RDB supports Sysclk
-66MHz if jumper J16 is close (default state)
-100MHz if jumper J16 is open

Add targets
-BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz
-BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot at Sysclk 100MHz

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:08 -05:00
Prabhakar Kushwaha
83e0c2bbe3 board/bsc9132qds:Add NAND boot support using new SPL format
- Add NAND boot target
   - defines constants
   - Add spl_minimal.c to initialise DDR
   - update TLB, LAW entries as per NAND boot

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:08 -05:00
Prabhakar Kushwaha
f159326926 board/bsc9131rdb:Add NAND boot support using new SPL format
- Add NAND boot target
   - defines constants
   - Add spl_minimal.c to initialise DDR
   - update TLB entries as per NAND boot

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:07 -05:00
Prabhakar Kushwaha
0fa934d235 board/p1010rdb:Add NAND boot support using new SPL format
- defines constants
  - Add spl_minimal.c to initialise DDR
  - update TLB entries as per NAND boot
  - remove nand_spl support for P1010RDB

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:09:07 -05:00
Prabhakar Kushwaha
3a88179d03 powerpc/mpc85xx: new SPL support for IFC NAND
Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds

common/Makefile: Avoid compiling unnecssary files

fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
NAND flash and copying into DDR. It also transfer control from NAND SPL
to u-boot image present in DDR.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-20 16:08:58 -05:00
Albert ARIBAUD
10e167329b Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/serial/Makefile
2013-06-08 14:35:10 +02:00
Fabio Estevam
4a1c7b13ae vf610twr: Drop unneeded 'status' variable
No need to use the 'status' variable, so just remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
2013-06-06 17:52:08 +02:00
Andrew Gabbasov
0c54f4b7c8 mx6: mx6qsabrelite/nitrogen6x: Remove incorrect setting of gpio CS signal
The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.

Also, SPI driver sets the direction and initial value of a gpio,
used as a chip select signal, before any actual activity happens
on the bus.

So, it is safe to just remove the gpio_direction_output call,
that works incorrectly, thus making no effect, anyway.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Tested-by: Robert Winkler <robert.winkler@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2013-06-03 13:25:46 +02:00
Renato Frias
a1f67807ff mx6qsabreauto: Add Port Expander reset
There are 3 IO expanders on the mx6qsabreauto all reset by the
same GPIO, just set it to high to use the IO.

Signed-off-by: Renato Frias <b13784@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-06-03 13:19:41 +02:00
Renato Frias
195781657c mx6qsabreauto: Add i2c to mx6qsabreauto board
Add i2c2 and 3 to mx6qsabreauto board, i2c3 is multiplexed
use gpio to set steering.

Signed-off-by: Renato Frias <b13784@freescale.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-06-03 13:19:11 +02:00
Alison Wang
8c653124a3 arm: vf610: Add basic support for Vybrid VF610TWR board
VF610TWR is a board based on Vybrid VF610 SoC.

This patch adds basic support for Vybrid VF610TWR board.

Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-06-03 10:56:54 +02:00
Albert ARIBAUD
3acb324ff1 mx31pdk: copy SPL directly, not using relocate_code.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
2013-05-30 20:23:08 +02:00
Albert ARIBAUD
a19b0dd62d Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
2013-05-30 14:45:06 +02:00
Shaveta Leekha
6eaeba23dd powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Shaohui Xie
e14cdc0a69 powerpc/p5040: fix mdio mux for 10G port
Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in
eth port enum structure, it will assign mdio mux depend on this assumption.
This is not true with Fman V3, which added more 1G ports after port DTSEC5
in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux.
So we use dynamic index for 10G ports instead of hardcoded enum value
when doing mdio mux for 10G ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Shaohui Xie
f9539a9caa powerpc/p2041: fix serdes reference clock frequency display for PC board
PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:13 -05:00
Shaveta Leekha
0fecbba80a powerpc/b4860: fix for Serdes connectivity to SFP's
Crossbar switches were wrongly programmed to
route the CPRI lanes to SFP as the connectivity table
was not correct.
Modified it correctly for SFPs connections.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:13 -05:00
Shengzhou Liu
037e19b812 powerpc/t4240qds: fix PHY reset timeout issue
QSGMII card has different PHY address against previous SGMII card.
We check the type of card in slots and set correct PHY address to
avoid complainning "PHY reset timed out" during u-boot booting up.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:13 -05:00
York Sun
e1379b0730 powerpc/t4qds: Add SW7[4] in the DIP switch display
SW7[4] is the new bit which controls the mapping of eMMC vs SDHC.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:13 -05:00
Suresh Gupta
16d88f415a Enable XAUI interface for B4860QDS
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
	The PHY addresses of Teranetics PHY on XAUI riser card are assigned
	based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
	AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:12 -05:00
Stephen George
49e946cb6a board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
Debug trace buffers are memory mapped in DCSR space beyond 4M.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:12 -05:00
Shaohui Xie
94025b1cd8 powerpc/p5040: enable PBL tool support
Provided a default RCW for P5040, then it can use PBL to build
ramboot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:12 -05:00
Ed Swarthout
f41388159a powerpc/t4qds: use clock measurement for sysclk and ddr clock
Use QIXIS measurement registers to obtain sysclk and ddr clock. This
allows using non-standard clock speeds, set by directly writing to
clock chip or store the values in qixis clock data eeprom.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:12 -05:00
Ed Swarthout
428ea86c64 powerpc/qixis: add clock measurement registers
QIXIS includes frequency measurement functions for each major processor
clock input. After reset (and after clocks are stable), QIXIS measures
the clocks against a reference frequency and stores the results in
CLK_FREQ registers. A base register supplies a multiplier which allows
directly obtaining the measured value, without requiring knowledge of
the target system or QIXIS core frequency.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:11 -05:00
Shaohui Xie
c79fd50382 T4240/ramboot: enable PBL tool for T4240
Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use
PBL tool to produce the ramboot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:10 -05:00
York Sun
0aadf4aa51 powerpc/t4240qds: Add VDD override
Allow VDD voltage overriding with a command. This is an add-on feasture of
VID. To override VDD, use command vdd_override with the value of voltage
in mV, for example

vdd_override <voltage in mV, eg. 1050>

The above example will set the VDD to 1.050 volt. Any wrong value out of
range of 0.8188 to 1.2125 volt or invalid string is ignored.

In addition to the command, if overriding VDD is needed earlier in booting
process, save an variable and reboot:

setenv t4240qds_vdd_mv <voltage in mV>
saveenv

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:10 -05:00
York Sun
9cefbd64b2 powerpc/t4240qds: Add board detail for bdinfo command
Print more detail information including core voltage, RCW source, switch
settings, etc. with bdinfo command.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:09 -05:00
Fabio Estevam
eadfc135d3 mx23evk: Add splash screen support
Enable display support.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-16 17:44:46 +02:00
Fabio Estevam
68661db2dc mx28evk: Add splash screen support
Enable display support.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-16 17:44:46 +02:00
Shaohui Xie
f63d638dad T4240/eth: fix SGMII card PHY address
QSGMII card assumed to be used by default, but if SGMII card is used,
it will use different PHY address, but we don't know which card is used
until we access PHY on the card. So we check the card type slot by slot,
if we can read a PHY ID by reading a SGMII PHY address on a slot, then
the slot must have a SGMII card pluged, we mark all ports on that slot,
and fix dts to use the SGMII card PHY address when doing dts fixup
for the marked ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:25 -05:00
Ed Swarthout
9c0a6de21d powerpc/t4qds: Fix disabling remote I2C connection
Only clear IRE bit in qixis brdcfg5 register and keep other bits
unchanged.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:25 -05:00
York Sun
431047955b powerpc/b4860qds: Assign DDR address in board file
B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
This is the requirement for DSP cores to run in 32-bit address space.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:25 -05:00
Shaohui Xie
04bccc3ab0 T4240/net: use QSGMII card PHY address by default
Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:25 -05:00
Shengzhou Liu
959278083d t4240qds/eth: fixup ethernet for t4240qds
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
   slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:24 -05:00
York Sun
97c7fe61b8 powerpc/t4240qds: Add voltage ID support
T4240 has voltage ID fuse. Read the fuse and configure the voltage
correctly. Core voltage has higher tolerance on over side than below.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:28 -05:00
York Sun
054dfd9b9d powerpc/t4240qds: Update DDR timing table
Update the timing table to support more rank density, based on the theory
that similar density DIMMs have similar clock adjust and write level start
timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:27 -05:00
Roy Zang
9458f6d83a T4/serdes: fix the serdes clock frequency
Reverse the bit sequence to set and display serdes clock frequency
correctly. The correct bit maps in BRDCFG2 are
0	1	2	3	4	5	6	7
S1RATE[1:0]	S2RATE[1:0] 	S3RATE[1:0] 	S4RATE[1:0]

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:25 -05:00
Albert ARIBAUD
ec7023db8d Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
	drivers/mtd/nand/mxc_nand_spl.c
	include/configs/m28evk.h
2013-05-11 09:25:36 +02:00
Anatolij Gustschin
b1e6c4c3d4 Fix references to the documentation files
Many boot image configuration files refer to the
appropriate documentation file, but these references
contain typos in the directory and file name. Fix
them. Also fix reference to doc/README.SPL file.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-05-10 08:16:33 -04:00
Benoît Thébaudeau
68088ceed7 imx: mx35pdk: Fix MUX2_CTR GPIO
MUX2_CTR is on GPIO1[5], not GPIO2[5], and it needs to be set high in order to
connect the FEC.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-06 15:21:59 +02:00
Fabio Estevam
3d11444c42 mx23evk: Do not set voltage selection bit for SSP pads
mx23 SSP pad registers do not contain voltage selection bit, so just remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-06 09:55:51 +02:00
Benoît Thébaudeau
544544a060 imx: mx53smd: Convert to iomux-v3
There is no change of behavior.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:05 +02:00
Benoît Thébaudeau
721d0b0026 imx: mx53loco: Convert to iomux-v3
There is no change of behavior.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:05 +02:00
Benoît Thébaudeau
58f0764658 imx: mx53evk: Convert to iomux-v3
There is no change of behavior.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:05 +02:00
Benoît Thébaudeau
5053b59300 imx: mx53ard: Convert to iomux-v3
There is no change of behavior.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:05 +02:00
Benoît Thébaudeau
4d15d36c08 imx: mx51evk: Convert to iomux-v3
There is no change of behavior, except for older silicon revisions for which
support is removed.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:04 +02:00
Benoît Thébaudeau
105c9eaf9b imx: mx35pdk: Convert to iomux-v3
There is no change of behavior.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:03 +02:00
Benoît Thébaudeau
0f6829e111 imx: mx35pdk: Fix WDOG_RST iomux function
The signal connected from this pin to the PMIC is WDOG_B, i.e. ALT0 mode, not
ALT1 (which even corresponds to nothing).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:03 +02:00
Benoît Thébaudeau
1b1c526751 imx: mx25pdk: Fix GPIO assignments
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:03 +02:00
Benoît Thébaudeau
d6208a3cf9 imx: mx25pdk: Convert to iomux-v3
There is no change of behavior, even if some pad control values could probably
be simplified.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-05-05 17:55:03 +02:00
Fabio Estevam
0ede8272d0 mx23evk: Fix DDR pin iomux settings
Change MUX_CONFIG_EMI to use the same drive strength as the bootlets code from
Freescale, which results in much better stability.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05 17:08:46 +02:00
Xu Jiucheng
545c12cf9a powerpc/p1_p2_rdb_pc: Add a pin to reset the DDR chip for P1021RDB-PC
When P1021RDB-PC reboot system, the board will hung at uboot DDR
configuration. For P1021RDB-PC DDR reset pin is multiplex with
QE, so uboot will reserve this pin for QE and skip DDR reset.
Other platforms without QE will do this reset. This patch adds
a slight code to reset DDR chip by QE CE_PB8 pin for NAND and
NOR FLASH boot. For booting from SPI FALSH and SD card, it
seems possible to use the rom on chip to write to the GPIO
pins before configuring the DDR.

Signed-off-by: Xu Jiucheng <B37781@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:57:34 -05:00
Shengzhou Liu
f68a730538 powerpc/p1010rdb: Change flexcan compatible string
Change flexcan compatible string from "fsl,flexcan-v1.0"
to "fsl,p1010-flexcan" to match the device tree.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:57:33 -05:00
Zhicheng Fan
7d83b79c2b qoriq/p1_p2_rdb_pc: USB device-tree fixups for P1020
Resolve P1020 second USB controller multiplexing with eLBC
         - mandatory to mention USB2 in hwconfig string to select it
           over eLBC, otherwise USB2 node is removed
         - works only for SPI and SD boot

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Zhicheng Fan <B32736@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:45 -05:00
Liu Gang
57966101c8 powerpc/b4860qds: Add the tlb entries for SRIO interfaces
Add the tlb entries based on the configuration of the SRIO interfaces.
Every SRIO interface has 256M space:

	#define CONFIG_SYS_SRIO1_MEM_VIRT   0xa0000000
	#define CONFIG_SYS_SRIO1_MEM_PHYS   0xc20000000ull

	#define CONFIG_SYS_SRIO2_MEM_VIRT   0xb0000000
	#define CONFIG_SYS_SRIO2_MEM_PHYS   0xc30000000ull

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:44 -05:00
Matthew McClintock
f45210d6e7 powerpc/p1022ds: Add support for NAND and NAND boot using SPL
Add defines needed to access NAND, remove second flash bank that is
actually connected to NAND.

Add nand booting support for P1022DS with hardcoded DDR config using
SPL framework from 2011

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:43 -05:00
Jiang Bin
acac075b94 board/freescale/common/cds_pci_ft.c: Fix rotate wrong cells in interrupt-map property
For linux 3.x, the size of each item in interrupt-map property is 9 not 7.
Don't use the static value and calculate the size with following cells:
	PCI #address-cells, PCI #interrupt-cells,
	PIC address, PIC #address-cells, PIC #interrupt-cells.

Signed-off-by: Bin Jiang <bin.jiang@windriver.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:56:42 -05:00
Michael Heimpold
d196bd8803 env_mmc: add support for redundant environment
This patch add support for storing the environment redundant on
mmc devices. Substantially it re-uses the logic from the NAND implementation,
that means using an incremental counter for marking newer data.

Signed-off-by: Michael Heimpold <mhei@heimpold.de>
2013-05-01 16:41:10 -04:00
Benoît Thébaudeau
7e2173cf82 imx: iomux-v3: Include PKE and PUE to pad control pull definitions
PUE requires PKE to mean something, as do pull values with PUE, so do not
compell users to explicitly use PKE and PUE everywhere. This is also what is
done on Linux and what has already been done for i.MX51.

By the way, remove some unused pad control definitions.

There is no change of behavior.

Note that SPI_PAD_CTRL was defined by several boards with a pull value, but
without PKE or PUE, which means that no pull was actually enabled in the pad.
This might be a bug in those boards, but this patch does not change the
behavior, so it just removes the meaningless pull value from those definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-28 11:15:07 +02:00
Benoît Thébaudeau
8f3ff11c1f imx: Homogenize and fix fuse register definitions
IIM:
 - Homogenize prg_p naming (the reference manuals are not always self-consistent
   for that).
 - Add missing SCSx and bank registers.
 - Fix the number of banks on i.MX53.

OCOTP:
 - Rename iim to ocotp in order to avoid confusion.
 - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the
   reference manual.
 - Merge the existing spinoff gp1 fuse definition on i.MX6.
 - Fix the number of banks on i.MX6.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-28 11:07:40 +02:00
Fabio Estevam
1155d555d6 mx53ard: Move register masks into imx-regs.h
imx-regs.h is more appropriate location for containing register masks.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2013-04-25 21:48:21 +02:00
Otavio Salvador
f07e286c7c mx6qsabresd: Return status when initializing MMC
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-04-25 21:32:45 +02:00
Fabio Estevam
7a56f1791d imx: mx6q_4x_mt41j128.cfg: Setup CCM_CCOSR register
Setup CCM_CCOSR register to provide a CKO1 clock frequency of 16.5 MHz.

CKO1 drives sgtl5000 codec clock on mx6qsabrelite and doing this setup in the
bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c
from the mainline kernel.

mx6q_4x_mt41j128.cfg is also used by mx6qsabresd, and it is safe to use it for
this board as well.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-25 21:14:19 +02:00
Stefan Roese
b29ca4a158 imx: Add titanium board support (i.MX6 based)
Titanium is a i.MX6 based board from ProjectionDesign / Barco. This
patch adds support for this board with the newly introduced NAND
support for i.MX6.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 10:26:40 +02:00
Fabio Estevam
57ca432fb9 mx6sl: Add initial support for mx6slevk board
mx6slevk board is a development board from Freescale based on the mx6 solo-lite
processor.

For details about mx6slevk, please refer to:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX6SLEVK&parentCode=i.MX6SL&fpsp=1

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-22 09:58:19 +02:00
Albert ARIBAUD
f84a7b8f54 ARM: Fix __bss_start and __bss_end in linker scripts
Commit 3ebd1cbc introduced compiler-generated __bss_start
and __bss_end__ and commit c23561e7 rewrote all __bss_end__
as __bss_end. Their merge caused silent and harmless but
potentially bug-inducing clashes between compiler- and linker-
generated __bss_end symbols.

Make __bss_end and __bss_start compiler-only, and create
__bss_base and __bss_limit for linker-only use.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-13 22:37:20 +02:00
Benoît Thébaudeau
1a9a91dcfa arm: Make all linker scripts compatible with per-symbol sections
Let all ARM linker scripts handle properly -ffunction-sections
and -fdata-sections. This will be useful for future changes in order to create
symbol-specific sections in common .S files.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:09 +02:00
Benoît Thébaudeau
5c6db120fc arm: Remove unused relocate_code() parameters
Commit e05e5de7fa made the 2 1st parameters of
ARM's relocate_code() useless since it moved the code handling them to crt0.S.
So, drop these parameters.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
da962b7175 nand: mxc: Switch NAND SPL to generic SPL
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fa.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12 07:55:07 +02:00
Benoît Thébaudeau
68fbc0e686 imx: mx53ard: Add support for NAND Flash
Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB
pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard.

eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this
board, which satisfies the 30-ns NF R/W cycle requirement.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-12 07:55:04 +02:00
Albert ARIBAUD
be08abc242 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-04-04 11:49:32 +02:00
Javier Martinez Canillas
7a3f481c6d i.MX6: mx6qsabrelite: README: don't pass chip-select to sf probe command
board/freescale/mx6qsabrelite/README explain a procedure to
update the SPI-NOR on the SabreLite board without Freescale
manufacturing tool but following this procedure leads to both
"sf erase" and "sf write" failing on a mx6qsabrelite board:

MX6QSABRELITE U-Boot > sf probe 1
MX6QSABRELITE U-Boot > sf erase 0 0x40000
SPI flash erase failed
MX6QSABRELITE U-Boot > sf write 0x10800000 0 0x40000
SPI flash write failed

This is because the chip-select 1 is wrong and the correct
value is 0x7300.

Since commit c1173bd0 ("sf command: allow default bus and chip selects")
the chip-select and bus arguments for the sf probe command are optional
so let's just remove it and use "sf probe" instead.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
2013-04-03 12:15:17 +02:00
Fabio Estevam
38e7007725 mx6: Fix get_board_rev() for the mx6 solo case
When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev()
returns 0x62xxx, which is not a value understood by the VPU
(Video Processing Unit) library in the kernel and causes the video playback to
fail.

The expected values for get_board_rev are:
0x63xxx: For mx6quad/dual
0x61xxx: For mx6dual-lite/solo

So adjust get_board_rev() accordingly and make it as weak function, so that we
do not need to define it in every mx6 board file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-04-03 11:36:34 +02:00
Abbas Raza
aad4659a2f mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board
Maximum bus width supported by some i.MX6 boards is not 8bit like
others. In case where both host controller and card support 8bit transfers,
they agree to communicate on 8bit interface while some boards support only 4bit interface.
Due to this reason the mmc 8bit default mode fails on these boards. To rectify this,
define maximum bus width supported by these boards (4bit). If max_bus_width is not
defined, it is 0 by default and 8bit width support will be enabled in host
capabilities otherwise host capabilities are modified accordingly.

It is tested with a MMCplus card.

Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com>
cc: stefano Babic <sbabic@denx.de>
cc: Andy Fleming <afleming@gmail.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2013-04-03 11:26:28 +02:00
Fabio Estevam
55600288ab mx6qsabrelite: README: No need to pass 'u-boot.imx'
The u-boot.imx binary is generated by default, so no need to pass it in the
'make' line.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-04-03 10:57:42 +02:00
Otavio Salvador
85449dbd4b mx6qsabre{sd,auto}: Add boot mode select
Adds support for 'bmode' command which let user to choose where to
boot from; this allows U-Boot to load system from another storage
without messing with jumpers.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-04-03 10:41:51 +02:00
Otavio Salvador
60bb462148 mx6qsabresd: Fix card detection for invalid card id case
This changes the code so in case an unkown value is passed it will
return as invalid.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-04-03 10:41:28 +02:00
Otavio Salvador
28ff917c28 mx6qsabresd: Document the mapping of USDHC[2-4]
This documents the SD card identifier so it is easier for user to spot
which card number will be used, if need.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-04-03 10:40:13 +02:00
Tom Rini
0ce033d258 Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-18 14:37:18 -04:00
Simon Glass
3929fb0a14 Replace __bss_end__ with __bss_end
Note this is a tree-wide change affecting multiple architectures.

At present we use __bss_start, but mostly __bss_end__. This seems
inconsistent and in a number of places __bss_end is used instead.

Change to use __bss_end for the BSS end symbol throughout U-Boot. This
makes it possible to use the asm-generic/sections.h file on all
archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:54 -04:00
Albert ARIBAUD
6579d15c58 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2013-03-15 15:18:31 +01:00
Albert ARIBAUD
ef123c5253 Refactor linker-generated arrays
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.

Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.

Conflicts:
	arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
	arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
	arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
	board/ait/cam_enc_4xx/u-boot-spl.lds
	board/davinci/da8xxevm/u-boot-spl-da850evm.lds
	board/davinci/da8xxevm/u-boot-spl-hawk.lds
	board/vpac270/u-boot-spl.lds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:40 +01:00
Albert ARIBAUD
3ebd1cbc49 arm: make __bss_start and __bss_end__ compiler-generated
Turn __bss_start and __bss_end__ from linker-generated
to compiler-generated symbols, causing relocations for
these symbols to change type, from R_ARM_ABS32 to
R_ARM_RELATIVE.

This should have no functional impact, as it affects
references to __bss_start and __bss_end__ only before
relocation, and no such references are done.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:32 +01:00
Anatolij Gustschin
e5f538649c mpc512x: use common code for clock setting for all mpc512x boards
Only define enabled clocks in the config file and enable
the clocks in common code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Wolfgang Denk <wd@denx.de>
2013-03-09 08:22:23 +01:00
Anatolij Gustschin
676c66918a mpc512x: use common code for CSx configuration
Remove CSx configurations from board code and only define
required CSx macros in the board config file to configure
chip select windows and parameters.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Cc: Wolfgang Denk <wd@denx.de>
2013-03-09 08:21:46 +01:00
Fabio Estevam
1b097cff51 mx6: Provide a structure for accessing HDMI registers
Provide a structure for accessing HDMI registers, so that we can use proper
read/write accessors.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 18:03:44 +01:00
Otavio Salvador
920178d381 mx23evk: Adjust DRAM control register to use full 128MB of RAM
Adjust HW_DRAM_CTL14 to enable the chip selects to allow usage of full
128MB of RAM.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-03-07 17:22:57 +01:00
Eric Nelson
cfb8b9d335 i.MX6: consolidate pad names for multi-CPU boards
Rename all i.MX6 pad declarations to MX6_PAD_x, so a board
may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo
(MX6DL) by including the proper header.

Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd
only support MX6Q, so they include mx6q_pins.h.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 16:43:46 +01:00
Eric Nelson
74cf809972 i.MX6: mx6qsabrelite: indent with tabs
This patch has no functional changes and simply replaces
leading spaces with tabs.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 16:43:46 +01:00
Stefano Babic
9cd9b34dc7 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-02-23 10:13:40 +01:00
Tom Rini
951c6baaf4 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-02-12 10:18:31 -05:00
Benoît Thébaudeau
7c92c54075 imx: mx6q DDR3 init: Benefit from available CL = 7
All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK
hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to
DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it.

In these conditions:
  tRCD(min) = 13.125 ns
  tRP(min) = 13.125 ns
  tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min)
  tRAS(min, DDR3-1333H) = 36 ns
  tRAS(min, DDR3-1600K) = 35 ns

MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG0[3:0].

MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded
as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18].

MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG1[2:0].

MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[31:29].

MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[28:26].

MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded
as 0x1A in the bit-field MMDC1_MDCFG1[25:21].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12 13:52:31 +01:00
Benoît Thébaudeau
b42b5b7a24 imx: mx6q DDR3 init: Fix MR0.PPD
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12 13:52:31 +01:00
Benoît Thébaudeau
1791b1f97f imx: mx6q DDR3 init: Fix RST_to_CKE
MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded
as 0x23 for the bit-field MMDC1_MDOR[5:0].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12 13:52:31 +01:00
Benoît Thébaudeau
ada02b8463 imx: mx6q DDR3 init: Fix SDE_to_RST
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded
as 0x10 for the bit-field MMDC1_MDOR[13:8].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12 13:52:30 +01:00
Benoît Thébaudeau
aa53149e11 imx: mx6q DDR3 init: Fix tXPR
MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR.

For all DDR3 speed bins:
  tXPR(min) = max(5 nCK, tRFC(min) + 10 ns)
  tRFC(2 Gb) = 160 ns

All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron
MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD).

Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns
and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12 13:52:30 +01:00
Benoît Thébaudeau
6904e37746 imx: mx6q DDR3 init: Fix tMRD
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.

For all DDR3 speed bins:
  tMRD(min) = 4 nCK
  tMOD(min) = max(12 nCK, 15 ns)

Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK
at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-02-12 13:52:30 +01:00
Simon Glass
67ac13b1b9 ppc: Move lbc_clk and cpu to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-04 09:04:57 -05:00
Prabhakar Kushwaha
960aa89bda board/common: Add support for QIXIS read/write using i2c
QIXIS FPGA is accessable via both i2c and flash controller.
Only flash controller access is supported.

Add support of i2c based access. It is quite useful in the scenario
where either flash controller path is broken or not present.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:15 -06:00
Prabhakar Kushwaha
41d910118c powerpc/85xx: Add BSC9132QDS support
BSC9132QDS is a Freescale reference design board for BSC9132 SoC.
BSC9132 SOC is an integrated device that targets the evolving Microcell,
Picocell, and Enterprise-Femto base station market subsegments.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.

BSC9132QDS Overview
 --------------------
  2Gbyte DDR3 (on board DDR), Dual Ranki
  32Mbyte 16bit NOR flash
  128Mbyte 2K page size NAND Flash
  256 Kbit M24256 I2C EEPROM
  128 Mbit SPI Flash memory
  SD slot
  USB-ULPI
  eTSEC1: Connected to SGMII PHY
  eTSEC2: Connected to SGMII PHY
  PCIe
  CPRI
  SerDes
  I2C RTC
  DUART interface: supports one UARTs up to 115200 bps for console display

Apart from the above it also consists various peripherals to support DSP
functionalities.

This patch adds support for mainly Power side functionalities and peripherals

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00
Valentin Longchamp
c4d580797d powerpc/p2041: add RCW file for P2041RDB
All the dev boards of Freescale's QorIQ family have a RCW that is
supported by the u-boot.pbl build target. This patch adds one for the
P2041 dev board.

This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the
P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:12 -06:00
Prabhakar Kushwaha
afa2b72b08 powerpc/t4240qds: Print FPGA detail version
Qixis FPGA has tag data contains image name and build date.
It is helpful to identify the FPGA image precisely.

Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:12 -06:00
Shaveta Leekha
4457e3e678 powerpc/t4240qds: Add support to dump switch settings on t4240qds board
This function is called by "qixis_reset switch" command and
switch settings are calculated from qixis FPGA registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:11 -06:00
Shaveta Leekha
4354889b9b powerpc/b4860qds: Add support to dump switch settings on b4860qds board
This function is called by "qixis_reset switch" command
and switch settings are calculated from FPGA/qixis registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:11 -06:00
Shaveta Leekha
c6cef92f63 powerpc/qixis: enable qixis dump command and add switch dumping command
Remove #ifdef so that "qixis dump" command is always available

Add "qixis_reset switch" command to dump switch settings
Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from
registers to figure out switch settings. Not all bits are available.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:11 -06:00
York Sun
b5b06fb7b0 powerpc/b4860qds: Added Support for B4860QDS
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.

B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
  ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,  ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
  16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
  8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
  RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
  connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
  connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
  configuration reset source. The RCW source is set by appropriate
  DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
	- On-board eCWTAP controller with ETH and USB I/F
	- JTAG/COP 16-pin header for any external TAP controller
	- External JTAG source over AMC to support B2B configuration
	- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
	- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
  DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
  - total four refclk, including CPRI clock scheme

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:11 -06:00
Prabhakar Kushwaha
2ae4e8d958 board/freescale/common:Add support of QTAG register
QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE
fields. These fields have FPGA build version, image name and build date
information.

Add support to parse these fields to have complete FPGA image information.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:10 -06:00
Prabhakar Kushwaha
ac13eb5de0 board/T4240qds:Fix TLB and LAW size of NAND flash
The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.

So Update TLB and LAW size of NAND flash accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:09 -06:00
Timur Tabi
de757a7af0 powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.c
Static variables should be defined in C files, not header files, because
otherwise every C file that #includes the header file will generate a
duplicate of the variables.  Since the vsc3316_xxx[] arrays are only
used by t4qds.c anyway, just put the variables there.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:08 -06:00
Shaohui Xie
220d506af3 powerpc/p2041: move Lanes mux to board early init
Lanes mux currently is configured in eth.c when initializing FMAN ethernet
ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to
p2041rdb.c which implements a board-specific initialization and will be
called at early stage.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:08 -06:00
Otavio Salvador
81ca840976 mx23evk: Add initial board support
The following features are supported:
 * 128 MB DDR1 SDRAM
 * DUART
 * SD/MMC Card Socket

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-28 11:51:04 +01:00
Marek Vasut
90bc2bf297 mxs: mmc: Allow overriding default card detect implementation
Some MXS based boards do not implement the card-detect signal. Allow
user to specify alternate card-detect implementation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-28 11:43:01 +01:00
Troy Kisky
3236921968 mx6qsabrelite: search mii phy address 4-7
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-28 06:57:51 +01:00
Troy Kisky
71a988aa63 imximage.cfg: run files through C preprocessor
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.

The mkimage command which uses this preprocessor output
was moved to arch/arm/imx-common/Makefile

.gitignore was updated to ignore .cfgtmp files.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2013-01-22 10:20:13 +01:00
Otavio Salvador
bf48fcb61b mxs: clock: Use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2013-01-21 12:05:20 +01:00
Kim Phillips
a6187dccd8 Merge remote-tracking branch 'mpc83xx/next' 2013-01-16 18:34:09 -06:00
Fabio Estevam
11d80af487 mx51evk: Add DVI output support
Add DVI output support and make it the default video output.

Currently the CLAA WVGA panel is supported, but this panel has to be purchased
separately, so using the DVI output as the default would allow more people to
try the splash screen feature on a mx51evk.

If someone still wants to use the CLAA WVGA, just set the panel variable as:
set panel claa

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-13 12:06:35 +01:00
Troy Kisky
abbab70363 mx31/mx35/mx51/mx53/mx6: add watchdog
Use a common watchdog driver for all these cpus.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-01-13 11:39:57 +01:00
Fabio Estevam
17c5ef2007 mx53loco: Add support for SEIKO 4.3'' WVGA panel
Add support for the Seiko 4.3'' WVGA panel on mx53loco.

By default, the CLAA WVGA panel is selected.

In order to support the Seiko panel, the enviroment variable 'panel' must be
set to 'seiko'.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-09 19:22:24 +01:00
Fabio Estevam
085e728aa5 mx53loco: Improve error handling on power_init()
Make the error handling more robust.

Check if each one of the PMIC writes fail and if they do, just return
immediately.

Also, print the cause for the failures.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-05 18:07:53 +01:00
Fabio Estevam
d22925108e mx53loco: Remove unneeded 'retval' variable
commit c73368150 (pmic: Extend PMIC framework to support multiple instances
of PMIC devices) introduced an extra 'retval' variable, but this is not
necessary since we have already the variable 'ret' in place.

So use 'ret' to store the return values from the pmic related calls and remove
'retval'.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-01-05 18:06:12 +01:00
Shawn Guo
de7d02aeba mx6qsabresd: add usdhc2 and usdhc4 support
The on-board number of available usdhc devices is something board
specific.  The patch moves CONFIG_SYS_FSL_USDHC_NUM out of
mx6qsabre_common.h and adds usdhc2 and usdhc4 support for mx6qsabresd
board.

To keep the default mmc device for environment same as before (usdhc3),
it moves CONFIG_SYS_MMC_ENV_DEV out of mx6qsabre_common.h and changes
it to 1 for mx6qsabresd.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-01-05 18:00:14 +01:00
Ashok
e660c44d9e mx35pdk:Use IMX_GPIO_NR macro
Use IMX_GPO_NR macro

Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-01-05 17:44:41 +01:00
Fabio Estevam
54bb84115d mx53loco: Call PMIC related functions from board_late_init()
Since commit c733681 (pmic: Extend PMIC framework to support multiple instances
of PMIC devices) mx53loco fails to allocate the memory for PMIC:

U-Boot 2013.01-rc2-dirty (Dec 20 2012 - 15:55:01)

Board: MX53 LOCO
I2C:   ready
DRAM:  1 GiB
pmic_alloc: No available memory for allocation!
pmic_init: POWER allocation error!
CPU:   Freescale i.MX53 family rev2.0 at 800 MHz
Reset cause: POR
MMC:   FSL_SDHC: 0, FSL_SDHC: 1

Calling the PMIC related functions at a later stage, ie, from board_late_init()
fixes the issue.

Reported-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
2012-12-27 11:03:43 +01:00
Scott Wood
22f4442d12 powerpc/mpc83xx: convert MPC8313ERDB to new-SPL
This converts MPC8313ERDB NAND boot to use the new SPL infrastructure.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-12-19 17:45:54 -06:00
Fabio Estevam
8965112bbf mx53loco: Fix PMIC name
commit c73368150 (pmic: Extend PMIC framework to support multiple instances
of PMIC devices) has incorrectly passed the PMIC name under the FSL PMIC case.

Fix that by passing "FSL_PMIC" as the parameter of pmic_get.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-12-13 09:22:55 +01:00
Fabio Estevam
cabe240b59 mx25pdk: Adapt it for the new PMIC framework
Make the necessary adaptions for the new PMIC framework, so that mx25pdk can
be built again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-12-11 17:41:19 +01:00
Stefano Babic
05a860c228 Merge branch 'master' of git://git.denx.de/u-boot into master
Conflicts:
	drivers/power/power_fsl.c
	include/configs/mx35pdk.h
	include/configs/mx53loco.h
	include/configs/woodburn_common.h
	board/woodburn/woodburn.c

These boards still use the old old PMIC framework, so they
do not merge properly after the power framework was merged into
mainline.

Fix all conflicts and update woodburn to use Power Framework.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-12-08 12:02:45 +01:00
York Sun
765ad3cf4d powerpc/corenet_ds: Update DDR timing for single-rank DIMMs
Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
d31e53b42c powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Andy Fleming
e76cd5d4cf 8xxx: Change all 8*xx_DDR addresses to 8xxx
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-27 17:45:17 -06:00
Scott Wood
13d1143ffb powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data.  The SPL itself cannot use SPD due
to code size constraints.  It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with.  It's possible that different revisions of the board
require different settings.  Using SPD eliminates that problem.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:27 -06:00
Scott Wood
d674bccf73 powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map
- Sort by address, and fix column alignment

- Don't label things as localbus that aren't.  Instead, put chipselect
  info at the end of the description for localbus windows.  Note that
  NAND/NOR have their chipselects swapped when booting from NAND, and CS2
  can be either PMC or VSC7385 depending on hwconfig.

- Shrink NAND to the 32K that's actually mapped in the localbus

- Assign an address and size to L2 SRAM.  Remove the similarly named
  but unintelligible "L2 SDRAM(REV.)".

- Remove the untrue comment about L1 stack being mapped with TLB0.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:26 -06:00
Scott Wood
94a45bb197 powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support
Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
2012-11-26 15:41:25 -06:00
Tom Rini
178d0cc1a4 Merge branch 'master' of git://git.denx.de/u-boot-video 2012-11-19 09:28:04 -07:00
Benoît Thébaudeau
961a762838 mx35pdk: Add support for OTG
Add support for the OTG port on the mx35pdk Personality board.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
2012-11-16 09:16:45 +01:00
Vikram Narayanan
30ea4be921 mx53loco: Fix build error when CONFIG_VIDEO is disabled
The inclusion of LCD patch into mx53loco breaks the build when
CONFIG_VIDEO is disabled. Fix this by splitting the video
related stuff to a new file.

Also rename the function lcd_iomux to setup_iomux_lcd to make the
namings aligned with the other iomux functions.

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-14 14:05:51 +01:00
Vikram Narayanan
5d71bd210f mx51evk: Fix build error when CONFIG_VIDEO is disabled
The inclusion of LCD patch into mx51evk breaks the build when
CONFIG_VIDEO is disabled. Fix this by splitting the video related
stuff to a new file.

Also rename the function lcd_iomux to setup_iomux_lcd to make the
namings aligned with the other iomux functions.

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-14 14:05:35 +01:00
Łukasz Majewski
c733681507 pmic: Extend PMIC framework to support multiple instances of PMIC devices
The PMIC framework has been extended to support multiple instances of
the variety of devices responsible for power management.
This change allows supporting of e.g. fuel gauge, charger, MUIC (Micro USB
Interface Circuit).
Power related includes have been moved to ./include/power directory.
This is a first of a series of patches - in the future "pmic" will be
replaced with "power".

Two important issues:
1. The PMIC needs to be initialized just after malloc is configured
2. It uses list to hold information about available PMIC devices

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-11-14 11:21:09 +01:00
Stefano Babic
3e4d27b06d Merge git://git.denx.de/u-boot 2012-11-10 08:05:54 +01:00
Tom Rini
6acc7c3cbc Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-11-05 07:42:00 -07:00
Kim Phillips
a2873bde4c powerpc/mpc83xx: sparse fixes
fdt.c:91:78: warning: Using plain integer as NULL pointer
fdt.c:103:78: warning: Using plain integer as NULL pointer
speed.c:55:11: warning: symbol 'corecnf_tab' was not declared. Should it be static?
speed.c:519:5: warning: symbol 'do_clocks' was not declared. Should it be static?
mpc8313erdb.c:73:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:74:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:75:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:76:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:79:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:80:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:81:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:82:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:85:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:86:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:87:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:88:17: warning: obsolete struct initializer, use C99 syntax

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:37 -07:00
Kim Phillips
e56143e54f powerpc/mpc85xx: sparse fixes
fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static?
cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static?
bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart'
bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write'
bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write'
bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio'
bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write'
bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write'
bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec'
bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect'
ngpixis.c:245:1: error: directive in argument list
ngpixis.c:247:1: error: directive in argument list

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-04 11:00:36 -07:00
Jason Jin
f9a2d79337 ColdFire: Update the lds file for M54418TWR board.
The M54418TWR lds file  need to update since commit:

8b493a5236

common: Discard the __u_boot_cmd section

The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2012-10-29 22:08:09 +08:00
Albert ARIBAUD
f04821a8ca Merge remote-tracking branch 'u-boot-imx/master' 2012-10-27 11:43:17 +02:00
Fabio Estevam
e00c89df06 mx25pdk: Add Ethernet support
mx25pdk has a Ethernet port that is connected to its internal FEC controller.

In order to power up the Ethernet PHY (DP83640) it is necessary to communicate
with the MC34704 PMIC via I2C.

Make the FEC ethernet port functional

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-26 16:28:08 +02:00
Fabio Estevam
af2a4093cb mx25pdk: Add esdhc support
mx25pdk has a SD/MMC slot connected to esdhc1.

Add support for it and allow the environment variables to be saved into SD/MMC.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-26 16:28:07 +02:00
Stefano Babic
b736e4b929 ARM: Fix start.S when used with SPL in arm1136
This patch modifies start.S for the arm1136 to make it
conform to start.S  in armv7 architecture, to make it
usable if the SPL framework is used.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-10-26 16:27:58 +02:00
Alison Wang
186fc4db26 ColdFire: Add Freescale MCF54418TWR ColdFire development board support
Add Freescale MCF54418TWR ColdFire development board support.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-10-24 22:27:46 +08:00
Tom Rini
c7656bab41 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx 2012-10-22 16:54:38 -07:00
York Sun
ee52b188ca powerpc/t4qds: Add T4QDS board
The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.

SERDES Connections
  32 lanes grouped into four 8-lane banks
  Two “front side” banks dedicated to Ethernet
  Two “back side” banks dedicated to other protocols
DDR Controllers
  Three independant 64-bit DDR3 controllers
  Supports rates up to 2133 MHz data-rate
  Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
QIXIS System Logic FPGA

Each DDR controller has two DIMM slots. The first slot of each controller
has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
The second slot has only 2 chip selects to support single- and dual-rank
DIMMs. At any given time, up to total 4 chip selects can be used.

Detail information can be found in doc/README.t4qds

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 15:52:46 -05:00
Shaveta Leekha
aa42cb71fa board/freescale/common: VSC3316/VSC3308 initialization code
Add code for configuring VSC3316/3308 crosspoint switches
Add README to understand the APIs

   - VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch
     capable of data rates upto 11.5Gbps. VSC3316 has 16 input and 16
     output ports whereas VSC3308 has 8 input and 8 output ports.
     Programming of these devices are performed by two-wire or four-wire
     serial interface.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:21 -05:00
Shengzhou Liu
e4de13e38a powerpc/board: add present2 register definition for QIXIS
According to new QIXIS system definition, update QIXIS registers set
to add present2 register instead of obsolete ctl_sys2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:14 -05:00
Marek Vasut
8b493a5236 common: Discard the __u_boot_cmd section
The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-22 08:29:42 -07:00
Marek Vasut
556751427b common: Add .u_boot_list into all linker files
Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adjustment.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
2012-10-22 08:29:42 -07:00
Prabhakar Kushwaha
9f26fd7947 board/freescale/common:QIXIS:Fix magic number usage
QIXIS FPGA layout defines the  address of registers but The actual register bit
implementation is board-specific,

So avoid use of magic numbers as it may vary across different boards's QIXIS
FPGA implementation.
Also, Avoid board specific defines in common/qixis.h

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 03:04:28 -05:00
Jason Jin
87c9b18687 ColdFire: Fix the build error for Freescale m5282evb board.
Clean up the lds file and fix the environment build error.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2012-10-19 23:52:09 +08:00
Eric Nelson
e58010b554 i.MX6: mx6qsabrelite: Add splash screen support
Adds support for HDMI, two LVDS panels and one RGB panel to
the SABRE-Lite board.

Displays supported:
         HDMI		- 1024 x 768 for maximum compatibility
         Hannstar-XGA   - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
         wsvga-lvds     - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
         wvga-rgb       - 800 x 480 RGB (Boundary p/n Nit6X_800x480)

Since the ipuv3_fb display driver currently supports only a single display,
this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
or the I2C touch controller of the LVDS and RGB displays in the priority
listed above.

Setting 'panel' environment variable to one of the names above will
override auto-detection.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-16 12:35:12 +02:00
Eric Nelson
08fd6a3580 i.MX: ipufb: add const to fb_videomode declarations
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-16 12:35:11 +02:00
Eric Nelson
6e14232010 i.MX: declare iomux_v3_cfg_t arrays as const
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-16 12:35:11 +02:00
Fabio Estevam
dce67bd548 mx6qsabreauto: Pass the board revision to the kernel
The kernel from Freescale expects that the bootloader passes the board revision.

Read the board revision and pass it via get_board_rev().

Without passing the board revision the kernel does not operate properly as the
initialization of peripherals are different in revA versus revB boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-16 12:35:11 +02:00
Benoît Thébaudeau
a2ac1b3a7d mxc: Fix SDHC multi-instance clock
On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not
suitable for the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).

This patch fixes this issue by adding a configuration field for the SDHC input
clock frequency.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Andy Fleming <afleming@gmail.com>
2012-10-16 12:35:10 +02:00
Benoît Thébaudeau
151d63cb91 mx35: Clean up lowlevel_init
Clean up mx35 lowlevel_init:
 - Indent with tabs.
 - Fix comments.
 - Use defined values instead of literal constants.
 - Use defined macros instead of duplicating code.
 - Use macro parameters with default values instead of #define'd configs.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-16 12:35:10 +02:00
Fabio Estevam
fe5ebe97fa mx6qsabreauto: Add Ethernet support
mx6qsabreauto has a AR8031 Gigabit PHY.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:14 -07:00
Benoît Thébaudeau
9e0081d573 mx31: Fix PDR0_CSI_PODF
The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0
register is actually composed of two bit-fields: one pre-divider and one
post-divider. This patch fixes the CCM access macros and the code using them
accordingly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:14 -07:00
Benoît Thébaudeau
833b6435de mx5/6: Define default SoC input clock frequencies
Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:10 -07:00
Fabio Estevam
7dd6545da7 mx6q: Add basic support for mx6qsabreauto
mx6qsabreauto is a board based on mx6q SoC with the following features:
- 2GB of DDR3
- 2 USB ports
- 1 HDMI output port
- SPI NOR
- 2 LVDS LCD ports
- Gigabit Ethernet
- Camera
- eMMC and SD card slot
- Multichannel Audio
- CAN
- SATA
- NAND
- PCIE
- Video Input

Add very basic support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:09 -07:00
Fabio Estevam
e72d617860 mx6qsabresd: Add 8-bit USDHC support
USDHC3 has 8 pins wired in mx6qsabresd. Configure the extra pins.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:08 -07:00
Fabio Estevam
a0d21fc01a mx6qsabresd: Add Ethernet support
mx6qsabresd has a AR8031 Gigabit PHY.

Add support for it.

Also increase CONFIG_SYS_MALLOC_LEN so that FEC buffer allocation does not fail.

Tested on 1Gbp and 100Mbps networks.

Suggested-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-15 11:54:08 -07:00
Fabio Estevam
7891e258d4 mx6: Add basic support for mx6qsabresd board.
mx6qsabresd is a board based on mx6q SoC with the following features:
- 1GB of DDR3
- 1 USB OTG port
- 1 HDMI output port
- SPI NOR
- LVDS panel
- Gigabit Ethernet
- Camera Connector
- eMMC and SD card slot
- Audio

Add very basic support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:08 -07:00
Fabio Estevam
af7ec0b058 mx6q: Factor out common DDR3 init code
Factor out common DDR3 initialization code, allowing easier maintainance of such
scripts.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-10-15 11:54:08 -07:00
Albert ARIBAUD
1c27059a2f Merge remote-tracking branch 'u-boot/master' 2012-09-30 23:49:17 +02:00
Tom Rini
5675b50916 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2012-09-25 12:23:55 -07:00
Fabio Estevam
5436eaeab9 mx28evk: Remove fecmxc_mii_postcall()
fecmxc_mii_postcall() is specific to the KSZ9021 PHY on m28evk and
should not be used on mx28evk, which has LAN8270 instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-24 10:45:41 +02:00
Benoît Thébaudeau
362635bd50 mx51evk: Add CONFIG_REVISION_TAG
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG
information.

If this data is not present, the kernel misconfigures the TZIC, which results in
the timer interrupt handler never being called, so the kernel deadlocks while
calibrating its delay.

Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-23 19:55:06 +02:00
Tom Rini
495dbd72dd Merge branch 'master' of git://git.denx.de/u-boot-arm 2012-09-21 14:53:13 -07:00
Alison Wang
198cafbf2c ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
a4110eecf2 ColdFire: Clean up checkpatch warnings for MCF547x and MCF548x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
c6d8863015 ColdFire: Clean up checkpatch warnings for MCF523x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
aa0d99fc28 ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:27 +08:00
Alison Wang
32dbaafa5a ColdFire: Clean up checkpatch warnings for MCF52x2
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:26 +08:00
Alison Wang
849fc42471 ColdFire: Clean up checkpatch warnings for MCF5227x
Signed-off-by: Alison Wang <b18965@freescale.com>
2012-09-20 20:39:26 +08:00
Ira W. Snyder
db1fc7d28e mpc8308rdb: add support for eSDHC MMC controller
Add support for the onboard eSDHC MMC controller. The hardware on the
MPC8308RDB has the following errata:

- ESDHC111: manual asynchronous CMD12 is broken
- DMA is broken (PIO works)

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>

[added include fsl_esdhc header to prevent implicit declarations of
fsl_esdhc_mmc_init() and fdt_fixup_esdhc()]

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-09-18 16:16:45 -05:00
Ira W. Snyder
ea1ea54e35 mpc8308rdb: add support for Spansion SPI flash on header J8
The SPI pins are routed to header J8 for testing SPI functionality. A
Spansion flash has been wired up and tested on this header.

This patch breaks support for the second TSEC interface, since the GPIO
pin used as a chip select is pinmuxed with some of the TSEC pins.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-09-18 16:16:44 -05:00
Fabio Estevam
1d9b033269 mx35pdk: README: Remove NAND references
Booting from NAND is currently not supported, so remove its references.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-17 13:17:17 +02:00
Stefano Babic
3292539e7d MX35: mx35pdk: add support for MMC
Add support for SD card and change the default
environment due to increased u-boot size.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-09-10 14:32:47 +02:00
Ashok Kumar Reddy
5d20881eec mx6qsabrelite:Use IMX_GPIO_NR Macro
Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
2012-09-10 14:25:38 +02:00
Fabio Estevam
ddfcc810d3 mx28evk: Convert to mxs_adjust_memory_params()
Recent conversion from mx28_adjust_memory_params to mxs_adjust_memory_params
missed to update mx28evk, which caused the board not to boot.

Apply the conversion so that the board can boot again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-04 11:57:56 +02:00
Otavio Salvador
4f434e3d6d MX28: mx28evk: Align SSP clock speed
Align the SSP clock speed with oscilator to achieve higher transfer
stability.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
2012-09-04 11:57:56 +02:00
Benoît Thébaudeau
16e43f354d fsl_esdhc: Remove cache snooping for i.MX
The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so
disable it globally for this architecture. This avoids setting no_snoop for all
i.MX boards, and it prevents setting a reserved bit of a reserved register if
fsl_esdhc_mmc_init() is used on i.MX, like in
arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init().

Since no_snoop was only used on i.MX, get rid of it BTW.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
2012-09-01 14:58:30 +02:00
Ashok Kumar Reddy
925507088b mx5:Use IMX_GPIO_NR macro
Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
2012-09-01 14:58:30 +02:00
Ashok Kumar Reddy
acbdea2ece mx6qarm2:Use IMX_GPIO_NR macro
Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:29 +02:00
Otavio Salvador
72f8ebf17e mxs: Rename 'mx28_dram_init' to 'mxs_dram_init'
The DRAM initialization, after SPL has complete, is exactly the same
for all mxs SoCs so we should name it accordinly.

The following boards has been changed:

 * apx4devkit
 * m28evk
 * mx28evk
 * sc_sps_1

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
2012-09-01 14:58:28 +02:00
Fabio Estevam
5c8d14dfd9 mx53ard: Use IMX_GPIO_NR macro
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:28 +02:00
Fabio Estevam
5179a26848 mx51evk: Use IMX_GPIO_NR macro
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:28 +02:00
Fabio Estevam
3ef0a312c0 mx53loco: Use IMX_GPIO_NR macro
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:28 +02:00
Stefano Babic
5fecb36ca0 MX: Set a common gpio.h for all i.MX
Each i.MX has its own gpio.h, defining the same structure.
The internal GPIO controller has the same layout
(at least for the register used by u-boot) and can be shared.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Tested-by: Matt Sealey <matt@genesi-usa.com>
2012-09-01 14:58:27 +02:00
Troy Kisky
0aff384b14 mx53evk: add boot_mode support
This allows a watchdog reset to start the ROM's
usb/serial downloader, or boot from an sdcard.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-09-01 14:58:26 +02:00
Troy Kisky
bb05b40b06 mx6qsabrelite: add boot_mode support
This allows a watchdog reset to start the ROM's
usb downloader, or boot from an sdcard.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-09-01 14:58:26 +02:00
Troy Kisky
d1c679a46d iomux: move IOMUX_GPR13_xxx defines
Move mx6 specific defines to arch-mx6 directory.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Benoît Thébaudeau
34a31bf52b mx35: Fix typo on EDIO
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:26 +02:00
Marek Vasut
7fb1ed0eab MX28: Move the u-boot.bd info CPUDIR/SOCDIR
This gets us rid of duplication of the same file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01 14:58:18 +02:00
Fabio Estevam
1e080988d0 mx51evk: do not overwrite the console
On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:18 +02:00
Stefano Babic
3e0773708d MX5: mx53loco: do not overwrite the console
On this board, the console is always set to the serial line.
Do not allow to overwrite it when video is enabled.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01 14:58:18 +02:00
Otavio Salvador
1e0cf5c34b mxs: Reowork SPL to use 'mxs' prefix for methods
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Otavio Salvador
9c471142bc mxs: prefix register structs with 'mxs' prefix
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01 14:58:17 +02:00
Scott Wood
d69dba367a powerpc/mpc85xx/p1_p2_rdb: add all LAWs during SPL
LAW init is skipped in the SPL payload because it's assumed that the SPL
has taken care of it -- so make sure the SPL loads all the LAWs as is
done on other boards.

This bug was introduced by:

  commit 4589728e21
  Author: Kumar Gala <galak@kernel.crashing.org>
  Date:   Fri Nov 11 08:14:53 2011 -0600

    powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND

    Size grew a bit so nand-spl didn't fit in 4k, reduce done by removing
    LAW entries not needed during SPL phase.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-08-23 12:49:48 -05:00
Timur Tabi
055ce08004 powerpc/85xx: remove support for the Freescale P3060
The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 12:16:53 -05:00
Timur Tabi
61fc52b660 powerpc/85xx: get rid of enum board_slots in P4080 MDIO driver
enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on.  This is pointless, so remove it.  Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:19 -05:00
Timur Tabi
45b092d301 powerpc/85xx: introduce function serdes_device_from_fm_port()
In order to figure out which SerDes lane a given Fman port is connected
to, we need a function that maps the fm_port namespace to the srds_prtcl
namespace.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:18 -05:00
Paul Gortmaker
a2af6a7a84 mpc85xx: use LCRR_DBYP define instead of raw constant
Using the raw value of 0x80000000 directly in the code can
lead to "count the zeros" bugs like that fixed in commit
718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for
66-133MHz LBC")

Change all existing raw values to use the symbolic value of
LCRR_DBYP instead.

Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:18 -05:00
Matthew McClintock
c8f9802a72 p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit)
There was an extra 0 in front of the value we were using to mask,
remove it to improve the code.

Also fix the value written to ddr_sdram_cfg to set the bus width
properly to 16 bits

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
Shaohui Xie
5d898a00f3 powerpc/CoreNet: add tool to support pbl image build.
Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
Liu Gang
461632bd71 powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.

NOTE: Because the slave can not erase, write master's NOR flash by
	  PCIE interface, so it can not modify the ENV parameters stored
	  in master's NOR flash using "saveenv" or other commands.

environment and requirement:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image is in master NOR flash.
	3. Put the slave's ucode and ENV into it's own memory space.
	4. Normally boot from local NOR flash.
	5. Configure PCIE system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to one PCIE interface by RCW.
	3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the slave module, need to finish these processes:
	1. Set the boot location to one PCIE interface by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID of one PCIE for the boot.
	4. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	5. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	6. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
	1. Updated the README.srio-boot-corenet to add descriptions about
	   boot from PCIE, and change the name to
	   README.srio-pcie-boot-corenet.
	2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
	   "xxxx_SRIO_PCIE_BOOT", and the image builded with
	   "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
	   from PCIE.
	3. Updated other macros and documents if needed to add information
	   about boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:15 -05:00
Liu Gang
81fa73bab0 powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:14 -05:00
Hongtao Jia
308bc61db7 powerpc/sgmii: To support PHY link state auto detect in SGMII mode
PHYs on SGMII riser card are used in SGMII mode with different external
IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type
under ethernet node should be updated. Otherwise the PHY interrupt can not
be handled therefor PHY link state change can not be auto detected.

For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed
but it's still be kept to guarantee the sgmii mode could work with old
device tree.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 18:32:15 -05:00
Shaohui Xie
145dbc0250 powerpc/p2041: configure the CPLD lane_mux according to RCW
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
is 0xc, CPLD supports SATA by default, we should re-configure the lane
muxing according to RCW, which indicates what SerDes protocol it is running.

Default lane muxing map is as below:
Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
and bit 3 respectively.

Default value of these bits for lane muxing is '1', we should set or clear
these bits accoring to RCW.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:39 -05:00
Timur Tabi
7a946961c7 powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
In order for indirect mode on the PIXIS to work properly, both chip selects
need to be set to GPCM mode, otherwise writes to the chip select base
addresses will not actually post to the local bus -- they'll go to the
NAND controller instead.  Therefore, we need to set BR0 and BR1 to GPCM
mode before switching to indirect mode.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:37 -05:00
Matthew McClintock
af2536088e powerpc/p1022ds: add support for SPI and SD boot
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.

Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.

Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-08 17:13:37 -05:00
Troy Kisky
9c06782863 mx6qsabrelite: add i2c multi-bus support
This includes bus recovery support.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-07-31 08:01:09 +02:00
Troy Kisky
af2a35fb1f i.mx: iomux-v3.h: move to imx-common include directory
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-07-31 08:00:19 +02:00
Wolfgang Denk
b98b611502 Merge branch 'next' of git://git.denx.de/u-boot
* 'next' of git://git.denx.de/u-boot:
  MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
  doc: cleanup - move board READMEs into respective board directories
  net: sh_eth: add support for SH7757's GETHER
  net: sh_eth: modify the definitions of regsiter
  net: sh_eth: add SH_ETH_TYPE_ condition
  net: sh_eth: clean up for the SH7757's code
  net: fec_mxc: Fix MDC for xMII
  net: fec_mxc: Fix setting of RCR for xMII
  net: nfs: make NFS_TIMEOUT configurable
  net: Inline the new eth_setenv_enetaddr_by_index function
  net: allow setting env enetaddr from net device setting
  net/designware: Consecutive writes to the same register to be avoided
  CACHE: net: asix: Fix asix driver to work with data cache on
  net: phy: micrel: make ksz9021 phy accessible
  net: abort network initialization if the PHY driver fails
  phylib: phy_startup() should return an error code on failure
  net: tftp: fix type of block arg to store_block

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-30 20:39:52 +02:00
Wolfgang Denk
702e6014f1 doc: cleanup - move board READMEs into respective board directories
Also drop a few files referring to no longer / not yet supported
boards.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Jason Jin <jason.jin@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-07-29 15:42:02 +02:00
Wolfgang Denk
00c60f9131 Minor Coding Style Cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-22 21:58:26 +02:00
Fabio Estevam
175a7d2778 mx28evk: Add I2C support
Add I2C support.

Tested by placing a 24LC16 EEPROM into the U50 slot which comes empty from factory.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-11 10:54:53 +02:00
Troy Kisky
3174689be2 mx6qsabrelite: add i2c support
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-07-11 10:54:52 +02:00
Wolfgang Denk
3fe63839f3 Minor Coding Style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-10 09:18:33 +02:00
Wolfgang Denk
50cd93b250 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
  ARM: cache: Move the cp15 CR register read before flushing the cache.
  ARM: introduce arch_early_init_r()
  PXA: Enable CONFIG_PREBOOT on zipitz2
  ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
  No need to define CONFIG_ARCH_CPU_INIT.
  add new board vl_ma2sc
  MTD: SPEAr SMI: Add write support for length < 4 bytes
  i2c: designware_i2c.c: Add support for the "i2c probe" command
  rtc/m41t62: Add support for M41T82 with HT (Halt Update)
  SPL: ARM: spear: Add SPL support for SPEAr600 platform
  Makefile: Add u-boot.spr build target (SPEAr)
  SPL: ARM: spear: Remove some objects from SPL build
  SPL: lib/Makefile: Add crc32.c to SPL build
  SPL: common/Makefile: Add image.c to SPL build
  arm: Don't use printf() in SPL builds
  GPIO: Add SPEAr GPIO driver
  net: Multiple updates/enhancements to designware.c
  cleanup/SPEAr: Define configuration flags more elegantly
  cleanup/SPEAr: Remove unnecessary parenthesis
  SPEAr: Correct SoC ID offset in misc configuration space
  SPEAr: explicitly select clk src for UART
  SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
  SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
  SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
  SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
  SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
  SPEAr: Enable dcache for fast file transfer
  SPEAr: Enable autoneg for ethernet
  SPEAr: Enable udc and usb-console support only for usbtty configuration
  SPEAr: Enable usb device high speed support
  SPEAr: Initialize SNOR in early_board_init_f
  SPEAr: Change the default environment variables
  SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
  SPEAr: Add configuration options for spear3xx and spear6xx boards
  SPEAr: Add basic arch related support for SPEAr SoCs
  SPEAr: Add interface information in initialization
  SPEAr: Add macb driver support for spear310 and spear320
  SPEAr: Configure network support for spear SoCs
  SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
  SPEAr: Eliminate dependency on Xloader table
  SPEAr: Fix ARM relocation support
  st_smi: Fixed page size for Winbond W25Q128FV flash
  st_smi: Change timeout loop implementation
  st_smi: Fix bug in flash_print_info()
  st_smi: Change the flash probing method
  st_smi: Removed no needed dependency on ST_M25Pxx_ID
  st_smi: Fix smi read status
  st_smi: Move status register read before modifying ctrl register
  st_smi: Read status until timeout happens
  st_smi: Enhance the error handling
  st_smi: Change SMI timeout values
  st_smi: Return error in case TFF is not set
  st_smi: Add support for SPEAr SMI driver
  mtd/NAND: Remove obsolete SPEAr specific NAND drivers
  SPEAr: Configure FSMC driver for NAND interface
  mtd/NAND: Add FSMC driver support
  arm/km: remove calls to kw_gpio_* in board_early_init_f
  arm/km: add implementation for read_dip_switch
  arm/km: support the 2 PCIe fpga resets
  arm/km: skip FPGA config when already configured
  arm/km: redefine piggy 4 reg names to avoid conflicts
  arm/km: cleanup km_kirkwood boards
  arm/km: enable BOCO2 FPGA download support
  arm/km: remove portl2.h and use km_kirkwood instead
  arm/km: convert mgcoge3un target to km_kirkwood
  arm/km: add kmcoge5un board support
  arm/km: add kmnusa board support
  arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
  cm-t35: fix incorrect NAND_ECC layout selection
  ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
  ARM: OMAP4/5: Move USB pads to essential list.
  ARM: OMAP4/5: Move USB clocks to essential group.
  ARM: OMAP4/5: Move gpmc clocks to essential group.
  ARM: OMAP4+: Move external phy initialisations to arch specific place.
  omap4: Use a smaller M,N couple for IVA DPLL
  da850/omap-l138: Enable auto negotiation in RMII mode
  omap: am33xx: accomodate input clocks other than 24 Mhz
  omap: emif: fix bug in manufacturer code test
  omap: emif: deal with rams that return duplicate mr data on all byte lanes
  OMAP4+: Force DDR in self-refresh after warm reset
  OMAP4+: Handle sdram init after warm reset
  ARM: OMAP3+: Detect reset type
  arm: bugfix: Move vector table before jumping relocated code
  Kirkwood: Add support for Ka-Ro TK71
  arm/km: use spi claim bus to switch between SPI and NAND
  arm/kirkwood: protect the ENV_SPI #defines
  ARM: don't probe PHY address for LaCie boards
  lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
  lacie_kw: fix SDRAM banks number for net2big_v2
  Kirkwood: add lschlv2 and lsxhl board support
  net: add helper to generate random mac address
  net: use common rand()/srand() functions
  lib: add rand() function
  kwboot: boot kirkwood SoCs over a serial link
  kw_spi: add weak functions board_spi_claim/release_bus
  kw_spi: support spi_claim/release_bus functions
  kw_spi: backup and reset the MPP of the chosen CS pin
  kirkwood: fix calls to kirkwood_mpp_conf
  kirkwood: add save functionality kirkwood_mpp_conf function
  km_arm: use filesize for erase in update command
  arm/km: enable mii cmd
  arm/km: remove CONFIG_RESET_PHY_R
  arm/km: change maintainer for mgcoge3un
  arm/km: fix wrong comment in SDRAM config for mgcoge3un
  arm/km: use ARRAY_SIZE macro
  arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
  arm/km: add piggy mac adress offset for mgcoge3un
  arm/km: add board type to boards.cfg
  AT91SAM9*: Change kernel address in dataflash to match u-boot's size
  ATMEL/PIO: Enable new feature of PIO on Atmel device
  ehci-atmel: fix compiler warning
  AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
  Atmel : usb : add EHCI driver for Atmel SoC
  Fix: AT91SAM9263 nor flash usage
  Fix: broken boot message at serial line on AT91SAM9263-EK board
  i.MX6 USDHC: Use the ESDHC clock
  mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
  i.MX28: Add function to adjust memory parameters
  mx28evk: Fix PSWITCH key position
  mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
  mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
  imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove unused CONFIG_MII_GASKET
  mx6: Avoid writing to read-only bits in imximage.cfg
  m28evk: use same notation to alloc the 128kB stack
  ...

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-07-08 19:26:33 +02:00
Fabio Estevam
f69b0653ac mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
commit acc4959fc1 (Revert "i.MX28: Enable additional DRAM address bits")
broke mx28evk boot.

Fix it by properly adjusting the HW_DRAM_CTL29 register value.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:29 +02:00
Vikram Narayanan
b29da17494 mx6: Avoid writing to read-only bits in imximage.cfg
If in case this is valid according to the latest datasheet, ignore this patch.
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:27 +02:00
Fabio Estevam
001533eb0e mx6qsabrelite: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-07-07 14:07:27 +02:00
Fabio Estevam
ef0ed6a48d mx6qarm2: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-07-07 14:07:27 +02:00
Fabio Estevam
cf0a8ec227 mx51evk: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:26 +02:00
Fabio Estevam
d0004a687c mx53smd: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:26 +02:00
Fabio Estevam
5094fbf79b mx53ard: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:26 +02:00
Fabio Estevam
b4896cd618 mx53evk: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:26 +02:00
Fabio Estevam
2fb563f2f5 mx53loco: Remove unused SOBJS
There is no .S file in this directory, so just remove SOBJS.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-07-07 14:07:26 +02:00
Fabio Estevam
eae08eb2b5 mx53loco: Fix revision of Dialog boards
Original code was assuming that the fuse revision version for all mx53loco boards
based on Dialog PMIC was the same, which is not the case.

Force the revision of all Dialog-based boards to 0.

This fixes a kernel crash when PMIC is accessed in the 2.6.35 kernel
for Dialog rev E boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-07 14:07:25 +02:00
York Sun
48f6a5c348 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun <yorksun@freescale.com>
2012-07-06 17:30:33 -05:00
Timur Tabi
1fc0d59486 powerpc/85xx: fdt_set_phy_handle() should return an error code
fdt_set_phy_handle() makes several FDT calls that could fail, so it should
not be hiding these errors.

Signed-off-by: Timur Tabi <timur@freescale.com>
2012-07-06 17:30:32 -05:00
Shengzhou Liu
d3de823e54 powerpc/p1010rdb: add readme document for p1010rdb
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2012-07-06 17:30:31 -05:00
Shengzhou Liu
487e8abbaa powerpc/p1010rdb: update mux config of p1010rdb board
On p1010rdb some signals are muxed for tdm/can/uart/flash.
If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" explicitly,
defaultly we keep spi chip selection to spi-flash instead of to
tdm/slic and disable uart1 when not using flexcan, as well disable sdhc.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2012-07-06 17:30:29 -05:00
Prabhakar Kushwaha
7530d341c7 powerpc/mpc85xx:Add BSC9131 RDB Support
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC
 is an integrated device that targets Femto base station market. It combines
 Power Architecture e500v2 and DSP StarCore SC3850 core technologies with
 MAPLE-B2F baseband acceleration processing elements

  BSC9131RDB Overview
   -----------------
     -1Gbyte DDR3 (on board DDR)
     -128Mbyte 2K page size NAND Flash
     -256 Kbit M24256 I2C EEPROM
     -128 Mbit SPI Flash memory
     -USB-ULPI
     -eTSEC1: Connected to RGMII PHY
     -eTSEC2: Connected to RGMII PHY
     -DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.

This patch adds support for mainly Power side functionalities and peripherals

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-07-06 17:30:29 -05:00
ramneek mehresh
3d7506fa38 powerpc/85xx: Add USB device-tree fixup for various platforms
Add USB device-tree fixup for following platforms:
MPC8536DS, P1022DS, P1023RDS, P2020COME, P2020DS, P2041RDB, P3060QDS

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2012-07-06 17:03:25 -05:00
Fabio Estevam
f714b0a911 mx53loco: Add LCD support
Add support for CLAA07LC0ACW LCD that connects to the mx53loco board.

Configure the board to show the Linux logo on the LCD.

Also increase the size of CONFIG_SYS_MALLOC_LEN variable to take into account
the framebuffer usage.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-05-25 10:40:32 +02:00
Fabio Estevam
a1b0e190a3 mx5: Rename mx51_fb_init()
The ipuv3 driver is currently only used on mx51, but it can be extended to work
on mx53 and mx6 as well.

Rename mx51_fb_init(), so that it can be used by other SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-05-25 10:39:23 +02:00
Fabio Estevam
f1adefd239 mx51evk: Add LCD support
Add support for CLAA07LC0ACW LCD that connects to the mx51evk board.

Configure the board to show the Linux logo on the LCD.

Also increase the size of CONFIG_SYS_MALLOC_LEN variable to take into account
the framebuffer usage.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-25 10:06:38 +02:00
Fabio Estevam
6ecaee8201 mx53loco: Remove unneeded gpio_set_value()
There is no need to set the VBUS power enable to 0 first and then to 1.

Set it to 1 in the gpio_direction_output() function.

While at it, use the standard naming convention for the GPIO comment.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-05-15 08:31:34 +02:00
Fabio Estevam
54cd1dee8f mx53loco: Add CONFIG_REVISION_TAG
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.

The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
and also to distinguish between revA and revB of the mc34708 based boards.

Suggested-by: Yu Li <yk@magniel.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Fabio Estevam
768a059710 mx53loco: Turn on VUSB regulator
On the mx53loco board with mc34708 PMIC it is necessary to turn on VUSB regulator
so that the mx53 USBH1 PHY receives the 3.3V voltage.

Tested by inserting a USB pen drive in the upper USB slot (USBH1) and then issued the
commands:

usb start

usb info

,which correctly detected and printed the USB pen drive information.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Fabio Estevam
5b547f3c20 mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
Add mc34708 support and set mx53 core frequency at its maximum value of 1GHz.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Fabio Estevam
ed5157e889 pmic: dialog: Avoid name conflicts
As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC,
we need to be able to build both drivers.

Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:34 +02:00
Eric Nelson
3996a96c5e i.MX6: mx6q_sabrelite: add SATA bindings
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: stefano Babic <sbabic@denx.de>
2012-05-15 08:31:33 +02:00
Lauri Hintsala
ecb7be2985 mx28evk: add NAND support
NAND support is not enabled by default because Eval Kit is not delivered
with NAND chip. To enable NAND support add CONFIG_CMD_NAND to board config.

Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Acked-by: Marek Vasut <marex@denx.de>
2012-05-15 08:31:33 +02:00
Fabio Estevam
e7e337227b mx53loco: Add support for 1GHz operation for DA9053-based boards
There are two types of mx53loco boards: initial boards were built with a Dialog
DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC.

Add DA9053 PMIC support and adjust the required voltages and clocks for running
the CPU at 1GHz.

Tested on both versions of mx53loco boards.

In the case of a MC34708-based board the CPU operating voltage remains at 800MHz.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by : Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:32 +02:00
Fabio Estevam
1fc56f1cb0 mx53loco: Allow to print CPU information at a later stage
Print CPU information within board_late_init().

This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:32 +02:00
Eric Nelson
28fdbddc94 i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
Uses the 'magic_keys' idiom as described in doc/README.kbd:
	http://lists.denx.de/pipermail/u-boot/2012-April/122502.html

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-05-15 08:31:32 +02:00
Fabio Estevam
bdb9f7604d mx6qsabrelite: No need to set the direction for GPIO3_23 again
There is a 'gpio_direction_output(87, 0);' call previously, so the GPIO direction is
already established.

Use gpio_set_value() for changing the GPIO output then.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
2012-05-15 08:31:31 +02:00
Stefano Babic
f92e4e6c19 MX53: mx53loco: Add SATA support
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
2012-05-15 08:31:31 +02:00
Timur Tabi
5d065c3e10 powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
Most 85xx boards can be built as a 32-bit or a 36-bit.  Current code sometimes
displays which of these is actually built, but it's inconsistent.  This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used.  Not only that, but each board includes code that displays
the message, so there is duplication.

The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time.  The board-specific code is
deleted.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:34 -05:00
Liu Gang
3f1af81b80 powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.

Master needs to:
	1. Put the slave's ucode image into it's own memory space.
	2. Set an inbound SRIO window covered slave's ucode stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
292dc6c501 powerpc/corenet_ds: Slave module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.
	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
	   locally.

For the slave module, need to finish these processes:
	1. Set the boot location to SRIO1 or SRIO2 by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
	4. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_SLAVE_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
York Sun
1ba62f1017 powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Chunhe Lan
617e46e3c0 powerpc/p1023rds: Disable nor flash node and enable nand flash node
In the p1023rds, when system boots from nor flash, kernel only accesses nor
flash and can not access nand flash with BR0/OR0; when system boots from
nand flash, kernel only accesses nand flash and can not access nor flash
with BR0/OR0.

Default device tree nor and nand node should have the following structure:

	Example:

		nor_flash: nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x02000000>;
			bank-width = <2>;
			device-width = <1>;
			status = "okay";

			partition@0 {
				label = "ramdisk";
				reg = <0x00000000 0x01c00000>;
			};
		}

		nand_flash: nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,p1023-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <0x2 0x0 0x00040000>;
			status = "disabled";

			u-boot-nand@0 {
				/* This location must not be altered  */
				/* 1MB for u-boot Bootloader Image */
				reg = <0x0 0x00100000>;
				read-only;
			};
		}

When booting from nor flash, the status of nor node is enabled and the
status of nand node is disabled in the default dts file, so do not do
anything.

But, when booting from nand flash, need to do some operations:

	o Disable the NOR node by setting status = "disabled";
	o Enable the NAND node by setting status = "okay";

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:30 -05:00
Dirk Behme
03f3587822 i.MX6: arm2: Add AXI cache and Qos setting
Do the same AXI cache and Qos settings done already in the
SabreLite imximage.cfg for the ARM2 board, too.

It fixes a display flash issue caused by low priority of
the display IDMA channel.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-04-17 15:41:22 +02:00
Wolfgang Denk
f5cdc11775 Prepare v2012.04-rc2; minor Coding Style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-04-16 23:13:51 +02:00
Stefano Babic
2f002eceae MX35: mx35pdk: wrong board revision
The board revision is detected accessing to the pmic,
that is not available before relocation (I2C).
This generates the following error:

CPU:   Freescale i.MX35 rev 2.0 at 532 MHz.
Reset cause: WDOG
<reg num> = 7 is invalid. Should be less than 0
Board: MX35 PDK 1.0

The revision number is wrong, as a default value is printed
(tested on a mx35pdk Rev. 2.0).

Move the output in the board_late_init(), when
pmic can be accessed.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-04-16 14:53:59 +02:00
Stefano Babic
d0f5600f54 MX31: mx31pdk: drop enable_caches from board file
enable_caches() is implemented now in cpu.c for
ARM1136.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-04-16 14:53:59 +02:00
Troy Kisky
1482410531 MX53: DDR: Fix ZQHWCTRL field TZQ_CS
Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-04-16 14:53:58 +02:00
Fabio Estevam
19db9be4aa mx53ard: Initialize return code with error
The variable "rc" is the return of board_eth_init() function. Initialize
it with an error code, so that this function can return an error when
CONFIG_SMC911X is not set.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-03-27 09:41:17 +02:00
Eric Nelson
1c9ceff8ca i.MX6: mx6q_sabrelite: add CONFIG_REVISION_TAG
This is needed to support Freescale-supplied userspaces.

At the moment, both the IPU and VPU libraries provided by Freescale
in the "imx-lib" package contain routines which scrape the system
revision from /proc/cpuinfo. In the VPU library, this information is
used to load the proper firmware, allowing a single binary to be used
across various i.MX processors.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-03-27 09:41:15 +02:00
Eric Nelson
d928a8f3f3 mx6q: mx6qsabrelite: setup_spi() should be called in board_init to allow use for environment
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-03-27 09:41:15 +02:00
Wolfgang Grandegger
2ea73e9e38 mx6qsabrelite: add and enable USB Host 1 support
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
2012-03-26 23:09:23 +02:00
Troy Kisky
2bf3359ea5 i.mx6q: mx6qsabrelite: Update the network configuration
Define CONFIG_PHY_MICREL, and
minimize the tx clock delay.

There is an issue with 1000 baseTx mode on early revs
of the SabreLite boards. The center tap pin 9 of the mag RJ45
USB combo was connected to the 3.3 filtered supply. Letting
this pin float solved the problem. Symptoms of the problem
were packets with many extra zeroes tacked on the end, and random
bit flips causing a high rate of CRC errors. 10/100 baseTx worked
fine on all revs. To disable 1000 baseTx for these boards, simply
define the environment variable disable_giga. ie.

setenv disable_giga 1

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2012-02-27 21:19:25 +01:00
Troy Kisky
9fafe7dab9 net: phy: make board_phy_config responsible for calling drv->config
Boards may have things they want done before or after normal phy config.
Letting the boards call drv->config allows them more flexibilty.
Boards affected by this change are corenet_ds and mpc8544ds.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2012-02-27 21:19:25 +01:00
Fabio Estevam
ba901df41b mx35pdk: Remove duplicate CPU revision and reset cause information
MX35PDK board does not need to print CPU revision and reset cause in board file
because this is printed by common code when CONFIG_DISPLAY_CPUINFO is selected

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-02-27 21:19:24 +01:00
Fabio Estevam
ed9d21696d mx51evk: Use gpio_direction_input prior to gpio_get_value
Use gpio_direction_input prior to gpio_get_value.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-02-27 21:19:24 +01:00
Fabio Estevam
c9d5fd1602 mx53smd: Use gpio_direction_input prior to gpio_get_value
Use gpio_direction_input prior to gpio_get_value.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-02-27 21:19:24 +01:00
Fabio Estevam
7d1267d623 mx53evk: Use gpio_direction_input prior to gpio_get_value
Use gpio_direction_input prior to gpio_get_value.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2012-02-27 21:19:24 +01:00
Fabio Estevam
93082044a9 mx53ard: Use gpio_direction_input prior to gpio_get_value
Use gpio_direction_input prior to gpio_get_value.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-02-27 21:19:23 +01:00
Fabio Estevam
a091be766d mx53loco: Use gpio_direction_input prior to gpio_get_value
Use gpio_direction_input prior to gpio_get_value.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
2012-02-27 21:19:23 +01:00
Eric Nelson
ba54b9276a mx6q: mx6qsabrelite: Provide default serial flash bus and chip-select
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-02-27 21:19:23 +01:00
Eric Nelson
373a1d8c0e mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-02-27 21:19:23 +01:00
Matthias Fuchs
ed97abed27 mx28evk: add SPI support
This patch adds SPI support for the MX28EVK. Support for
an optionally installed SPI flash is also added. An example
configuration for redundant envrionment from SPI flash is also
added but disabled by default.

This patch has been tested on a MX28EVK Rev. D with an installed
SST25VF032B 32Mbit SPI flash.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-02-27 21:19:22 +01:00
Matthias Fuchs
598aa2bbfb mx28evk: add USB support
This patch enables USB host support on the MX28EVK board.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-02-27 21:19:22 +01:00
Stefano Babic
b125e7bdd8 imx6: mx6qarm2: updated board_mmc_getcd() to the new prototype
Commit 314284b156 has
changed board_mmc_getcd() function prototype, while
mx6qarm2 has still the old one.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-02-12 10:11:26 +01:00
Jason Liu
2af81e2735 i.mx6q: mx6qsabrelite: Add the ethernet function support
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Eric Miao <eric.miao@linaro.org>
CC: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:26 +01:00
Troy Kisky
8e7d7b6b25 i.mx6q: mx6qsabrelite: Setup uart1 pinmux
This allows the Linux kernel to use UART1 before pinmux
support is added for UART1

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
2012-02-12 10:11:26 +01:00
Fabio Estevam
4394d0c2ee sdhc_boot: Introduce CONFIG_FSL_FIXED_MMC_LOCATION option
Since commit 97039ab98 (env_mmc: Allow board code to override the environment address)
mmc_get_env_addr is a weak-aliased function in common/env_mmc.c

The mmc_get_env_addr implementation that exists at
board/freescale/common/sdhc_boot.c is meant to be used only for PowerPC boards,
but currently it is being used for all platforms that have CONFIG_ENV_IS_IN_MMC defined.

Introduce CONFIG_FSL_FIXED_MMC_LOCATION so that the boards that need to use
the mmc_get_env_addr version from board/freescale/common/sdhc_boot.c could activate
this config option on their board file.

This fixes the retrieval of CONFIG_ENV_OFFSET on non-PowerPC boards.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-02-12 10:11:25 +01:00
Jason Liu
bc5833c49a i.mx: i.mx6q: add the initial support for i.mx6q Sabre Lite board
Add the initial support for Freescale i.MX6Q Sabre Lite board

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
CC: Eric Nelson <eric.nelson@boundarydevices.com>
2012-01-16 08:40:10 +01:00
Fabio Estevam
d109ed946c mx28evk: Remove 'all' target from Makefile
Remove 'all' target from Makefile, as this is unused code.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-01-16 08:40:09 +01:00
Fabio Estevam
29f75a5ce5 mx28evk: Add initial support for MX28EVK board
Add initial support for Freescale MX28EVK board.

Tested boot via SD card and by loading a kernel via TFTP through
the FEC interface.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-16 08:40:09 +01:00
Eric Nelson
3c057897e9 i.mx6q: mx6qarm2: Enable the usboh3 clock
Bits 0 and 1 of CCM_CCGR7 are the usboh3 clock enable bits. Enabling this
clock is necessary for the USB download.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
CC: Jason Hui <jason.hui@linaro.org>
Acked-by: Jason Hui <jason.hui@linaro.org>
2012-01-16 08:40:08 +01:00
Jason Liu
473c63592e i.mx6q: arm2: Add the enet function support
This enable the network function on the i.mx6q armadillo2
board(arm2), thus we can use tftp to load image from network.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
2012-01-16 08:40:08 +01:00
Wolfgang Denk
670c24f6f3 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  fsl_lbc: add printout of LCRR and LBCR to local bus regs
  sbc8548: Fix up local bus init to be frequency aware
  sbc8548: enable support for hardware SPD errata workaround
  sbc8548: relocate fixed ddr init code to ddr.c file
  sbc8548: Make enabling SPD RAM configuration work
  sbc8548: Fix LBC SDRAM initialization settings
  sbc8548: enable ability to boot from alternate flash
  sbc8548: relocate 64MB user flash to sane boundary
  Revert "SBC8548: fix address mask to allow 64M flash"
  MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
  eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
  eXMeritus HWW-1U-1A: Minor environment variable tweaks
2012-01-13 20:38:49 +01:00
Wolfgang Denk
3dc5ea500f Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx:
  mpc8313erdb: fix mtdparts address
  powerpc/83xx/km: add support for 8321 based tuge1 board
  powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
  powerpc/83xx/km: remove obsolete defines for tuda1
  powerpc/83xx/km: update SDRAM parameters for km8321 boards
  mpc8313erdb: Enable GPIO support on the MPC8313E RDB
  mpc83xx: Add a GPIO driver for the MPC83XX family
  gpio: Replace ARM gpio.h with the common API in include/asm-generic
  gpio: Modify common gpio.h to more closely match Linux
2012-01-13 20:07:40 +01:00
Paul Gortmaker
1667013ddf MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
These boards were meaning to deploy this value:

  #define LCRR_DBYP        0x80000000

but were missing a zero, and hence toggling a bit that
lands in an area marked as reserved in the 8548 reference
manual.

According to the documentation, LCRR_DBYP should be used as:

   PLL bypass. This bit should be set when using low bus
   clock frequencies if the PLL is unable to lock.  When in
   PLL bypass mode, incoming data is captured in the middle
   of the bus clock cycle.  It is recommended that PLL bypass
   mode be used at frequencies of 83 MHz or less.

So the impact would most likely be undefined behaviour for
LBC peripherals on boards that were running below 83MHz LBC.
Looking at the actual u-boot code, the missing DBYP bit was
meant to be deployed as follows:

      Between 66 and 133, the DLL is enabled with an
      override workaround.

In the future, we'll convert all boards to use the symbolic
DBYP constant to avoid these "count the zeros" problems, but
for now, just fix the impacted boards.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:57:56 -06:00
Joe Hershberger
0eaf8f9ea8 mpc8313erdb: Enable GPIO support on the MPC8313E RDB
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:33 -06:00
Thierry Reding
314284b156 mmc: Change board_mmc_getcd() function prototype.
The new API no longer uses the extra cd parameter that was used to store
the card presence state. Instead, this information is returned via the
function's return value. board_mmc_getcd() returns -1 to indicate that
no card-detection mechanism is implemented; 0 indicates that no card is
present and 1 is returned if it was detected that a card is present.

The rationale for this change can be found in the following email
thread:

	http://lists.denx.de/pipermail/u-boot/2011-November/110180.html

In summary, the old API was not consistent with the rest of the MMC API
which always passes a struct mmc as the first parameter. Furthermore the
cd parameter was used to mean "card absence" in some implementations and
"card presence" in others.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-01-08 21:28:27 -06:00
Anatolij Gustschin
60bae5ef82 Fix building for mx51evk board
Fix:
mx51evk.c:206:6: error: conflicting types for 'board_ehci_hcd_init'
/u-boot/include/usb/ehci-fsl.h:254:5: note: previous declaration of
'board_ehci_hcd_init' was here

We also fix board_ehci_hcd_init() for mx53loco board.
Building for mx53loco worked since <usb/ehci-fsl.h> is
not included here.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2011-12-19 17:52:43 +01:00
Wolfgang Grandegger
055d969332 USB: mx51evk: add end enable USB host support on port 1
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Jason Liu <r64343@freescale.com>
2011-12-11 14:49:56 +01:00
Wolfgang Grandegger
45cf6ada60 USB: mx53loco: add end enable USB host support on port 1
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Jason Liu <r64343@freescale.com>
2011-12-11 14:49:50 +01:00
Jason Liu
76d7f57449 i.mx: i.mx6q: add the initial support for i.mx6q ARM2 board
Add the initial support for Freescale i.MX6Q Armadillo2 board
Support: MMC boot from slot 0/1, debug UART(UART4), usdhc.

There is two MMC slots on the boards:
mmc dev 0 -> connect USDHC3 -> the lower slot on the board,
mmc dev 1 -> connect USDHC4 -> the upper slot on the board,

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
2011-12-09 17:30:10 +01:00
Wolfgang Denk
c786f54b9a Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  davinci: Remove unwanted memsize.c from hawkboard's nand spl build
  devkit8000: Move CONFIG_SYS_TEXT_BASE out of bss
  da850evm: pass board revision info to kernel
  arch/arm/include/asm/arch-omap5/clocks.h: Fix GCC 4.2 warnings
  arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix GCC 4.6 warnings
  arch/arm/cpu/armv7/omap-common/spl.c: Fix GCC 4.2 warnings
  MX35: flea3: changes due to hardware revision B
  MX: serial_mxc: cleanup removing nasty #ifdef
  M28: Fix OB1 bug in GPIO driver
  MXS: Add static annotations to dma driver
  apbh_dma: return error value on timeout
  Efika: Configure additional regulators for HDMI output
  mx5: Correct a warning in clock.c
  MC13892: Add REGMODE0 bits definitions
  mx51evk: Configure the pins as GPIOs prior to using gpio_get_value
  mx53smd: Configure the pins as GPIOs prior to using gpio_get_value
  mx53evk: Configure the pins as GPIOs prior to using gpio_get_value
  mx53ard: Configure the pins as GPIOs prior to using gpio_get_value
  mx53loco: Configure the pins as GPIOs prior to using gpio_get_value
  OMAP3: Add SPL_BOARD_INIT hook
  AM3517 CraneBoard: Add SPL support
  AM3517: Add SPL support
  OMAP3: Add SPL support to omap3_evm
  OMAP3: Add SPL support to Beagleboard
  OMAP3 SPL: Add identify_nand_chip function
  OMAP3 SPL: Rework memory initalization and devkit8000 support
  OMAP3: Suffix all Micron memory timing parts with their speed
  OMAP3: Add optimal SDRC autorefresh control values
  omap3: mem: Add MCFG helper macro
  OMAP3: Remove get_mem_type prototype
  OMAP3: Change mem_ok to clear again after reading back
  OMAP3: Add a helper function to set timings in SDRC
  OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()
  omap3: mem: Comment enable_gpmc_cs_config more
  ARM: davici_emac: Fix condition for number of phy detects
  arm: printf() is not available in some SPL configurations
  arm, davinci: add support for am1808 based enbw_cmc board
  arm, davinci: move misc function in arch tree
  arm, board/davinci/common/misc.c: Codingstyle cleanup
  arm, davinci, da850: add uart1 tx rx pinmux config
  arm, davinci: move davinci_rtc struct to hardware.h
  arm, davinci: Remove duplication of pinmux configuration code
  arm, hawkboard: Use the pinmux configurations defined in the arch tree
  arm, da850evm: Use the pinmux configurations defined in the arch tree
  arm, da850: Add pinmux configurations to the arch tree
  arm, da850evm: Do pinmux configuration for EMAC together with other pinmuxes
  arm, hawkboard: Remove obsolete struct pinmux_config i2c_pins
  arm, davinci: Move pinmux functions from board to arch tree
  arm, arm926ejs: always do cpu critical inits
  omap_gpmc: use SOFTECC in SPL if it's enabled
  nand_spl_simple: add support for software ECC
  AM3517: move AM3517 specific mux defines to generic header
  AM35xx: add EMAC support
  davinci_emac: hardcode 100Mbps for AM35xx and RMII
  davinci_emac: fix for running with dcache enabled
  arm926ejs: add noop implementation for dcache ops
  davinci_emac: conditionally compile specific PHY support
  davinci_emac: use internal addresses in buffer descriptors
  davinci_emac: move arch-independent defines to separate header
  BeagleBoard: config: Really switch to ttyO2
  ARM: davinci_dm6467Tevm: Fix build breakage
  ARM: OMAP: Remove STACKSIZE for IRQ and FIQ if unused
  ARM: OMAP3: Remove unused define SDRC_R_C_B
  ARM: OMAP3: Remove unused define CONFIG_OMAP3430
  omap4: fix IO setting
  omap4+: streamline CONFIG_SYS_TEXT_BASE and other SDRAM addresses
  omap4460: add ES1.1 identification
  omap4: emif: fix error in driver
  omap: remove I2C from SPL
  omap4460: fix TPS initialization
  omap: fix cache line size for omap3/omap4 boards
  omap4: ttyO2 instead of ttyS2 in default bootargs
  omap: Improve PLL parameter calculation tool
  start.S: remove omap3 specific code from start.S
  armv7: setup vector
  armv7: include armv7/cpu.c in SPL build
  armv7: disable L2 cache in cleanup_before_linux()
  arm, arm926ejs: Fix clear bss loop for zero length bss
  PXA: Move colibri_pxa270 to board/toradex/
  PXA: Flip colibri_pxa27x to pxa-common.h
  PXA: Introduce common configuration header for PXA
  PXA: Rename pxa_dram_init to pxa2xx_dram_init
  PXA: Squash extern pxa_dram_init()
  PXA: Export cpu_is_ and pxa_dram_init functions
  PXA: Cleanup Colibri PXA270
  PXA: Replace timer driver
  PXA: Add cpuinfo display for PXA2xx
  PXA: Separate PXA2xx CPU init
  PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]X
  PXA: Unify vpac270 environment size
  PXA: Enable command line editing for vpac270
  PXA: Adapt Voipac PXA270 to OneNAND SPL
  PXA: Drop Voipac PXA270 OneNAND IPL
  PXA: Fixup PXA25x boards after start.S update
  PXA: Re-add the Dcache locking as RAM for pxa250
  PXA: Rework start.S to be closer to other ARMs
  PXA: Drop XM250 board
  PXA: Drop PLEB2 board
  PXA: Drop CRADLE board
  PXA: Drop CERF250 board
  Fix regression in SMDK6400
  nand: Add common functions to linux/mtd/nand.h
  Ethernut 5 board support
  net: Armada100: Fix compilation warnings
  ARM: remove duplicated code for LaCie boards
  ARM: add support for LaCie 2Big Network v2
  mvsata: fix ide_preinit for missing disks
  netspace_v2: Read Ethernet MAC address from EEPROM
  omap3evm: Add support for EFI partitions
  part_efi: Fix compile errors
2011-12-07 09:09:58 +01:00
Shaohui Xie
4497861ae7 p2041rdb: fix serdes clock map
Description of SerDes clock Bank2 setting in p2041 hardware specification
is wrong, the clock map which based on it is wrong either, so fix the
serdes clock map.

wrong setting of SERDES Reference Clocks Bank2:
SW2[5:6] = ON OFF	=>100MHz for PCI mode
SW2[5:6] = OFF ON	=>125MHz for SGMII mode

right setting of SERDES Reference Clocks Bank2:
SW2[5:6] = OFF OFF	=>100MHz for PCI mode
SW2[5:6] = OFF ON	=>125MHz for SGMII mode
SW2[5:6] = ON OFF	=>156.25MHZ

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-06 21:44:33 -06:00
Fabio Estevam
58aef72d89 mx51evk: Configure the pins as GPIOs prior to using gpio_get_value
Configure the pins as GPIO prior to using gpio_get_value.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-12-06 23:59:39 +01:00
Fabio Estevam
3ee3729e95 mx53smd: Configure the pins as GPIOs prior to using gpio_get_value
Configure the pins as GPIO prior to using gpio_get_value.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-12-06 23:59:39 +01:00
Fabio Estevam
a146dca5c2 mx53evk: Configure the pins as GPIOs prior to using gpio_get_value
Configure the pins as GPIO prior to using gpio_get_value.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <jason.hui@linaro.org>
2011-12-06 23:59:39 +01:00
Fabio Estevam
d59c33a1f3 mx53ard: Configure the pins as GPIOs prior to using gpio_get_value
Configure the pins as GPIO prior to using gpio_get_value.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-12-06 23:59:39 +01:00
Fabio Estevam
73128aad58 mx53loco: Configure the pins as GPIOs prior to using gpio_get_value
Configure the pins as GPIO prior to using gpio_get_value.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <jason.hui@linaro.org>
2011-12-06 23:59:39 +01:00
Wolfgang Denk
e38cc2c771 board/freescale/mpc8610hpcd/mpc8610hpcd.c: Fix GCC 4.6 build warning
Fix:
mpc8610hpcd.c: In function 'pci_init_board':
mpc8610hpcd.c:238:15: warning: variable 'pordevsr' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-02 00:16:30 +01:00
Ira W. Snyder
9839709ea3 mpc85xx: support for Freescale COM Express P2020
This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.

Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.

This board has no NOR flash, and can only be booted via SD or SPI. This
procedure is documented in Freescale Document Number AN3659 "Booting
from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is
provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated
Processor Reference Manual" (section 4.5).

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 09:07:51 -06:00
Shengzhou Liu
ae6b03fefc powerpc/p3060qds: Add board related support for P3060QDS platform
The P3060QDS is a Freescale reference board for the six-core P3060 SOC.

P3060QDS Board Overview:
 Memory subsystem:
  - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
  - 128M Bytes NOR flash single-chip memory
  - 16M Bytes SPI flash
  - 8K Bytes AT24C64 I2C EEPROM for RCW
 Ethernet:
  - Eight Ethernet controllers (4x1G + 4x1G/2.5G)
  - Three VSC8641 PHYs on board (2xRGMII + 1xMII)
  - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3
 PCIe: Two PCI Express 2.0 controllers/ports
 USB:  Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board
 I2C:  Four I2C controllers
 UART: Supports two dUARTs up to 115200 bps for console
 RapidIO:  Two RapidIO, sRIO1 and sRIO2

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-29 08:48:06 -06:00
Kim Phillips
b86c770973 mpc83xx: mpc8360emds - fix gcc 4.6 compiler warning
Configuring for MPC8360EMDS_66_HOST_33 - Board: MPC8360EMDS, Options: CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1
mpc8360emds.c: In function 'board_eth_init':
mpc8360emds.c:178:12: warning: array subscript is above array bounds [-Warray-bounds]

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-16 21:41:39 +01:00
Kumar Gala
4589728e21 powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND
Size grew a bit so nand-spl didn't fit in 4k, reduce done by removing
LAW entries not needed during SPL phase.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 08:14:53 -06:00
Kumar Gala
e3779209dd board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warning
mpc8569mds.c: In function 'local_bus_init':
mpc8569mds.c:306:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:49:00 -06:00
Kumar Gala
502dd36b78 board/freescale/mpc8568mds/mpc8568mds.c: Fix GCC 4.6 build warning
Fix:

mpc8568mds.c: In function 'local_bus_init':
mpc8568mds.c:150:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable]
mpc8568mds.c: In function 'pib_init':
mpc8568mds.c:271:11: warning: variable 'orig_i2c_bus' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:49:00 -06:00
Kumar Gala
945f43101e board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warning
Fix:

mpc8548cds.c: In function 'local_bus_init':
mpc8548cds.c:87:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable]
mpc8548cds.c: In function 'lbc_sdram_init':
mpc8548cds.c:121:7: warning: variable 'cpu_board_rev' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:49:00 -06:00
Kumar Gala
8dbd4b746d board/freescale/common/pixis.c: Fix GCC 4.6 build warning
Fix:

pixis.c: In function 'strfractoint':
pixis.c:383:6: warning: variable 'intarr_len' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:48:59 -06:00
Kumar Gala
67926c2a1d board/freescale/common/cds_pci_ft.c: Fix GCC 4.6 build warning
Fix:

cds_pci_ft.c: In function 'cds_pci_fixup':
cds_pci_ft.c:31:12: warning: variable 'tmp' set but not used [-Wunused-but-set-variable]

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:48:59 -06:00
Jerry Huang
71775d3b54 powerpc/mpc85xx: Set SYSCLK to the required frequency
For ICS307-02, there is one general expression to generate SYSCLK:
CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)

If we want the required frequency for SYSCLK, we must find one solution
to generate this frequency, this solution includes VDW, RDW and OD.
For OD, there are only eight option value: 10, 2, 8, 4, 5, 7, 3, 6.
For RDW, the range is 1 to 127.
For VDW, the range is 4 to 511.

First, we use one OD, RDW and required SYSCLK to calculate the VDW,
if VDW is in it's range, we will calculate the CLK1Frequency with
the OD, RDW and VDW calculated, and we will check this percent
(CLK1Frequency / required SYSCLK), and the precision is 1/1000.
if the percent is less than 1/1000, we think the CLK1Frequency is we want.
Otherwise, We will continue to calculate it with the next OD and RDW.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-11 07:48:54 -06:00
Kumar Gala
e4382acb1f powerpc/85xx: Fix MPC8572DS NAND build
Reduce NAND SPL build size by not include TLB entries that arent used by
it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 11:03:54 -06:00
Ramneek Mehresh
a311db6941 powerpc/85xx: Make inclusion of USB device fixup conditional
Include call to usb device-fixup only when CONFIG_HAS_FSL_DR_USB is
defined for the platform - P1020RDB, P1010RDB, P1020-PC

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:36:04 -06:00
chenhui zhao
d37012289d powerpc/mpc8548cds: Fix network initialization
Add board_eth_init(). PCIe network card is also supported.
Put RGMII init after tsec_eth_init().
Skip initializing eTSEC3 and eTSEC4 with Carrier boards prior to ver 1.3.

Signed-off-by: Ebony Zhu
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
2011-11-08 08:30:47 -06:00
Roy Zang
afc52db2f7 powerpc/QorIQ: fix network frame manager TBI PHY address settings
TBI PHY address (TBIPA) register has been set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c

So remove the duplicate code on QorIQ frame manager Ethernet related
platforms, which include Hydra board, P4080DS board and P2041rdb board.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:18:16 -06:00
Wolfgang Denk
5721385b18 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx:
  powerpc/mpc83xx: Add 33.33MHz support for mpc8360emds
  powerpc/mpc83xx: Add 512MB DDR support for mpc8360emds
  mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code
  mpc83xx: Cleanup usage of LBC constants
  mpc83xx: Cleanup usage of DDR constants
  mpc83xx: Cleanup usage of BAT constants
  mpc83xx: cosmetic: vme8349.h checkpatch compliance
  mpc83xx: cosmetic: ve8313.h checkpatch compliance
  mpc83xx: cosmetic: sbc8349.h checkpatch compliance
  mpc83xx: cosmetic: mpc8308_p1m.h checkpatch compliance
  mpc83xx: cosmetic: kmeter1.h checkpatch compliance
  mpc83xx: cosmetic: TQM834x.h checkpatch compliance
  mpc83xx: cosmetic: SIMPC8313.h checkpatch compliance
  mpc83xx: cosmetic: MVBLM7.h checkpatch compliance
  mpc83xx: cosmetic: MPC837XERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC837XEMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC8360ERDK.h checkpatch compliance
  mpc83xx: cosmetic: MPC8360EMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC8349ITX.h checkpatch compliance
  mpc83xx: cosmetic: MPC8349EMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC832XEMDS.h checkpatch compliance
  mpc83xx: cosmetic: MPC8323ERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC8315ERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC8313ERDB.h checkpatch compliance
  mpc83xx: cosmetic: MPC8308RDB.h checkpatch compliance
  mpc83xx: cosmetic: MERGERBOX.h checkpatch compliance
  mpc83xx: Fix ipic structure definition
  powerpc, mpc83xx: add DDR SDRAM Timing Configuration 3 definitions
  cosmetic, powerpc, mpc83xx: checkpatch cleanup
  powerpc/83xx: move km 83xx specific i2c code to km83xx_i2c
  mpc83xx: fix global timer structure definition
2011-11-08 07:44:52 +01:00
Wolfgang Denk
688d8f33f2 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  Arm: re-introduce the MACH_TYPE_XXXXXX for EB_CPUX9K2 board
  arm: jadecpu: Readd MACH_TYPE_JADECPU
  at91: defined mach-types for otc570 board in board config file
  at91: defined mach-types for meesc board in board config file
  mx31pdk: Enable D and I caches
  ehci-mxc: remove incorrect comment
  README: Fix supported i.MX SoC list for CONFIG_MXC_SPI
  mx53: Turn off child clocks before reconfigure perclk_root
  qong: enable support for compressed images
  imx: imx31_phycore.h: fix checkpatch warnings
  vision2: Remove unused get_board_rev function
  mx53smd: Remove unused get_board_rev function
  mx53ard: Remove unused get_board_rev function
  mx53evk: Remove unused get_board_rev function
  mx53evk: Add RTC support
  mx53loco: Remove unused get_board_rev function
  mx53evk: Remove unneeded '1' from mx53evk.h
  OMAP3: mvblx: Initial support for mvBlueLYNX-X
  ARM: dig297: Define MACH_TYPE_OMAP3_CPS and CONFIG_MACH_TYPE
  omap3: mem: Move comments next to definitions
  omap3: mem: Clean-up whitespaces
  omap3: mem: Define and use common macros
  Davinci: ea20: added PREBOOT to configuration
  Davinci: ea20: added I2C support
  Davinci: ea20: added video support
  VIDEO: davinci: add framebuffer to da8xx
  ARM: Davinci: added missing registers to hardware.h
  Davinci: ea20: add gpios for LCD backlight control
  Davinci: ea20: add gpio for keeping power on in board_late_init
  Davinci: ea20: Add default U-Boot environment
  Davinci: ea20: Add early init to get early output from console
  Davinci: ea20: Add NAND support
  Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
  Davinci: ea20: set console on UART0
  arm, davinci: add cam_enc_4xx support
  arm926ejs, davinci: add missing spi defines for dm365
  arm926ejs, davinci: add cpuinfo for dm365
  arm, davinci: add lowlevel function for dm365 soc
  arm, davinci: add header files for dm365
  spl, nand: add 4bit HW ecc oob first nand_read_page function
  arm, davinci: add support for new spl framework
  spl: add option for adding post memory test to the SPL framework
  net, davinci_emac: make clock divider in MDIO control register configurable
  arm, usb, davinci: make USBPHY_CTL register configurable
  usb, davinci: add enable_vbus() weak function
  omap3evm: fix errors caused by multiple definitions
  omap3evm: Add (quick) configuration for NAND only
  omap3evm: Add (quick) configuration for MMC/SD only
  omap3evm: move common config options to new file
  omap3evm: Prepare to split configuration
  omap3evm: Reorder related config options
  omap/spl: actually enable the console
  davinci_emac: compilation fix, phy is array now
  omap3evm: Set environment variable 'ethaddr'
  arm, arm926: fix missing symbols in NAND_SPL mode
  arm, davinci: Add function lpsc_syncreset()
  arm, davinci: replace CONFIG_PRELOADER with CONFIG_SPL_BUILD
  arm/km: portl2 environment address update to P1B
  arm/km: adapt bootcounter evaluation
  arm/km: enable jffs2 cmds
  arm/km: trigger reconfiguration for the Xilinx FPGA
  arm/km: add boardid and hwkey to kernel command line
  ARM: Reintroduce MACH_TYPE_KM_KIRKWOOD for keymile ARM boards
  netspace_v2: enable I2C EEPROM support
  netspace_v2: fix SDRAM configuration
  armada100: define CONFIG_SYS_CACHELINE_SIZE
  pantheon: define CONFIG_SYS_CACHELINE_SIZE
  kirkwood: define CONFIG_SYS_CACHELINE_SIZE
  kirkwood: drop empty asm-offsets.s file
  arm/km/mgcoge3un: enhance "waitforne" feature
  arm/km: add variable waitforne to mgcoge3un
  gplugD: Fix for error:MACH_TYPE_SHEEVAD undeclared
  ARM: dreamplug: fix compilation
  ARM: DockStar: fix compilation
  ARM: netspace_v2: fix warnings
  am335x: Drop board_sysinfo struct
  am335x: Temporarily add MACH_TYPE define
  misc:pmic:samsung Enable PMIC driver at C210 Universal target
  dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p UNIVERSAL C210 target
  dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p GONI target
  smdkv310: use macro for mmc data read function address
  smdkv310: use spl framework for mmc spl
  SMDKV310: use get_ram_size() to validate dram size
  SMDKV310: Initialize board id using CONFIG_MACH_TYPE
  ORIGEN : use absolute paths and fix tool naming
  ORIGEN : enable device tree support
  MX25: tx25: Fix building due to missing MACH_TYPE
  mx31: Add board support for HALE TT-01
  mx31: add ESD control registers
  mx31: define pins and init for UART2 and CSPI3
  MX35: add support for flea3 board
  MX51: vision2: add MACH_TYPE in config file
  vision2: Remove unused header file
  mx51evk: Remove unused get_board_rev function
  mx51evk: Remove unneeded '1' from mx51evk.h
  I2C: Fix mxc_i2c.c problem on imx31_phycore
  mx35pdk: Add RTC support
  mx51evk: Use GPIO API for configuring the IOMUX
  mx51evk: Add RTC support
  rtc: Make mc13783-rtc driver generic
  qong: remove unneeded IOMUX settings
  qong: Use mx31_set_gpr to setup USBH2 pins
  mx31: Introduce mx31_set_gpr function
  mx31pdk: Add MC13783 PMIC support
  qong: remove unneeded "1" from qong.h
  misc: pmic: fix regression in pmic_fsl.c (SPI)
  mx5 configs: CONFIG_PRIME should really be CONFIG_ETHPRIME
  MX35: Drop unnecessary prototypes from imx-regs.h
  I2C: added I2C-2 and I2C-3 to MX35
  MX35: factorize common assembly code
  MX35: add reset cause as provided by other i.MX
  MX35: add pins definition for UART3
  MX35: added ESDC structure to imx-regs
2011-11-08 00:38:52 +01:00
Wolfgang Denk
7ba6d591b5 Merge branch 'master' of git://git.denx.de/u-boot-coldfire
* 'master' of git://git.denx.de/u-boot-coldfire:
  ColdFire: The EB+MCF-EV123 boards config update
  ColdFire: Fix the compile issue for M52277
  ColdFire:Moving the remaining coldfire boards to boards.cfg
2011-11-08 00:37:27 +01:00
Wolfgang Denk
caf63eb4a0 board/freescale/mpc8266ads/mpc8266ads.c: Fix GCC 4.6 build warning
Fix:
mpc8266ads.c: In function 'initdram':
mpc8266ads.c:278:9: warning: variable 'spd_size' set but not used
[-Wunused-but-set-variable]

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-11-07 22:49:44 +01:00
Wolfgang Denk
55e33279ce board/freescale/mpc8266ads/mpc8266ads.c: CodingStyle cleanup
Make (mostly) checkpatch clean.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Rune Torgersen <runet@innovsys.com>
2011-11-07 22:48:26 +01:00
Jason Jin
27f7ae70d6 ColdFire: Fix the compile issue for M52277
After commit 327474f854, the
M52277EVB_stmicro configuration fail to build. Fix it by moving
the env outside the flash and update the lds file.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2011-11-07 22:02:33 +08:00
Fabio Estevam
867b96a5b7 mx31pdk: Enable D and I caches
Enable D and I caches on mx31pdk.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-11-04 22:06:37 +01:00
Fabio Estevam
6bc31fbe08 mx53smd: Remove unused get_board_rev function
No board information is passed for MX53SMD, so remove get_board_rev function.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-11-04 22:06:37 +01:00
Fabio Estevam
d7f71414f4 mx53ard: Remove unused get_board_rev function
No board information is passed for MX53ARD, so remove get_board_rev function.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-11-04 22:06:37 +01:00
Fabio Estevam
850f4d6773 mx53evk: Remove unused get_board_rev function
No board information is passed for MX53EVK, so remove get_board_rev function.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2011-11-04 22:06:37 +01:00
Fabio Estevam
aa2bcf4be5 mx53loco: Remove unused get_board_rev function
No board information is passed for MX53LOCO, so remove get_board_rev function.

Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
2011-11-04 22:06:37 +01:00
Jerry Huang
d37be07ee5 powerpc/mpc83xx: Add 512MB DDR support for mpc8360emds
The new MPC8360EMDS board supports 512MB DDR since 2008.

For 512MB DDR:
BAT0 is used for the first 256MB memory, BAT4 is used for the second
256MB memory and the address space of SDRAM follows the DDR, so if the
size of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of
DDR is 512MB, the BAT4 will be used for the second 256MB memory and
there is no BAT for SDRAM.
Therefore, if the size of DDR is 512MB, this patch will use BAT6 for
SDRAM and BAT5 will be used for PCI MEM to replace the BAT6 after the
codes relocates to the DDR.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:56 -05:00
Joe Hershberger
2e651b2483 mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code
Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring
Cleanup the setting of the csnbds to respect the setting of
CONFIG_SYS_DDR_SDRAM_BASE
Use __ilog2 instead of writing the code to compute it
Disable unused CS configs
Ensure ddrlaw.bar is configured

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-11-03 18:27:56 -05:00
Fabio Estevam
9c818b1b98 mx51evk: Remove unused get_board_rev function
No board information is passed for MX51EVK, so remove get_board_rev function.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-11-03 22:56:19 +01:00
Fabio Estevam
d736ebea1c mx51evk: Use GPIO API for configuring the IOMUX
GPIO API provides mxc_request_iomux function for setting the IOMUX mode.

Use this function instead of directly writing to the IOMUX register.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-11-03 22:56:19 +01:00
Fabio Estevam
1f83d009e4 mx31pdk: Add MC13783 PMIC support
Add MC13783 PMIC support.

Tested by using the 'date' command, which reads the MC13783 RTC registers:

MX31PDK U-Boot > date
Date: 1970-01-01 (Thursday)    Time:  2:22:35

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-11-03 22:56:18 +01:00
Stefano Babic
9d940442d3 MX35: added ESDC structure to imx-regs
The structure and PLL defines are added to
the imx-regs.h file and dropped from board
header files.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-11-03 22:56:17 +01:00
Wolfgang Denk
87a5d60103 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  ARM: Add Calxeda Highbank platform
  dkb: make mmc command as default enabled
  Marvell: dkb: add mmc support
  ARM: pantheon: add mmc definition
  davinci: remove config.mk file from the sources
  ARM:AM33XX: Add support for TI AM335X EVM
  ARM:AM33XX: Added timer support
  ARM:AM33XX: Add emif/ddr support
  ARM:AM33XX: Add clock definitions
  ARM:AM33XX: Added support for AM33xx
  omap3/emif4: fix registers definition
  davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
  davinci: emac: add support for more than 1 PHYs
  davinci: emac: add new features to autonegotiate for EMAC
  da850evm: Move LPSC configuration to board_early_init_f()
  omap4_panda: Build in cmd_gpio support on panda
  omap: Don't use gpio_free to change direction to input
  mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
  OMAP3: overo : Add environment variable optargs to bootargs
  OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
  OMAP3: overo : Use ttyO2 instead of ttyS2.
  da830: add support for NAND boot mode
  dm36x: revert cache disable patch
  dm644X: revert cache disable patch
  devkit8000: Add malloc space
  omap: spl: fix build break due to changes in FAT
  OMAP3 SPL: Provide weak omap_rev_string
  omap: beagle: Use ubifs instead of jffs2 for nand boot
  omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
  omap: overo: Configure mux for gpio10
  SPL: Add DMA library
  omap3: Add interface for omap3 DMA
  omap3: Add DMA register accessors
  omap3: Add Base register for DMA
  arm, davinci: add missing LSPC define for MMC/SD1
  U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
  DaVinci: correct MDSTAT.STATE mask
  omap4: splitting padconfs into common, 4430 and 4460
  omap4: adding revision detection for 4460 ES1.1
  omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
  gplug: fixed build error as a result of code cleanup patch
  kirkwood_spi: add dummy spi_init()
  gpio: mvmfp: reduce include platform file
  ARM: orion5x: reduce dependence of including platform file
  serial: reduce include platform file for marvell chip
  ARM: kirkwood: reduce dependence of including platform file
  ARM: armada100: reduce dependence of including platform file
  ARM: pantheon: reduce dependence of including platform file
  Armada100: Add env storage support for Marvell gplugD
  Armada100: Add SPI flash support for Marvell gplugD
  Armada100: Add SPI support for Marvell gplugD
  SPI: Add SPI driver support for Marvell Armada100
  dreamplug: initial board support.
  imx: fix coding style
  misc: pmic: drop old Freescale's pmic driver
  MX31: mx31pdk: use new pmic driver
  MX31: mx31ads: use new pmic driver
  MX31: mx31_litekit: use new pmic driver
  MX5: mx53evk: use new pmic driver
  MX5: mx51evk: use new pmic driver
  MX35: mx35pdk: use new pmic driver
  misc: pmic: addI2C  support to pmic_fsl driver
  misc: pmic: use I2C_SET_BUS in pmic I2C
  MX5: efikamx/efikasb: use new pmic driver
  MX3: qong: use new pmic driver
  RTC: Switch mc13783 to generic pmic code
  MX5: vision2: use new pmic driver
  misc: pmic: Freescale PMIC switches to generic PMIC driver
  misc:pmic:samsung Enable PMIC driver at GONI target
  misc:pmic:max8998 MAX8998 support at a new PMIC driver.
  misc:pmic:core New generic PMIC driver
  mx31pdk: Remove unneeded config
  mx31: provide readable WEIM CS accessor
  MX51: vision2: Set global macros
  I2C: Add i2c_get/set_speed() to mxc_i2c.c
  ARM: Update mach-types
  devkit8000: Add config to enable SPL MMC boot
  devkit8000: protect board_mmc_init
  arm, post: add missing post_time_ms for arm
  cosmetic, post: Codingstyle cleanup
  arm, logbuffer: make it compileclean
  tegra2: Enable MMC for Seaboard
  tegra2: Add more pinmux functions
  tegra2: Rename PIN_ to PINGRP_
  tegra2: Add more clock functions
  tegra2: Clean up board code a little
  tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
2011-10-28 00:15:19 +02:00
Marek Vasut
7315ab226e GCC4.6: Squash warnings in mpc8610hpcd.c
mpc8610hpcd.c: In function 'misc_init_r':
mpc8610hpcd.c:79: warning: format '%02lx' expects type 'long unsigned int', but
argument 2 has type 'int'
mpc8610hpcd.c:86: warning: format '%02lx' expects type 'long unsigned int', but
argument 2 has type 'int'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:01 +02:00
Marek Vasut
1f09b44cae GCC4.6: Squash warnings in diu.c
diu.c: In function 'diu_set_pixel_clock':
diu.c:77: warning: format '%lu' expects type 'long unsigned int', but argument 2
has type 'u32'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:01 +02:00
Marek Vasut
dffe06fa4a GCC4.6: Squash warning in mpc5121ads.c
mpc5121ads.c: In function 'misc_init_r':
mpc5121ads.c:256: warning: format '%02lx' expects type 'long unsigned int', but
argument 2 has type 'int'
mpc5121ads.c:263: warning: format '%02lx' expects type 'long unsigned int', but
argument 2 has type 'int'

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-27 23:54:01 +02:00
Helmut Raiger
9660e442de cosmetic: s/BOARD_LATE_INIT/CONFIG_BOARD_LATE_INIT
This renames BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT.
Along the way it removes some leftover

 #define BOARD_LATE_INIT		1

and adds some basic documentation for board specific
callbacks in README.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-10-27 23:53:59 +02:00
Fabio Estevam
77f11a99e1 imx: fix coding style
Fix checkpatch warning and errors in several i.MX related files.

While at it also address a checkpatch warning at arch/arm/cpu/armv7/mx5/soc.c
regarding the usage of extern in a C file.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-10-27 21:56:32 +02:00
Stefano Babic
bba1b6cf15 MX5: mx53evk: use new pmic driver
Switch to new pmic generic driver.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
2011-10-27 21:56:32 +02:00
Stefano Babic
5357265a62 MX5: mx51evk: use new pmic driver
Switch to new pmic generic driver.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:32 +02:00
Stefano Babic
5213d6e48e MX35: mx35pdk: use new pmic driver
Switch to new pmic generic driver.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:31 +02:00
Helmut Raiger
47c5455a48 mx31: provide readable WEIM CS accessor
setup_weimcs() and some macros are added to support the setup
for i.MX31 WEIM chip selects. As a compromise between verbosity
and readability an ASCII-art'ish bit comment is used instead of
bitfields.
All i.MX31 boards have been patched to use this approach using a
helper program to verify the changes.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
2011-10-27 21:56:30 +02:00
Mike Frysinger
26ddff2d8d build: add missing $(AR)->$(cmd_link_o_target) update
Seems people fixed their files to use libfoo.o, but didn't actually
update the creation targets to use $(cmd_link_o_target).  Update the
rest of the Makefile's found with grep.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Simon Glass <sjg@chromium.org>
2011-10-22 01:18:41 +02:00
Anatolij Gustschin
c4c9fbebae consolidate mdelay by providing a common function for all users
There are several mdelay() definitions in the driver and
board code. Remove them all and provide a common mdelay()
in lib/time.c.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-10-22 01:16:08 +02:00
Wolfgang Denk
02aff558f4 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  mpc85xx: Add inline GPIO acessor functions
  powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
  powerpc/85xx: Fix P2020DS booting
  powerpc/85xx: Update USB device tree status based on pin settings
  fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers
  powerpc/85xx: Add support for RMan LIODN initialization
  powerpc/85xx: Update device tree handling for SRIO
  powerpc/85xx: Update setting of SRIO LIODNs
  fm: Don't allow disabling of FM1-DTSEC1
  fm-eth: Don't mark the MAC we use for MDIO as disabled in device tree
2011-10-21 23:48:46 +02:00
Timur Tabi
a836626cc4 powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 16:01:37 -05:00
stany MARCEL
606667d252 ColdFire: Fix compilation with CONFIG_SYS_DRAMSZ1 defined
A temp variable was used but not declared, with CONFIG_SYS_DRAMSZ1
defined. This variable is now declared in the functione when needed.

Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
2011-10-19 00:14:16 +08:00
stany MARCEL
327474f854 ColdFire: Merge differentiated linking files into a sigle one by board
The spa, stm, int, 32 and 16 linking files are identical so there is
no need to differentiate them. A single lds file is now used, and
_config rule are simplified.

Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
2011-10-19 00:13:39 +08:00
stany MARCEL
25ceb277de ColdFire: Cleanup lds files for multiple defined symbols
Lds files cleened to remove multiple defined section and modified to
be compliant with --gc-sections added for ColdFire platform in a
previous patch.

Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-10-19 00:13:13 +08:00
Kumar Gala
3b001ad26d powerpc/85xx: Fix P2020DS booting
The following commit removed the code that set odt_rd_cfg and
odt_wr_cfg.  With out this code P2020DS board will not boot:

commit 712cf7ab0b
Author: York Sun <yorksun@freescale.com>
Date:   Mon Oct 3 09:19:53 2011 -0700

    powerpc/mpc8xxx: Merge entries in DDR speed table

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-18 01:31:08 -05:00
Shengzhou Liu
2a523f5240 fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers
Add common function fdt_set_node_status() to assist in various locations
that we set a nodes status.  This function utilizes the status values
that are part of the EPAPR spec (on power.org).

fdt_set_status_by_alias() is based on fdt_set_node_status() but uses an
alias string to identify the node to update.

We also add some shortcut functions to help the common cases of setting
"okay" and "disabled":

	fdt_status_okay()
	fdt_status_disabled()
	fdt_status_okay_by_alias()
	fdt_status_disabled_by_alias()

Finally, we fixup the corenet_ds ethernet code which previously had
a function by the same name that can be replaced with the new helpers.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
2011-10-18 00:36:55 -05:00
Mike Frysinger
464c79207c punt unused clean/distclean targets
The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used.  Punt them all.

MAKEALL didn't report any errors related to this that I could see.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-15 22:20:36 +02:00
chenhui zhao
fff80975ae powerpc/mpc8548cds: Code cleanup and refactoring
- Rework tlb and law tables.
- PCI2 is not available on MPC8548CDS, so remove it.
- Move the memory map to the board config file.
- Rewrite the board info according to the manual.
- Remove unnecessary macros and redefine some macros to align with other boards.
- Fix some typos.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-13 23:38:10 -05:00
Xie Xiaobo
8af3d22db9 powerpc/mpc8536ds: Invert SDHC_WP pin polarity
MPC8536 Rev 1.0 silicon have NMG_eSDHC118 erratum, so that the SDHC write
protected pin polarity does not follow the SD card standard in MPC8536
Rev 1.0 silicon.

The MPC8536DS board invert the SDHC_WP pin as a workaround.  However, this
silicon erratum has been fixed in Rev 1.1, So need invert the SDHC_WP
polarity again when use the MPC8536 Rev1.1 and greater on MPC8536DS board.

Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-09 17:57:54 -05:00
Xie Xiaobo
ae2044d8b3 powerpc/mpc8536ds: Add eSPI support for MPC8536DS
1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS,
   so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width
   to 4-bit and enable SPI signals.
2. Add eSPI controller and SPI-FLASH definition.

Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-09 17:57:54 -05:00
York Sun
712cf7ab0b powerpc/mpc8xxx: Merge entries in DDR speed table
It is not necessary to keep multiple entries for the same setting in DDR
speed tables. Merge them for smaller tables. Also restructure the tables
for smaller size. Cleanup some typedefs.

Enforce strict checking for speed table. If DIMM is running at higher than
known speed, try to use the highest speed setting. If rank is unknown, it
has to panic.

Removed ODT overriding for P2020DS as it is not necessary.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-09 17:57:53 -05:00
Wolfgang Denk
1fed668b3f Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/p3060: Add SoC related support for P3060 platform
  powerpc/85xx: Add support for setting up RAID engine liodns on P5020
  powerpc/85xx: Refactor some defines out of corenet_ds.h
  fm-eth: Add ability for board code to disable a port
  powerpc/mpc8548: Add workaround for erratum NMG_LBC103
  powerpc/mpc8548: Add workaround for erratum NMG_DDR120
  powerpc/mpc85xxcds: Fix PCI speed
  powerpc/mpc8548cds: Fix booting message
  powerpc/p4080: Add support for secure boot flow
  powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
  powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
  powerpc/p2041rdb: remove watch dog related codes
  powerpc/p2041rdb: updated description of cpld command
  powerpc/p2041rdb: add more ddr frequencies support
  powerpc/p2041rdb: set sysclk according to status of physical switch SW1
  powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
  powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc8xxx: Add DDR2 to unified DDR driver
  powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
  powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
  powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
  powerpc/85xx: Refactor P2041RDB to use common p_corenet files
  powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
  powerpc/85xx: Enable CMD_REGINFO on corenet boards
  powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
  powerpc/85xx: Fix USB protocol definitions for P1020RDB
  powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
  powerpc/mpc8xxx: Move DDR RCW overriding to common code
  powerpc/mpc8xxx: Extend CWL table
  powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
  powerpc/85xx: Cleanup extern in corenet_ds board code
  powerpc/p2041rdb: Add ethernet support on P2041RDB board
  powerpc/85xx: Add networking support to P1023RDS
  powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
  powerpc/85xx: Add FMan ethernet support to P4080DS
  powerpc/85xx: Add support for FMan ethernet in Independent mode
  powerpc/mpc8548cds: Cleanup mpc8548cds.c
  powerpc/mp: add support for discontiguous cores
  powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
  fdt: Add new fdt_create_phandle helper
  fdt: Rename fdt_create_phandle to fdt_set_phandle
  powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
  fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
  powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
  fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
  powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
  powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
  nand: Freescale Integrated Flash Controller NAND support
  powerpc/85xx: Add basic support for P1010RDB
  powerpc/85xx: Add support for new P102x/P2020 RDB style boards
  powerpc/85xx: relocate CCSR before creating the initial RAM area
  powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
  powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
  powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
2011-10-04 22:08:13 +02:00
chenhui zhao
568336ecc7 powerpc/mpc85xxcds: Fix PCI speed
The CDS uses PCICLK as SYSCLK. The PCICLK should be 33333333Hz or 66666666Hz.

Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:52:14 -05:00
chenhui zhao
a6d0bfa86f powerpc/mpc8548cds: Fix booting message
Align the output for PCI. Replace "PCI" with "PCI1".

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
2011-10-03 08:52:14 -05:00
Shaohui Xie
93ab6ca1c8 powerpc/p2041rdb: remove watch dog related codes
CPLD 2.2 removed board watch dog support due to the limitation of CPLD
capacity after adding all the requested features, such as switch overriding.
There is no pin-compatible upgrade part available for current PCB design.
So remove codes related to it.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:52:13 -05:00
Shaohui Xie
60820457cc powerpc/p2041rdb: updated description of cpld command
According to CPLD 2.2, the default configuration is changed, so updated the
description of CPLD command, otherwise it will confusing.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:52:13 -05:00
Shaohui Xie
47784af714 powerpc/p2041rdb: add more ddr frequencies support
This table covers DDR frequencies from 666 to 1666. Frequencies 666, 833,
1000, 1066 and 1333 were verified on this board with SO-DIMM
(UG51U6400N8SU-ACF).

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:30:06 -05:00
Shaohui Xie
44d50f0b54 powerpc/p2041rdb: set sysclk according to status of physical switch SW1
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.

SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:30:02 -05:00
Shaohui Xie
ba50fee6ae powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
CPLD 2.0 provides a new register which bit[0] is set to '1' will reset
board with initializing the CPLD registers to default values. And add
bit[6] of register at offset 0x5 to use to enable flash bank selection.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:29:54 -05:00
Fabio Estevam
00e11a4397 mx53evk: Place machine ID into board config
Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
2011-09-30 22:01:04 +02:00
Fabio Estevam
7c2eabab0d mx53ard: Place machine ID into board config
Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:04 +02:00
Fabio Estevam
c4c596fb46 mx53smd: Place machine ID into board config
Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:04 +02:00
Fabio Estevam
9df82896c5 mx53loco: Place machine ID into board config
Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <jason.hui@linaro.org>
2011-09-30 22:01:04 +02:00
Fabio Estevam
4cd300ef16 mx51evk: Place machine ID into board config
Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:04 +02:00
Fabio Estevam
da3598ac7a mx31ads: Place machine ID into board config
Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:04 +02:00
Fabio Estevam
f39c008e92 mx25pdk: Place machine ID into board config
Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:03 +02:00
Fabio Estevam
9aa3c6a1ee mx31pdk: Place machine ID into board config
Let common code set the machine ID.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:03 +02:00
Fabio Estevam
14c7817b87 mx31ads: Remove dram_init_banksize()
As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:03 +02:00
Fabio Estevam
c3f4f31bcb mx25pdk: Remove dram_init_banksize()
As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:03 +02:00
Fabio Estevam
9bd72ebd0e mx31pdk: Remove dram_init_banksize()
As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:03 +02:00
Fabio Estevam
419adbfbcb MX25: Add initial support for MX25PDK
Add the initial support for MX25PDK booting from SD card via internal boot.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-30 22:01:00 +02:00
York Sun
d4b9106609 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c.
The unified driver can initialize data using DDR controller. No need to
use DMA if just to initialze for ECC.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
Kumar Gala
f8bc7bb5a7 powerpc/85xx: Refactor P2041RDB to use common p_corenet files
The P2041RDB has almost identical setup for TLB, LAWS, and PCI with
other P-Series CoreNet platforms.

The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the
CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the
TLB and LAW setup tables.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
Kumar Gala
360275b362 powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that
are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and
P5020DS.  There is a significant amount of commonality shared between
these boards that we can refactor into common code:

* Initial LAW setup
* Initial TLB setup
* PCI setup

We start by moving the shared code between P3041DS, P4080DS, and P5020DS
into a common directory to be shared with other P-Series CoreNet boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
Kumar Gala
aa061aeb23 powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
9ec8dec539 powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
RDIMM has different timing parameters from UDIMM. Create new tables for
RDIMMs. Single-, dual- and quad-rank RDIMMs have been verified with speeds
from 800 to 1333MT/s. Speed table expands to include 1600MT/s for future
use. Single- and quad-rank RDIMM entries are copied into UDIMM tables for
future use.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
cda1de21de powerpc/mpc8xxx: Move DDR RCW overriding to common code
DDR RCW varies at different speeds. It is common for all platform. Move it
out from corenet_ds.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
Kumar Gala
5471370b43 powerpc/85xx: Cleanup extern in corenet_ds board code
Move extern of pci_of_setup() into corenet_ds.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Mingkai Hu
0787ecc01f powerpc/p2041rdb: Add ethernet support on P2041RDB board
Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board.

The five dTSEC can be routed to two on-board RGMII phy, three on-board
SGMII phy or four SGMII phy on SGMII riser card according to different
serdes protocol configuration and board lane configuration. Also updated
the device tree to direct the Fmac MAC to the correct PHY.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Roy Zang
fe1a1da038 powerpc/85xx: Add networking support to P1023RDS
The P1023 has two 1G ethernet controllers the first can run in
SGMII, RGMII, or RMII.  The second can only do SGMII & RGMII.

We need to setup a for SoC & board registers based on our various
configuration for ethernet to function properly on the board.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Timur Tabi
cba4614862 powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS &
P5020DS ("Hydra").

The lane_to_slot[] array is initialized dynamically, since board switches
can be used to control the muxing of SERDES lanes to slots.

The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate
slot.  The SERDES configuration is queried to help determine the routing
between MACs and slot/phy combination.

If a XAUI card is inserted, muxing for that card is enabled and never
turned off.  The PHY address for the 10G XAUI card depends on the slot in
which it's inserted.  If it's in slot 1, the address is 4.  If it's in
slot 2, the address is 0.

Update the MDIO routing in the P3041DS and P5020DS device trees based on
the board-level muxing.  The SERDES configuration determines which
SGMII/XGMII boards are located in which slots, and so the MDIO bus needs
to be muxed correctly whenever talking to a PHY connected to any Fman MAC.
The Fman Ethernet nodes in the device tree also need to be routed to the
correct PHYs.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.

Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Andy Fleming
2915609a91 powerpc/85xx: Add FMan ethernet support to P4080DS
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS.

The board supports add-on cards for SGMII and XAUI functionality.  Which
slots on the board these cards are in is a function of the SERDES option
selected and muxes on the board.

Additionally because of the high-configurablity which MDIO bus one is
connected to is "selected" via an FPGA register.  We create dummy MDIO
bus for the phy layer and hide the mux manipulation in this dummy layer.

Add fman fdt helper function in board common code it'll be used by several
freescale boards that do various muxing of the MDIO signals based on which
controller/interface one is trying to talk to.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Zhao Chenhui
44d737111b powerpc/mpc8548cds: Cleanup mpc8548cds.c
Remove unnecessary or dead code/includes.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Kumar Gala
86df5142a1 powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Poonam Aggrwal
49249e137d powerpc/85xx: Add basic support for P1010RDB
Boot methods supported: NOR Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash.

P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
	32Mbyte 16bit NOR flash
	32Mbyte SLC NAND Flash
	64KB CPLD device(GPCM interface)
SPI Flash:
	128 Mbit SPI Flash memory
SD/MMC:
	connector to interface with the SD memory card
SATA:
	1 internal SATA connect to 2.5. 160G SATA2 HDD
	1 eSATA connector to rear panel
USB 2.0:
	x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
	x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC:
	eTSEC1: Connected to RGMII PHY VSC8641XKO
	eTSEC2: Connected to SGMII PHY VSC8221
	eTSEC3: Connected to SGMII PHY VSC8221
eCAN:
	Two DB-9 female connectors for Field bus interface
UART:
	supports two UARTs up to 115200 bps for console
TDM:
	2 FXS ports connected via an external SLIC to the TDM interface.
SLIC:
	SPI SLIC
I2C:
	Serial EEprom
	Real time clock
	256 Kbit M24256 I2C EEPROM
PCIe:
	PCIe and mPCIe connectors.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Li Yang
14aa71e660 powerpc/85xx: Add support for new P102x/P2020 RDB style boards
The following boards share a common design but with minor variations
between them:

P1020MSBG-PC
P1020RDB-PC
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC

The P1020RDB-PC shares its roots in the existing P1020RDB board design,
however uses DDR3 instead of DDR2.
P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK.

Key features on these boards include:
* DDR3
* NOR flash
* NAND flash (on RDB's only)
* SPI flash (on RDB's only)
* SDHC/MMC card slot
* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
* PCIE slot and mini-PCIE slots

As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported
with this approach. ODT option is forced to fit this set of boards, again
because they don't have regular DIMMs.

CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet
specification for writing timing.

VSC firmware Address is defined by default in config file for eTSEC1.

SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.

Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC
have pins multiplexing. QE function needs to be disabled to access Nor Flash
and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below

'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b26998@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
2011-09-29 19:01:04 -05:00
Zhao Chenhui
d5c784ed53 powerpc/mpc8610hpcd: set pci1_hose.config_table after fsl_setup_hose
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-09 08:58:11 -05:00
Zhao Chenhui
b813cbe916 powerpc/mpc8548cds: set pci1_hose.config_table after fsl_setup_hose
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-09 08:58:11 -05:00
Zhao Chenhui
b092072e47 powerpc/mpc8568mds: set pci1_hose.config_table after fsl_setup_hose
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-09 08:58:10 -05:00
Stefano Babic
a4814a69d3 Makefile : fix generation of cpu related asm-offsets.h
commit 0edf8b5b2f breaks
building on a different directory with the O= parameter.
The patch wil fix this issue, generating always asm-offsets.h before
the other targets.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Wolfgang Denk <wd@denx.de>
2011-09-07 21:41:27 +02:00
Wolfgang Denk
684cad5717 Merge branch 'master' of git://git.denx.de/u-boot-coldfire
* 'master' of git://git.denx.de/u-boot-coldfire:
  ColdFire:Clean up the CONFIG_STANDALONE_LOAD_ADDR usage
  ColdFire:Add mb for 5253 dram initialization
  ColdFire:Define the DM9000 byteswap for M5253 board.
  ColdFire:Update the env settings for several boards.
  ColdFire:disable the NFS define for 52277 board.
  ColdFire:Update the timer_init since it was unified.
  ColdFire: Cleanup for partial linking and --gc-sections
  ColdFire: Update compile flags for each CPUs
  ColdFire:Fix the configuration broken for some boards.
2011-09-04 22:53:04 +02:00
Jason Jin
6752da6b26 ColdFire:Add mb for 5253 dram initialization
The dram initialization sequence should be in order.
This patch add mb for the dram intialization code to make
sure the compiler do not disorder the code.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2011-09-04 22:46:55 +08:00
Jason Jin
6c0bf27d74 ColdFire: Cleanup for partial linking and --gc-sections
Introduce the --gc-sections for ColdFire platform and clean up the
corresponding lds file.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2011-09-04 22:46:55 +08:00
Stefano Babic
753fc2ebf9 MX5: mx51evk: make use of GPIO framework
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-09-04 11:36:12 +02:00
Stefano Babic
a4adedd439 MX35: mx35pdk: make use of GPIO framework
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-09-04 11:36:12 +02:00
Stefano Babic
50410078cd MX5: mx53loco: make use of GPIO framework
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
2011-09-04 11:36:12 +02:00
Stefano Babic
f7a364745e MX5: mx53evk: make use of GPIO framework
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
2011-09-04 11:36:12 +02:00
Stefano Babic
04e25fd629 MX5: mx53smd: make use of GPIO framework
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-04 11:36:12 +02:00
Stefano Babic
00c07fe692 MX5: mx53ard: make use of GPIO framework
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-04 11:36:12 +02:00
Stefano Babic
6b5acfc121 MX35: MX35PDK: support additional RAM on CSD1
Modules on mx35pdk have additional 128MB
memory connected to CSD1.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-09-04 11:36:11 +02:00
Fabio Estevam
9691c5b96d mx53: ddr3: Update DD3 initialization
Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from
"0x092080b0". This changes write recovery from 8 clocks to 6 clocks
(in line with ESDCFG1[tWR])

Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-04 11:36:11 +02:00
Timur Tabi
3b4a226305 video: Add SHARP LQ084S3LG01 LCD support on P1022DS
The SHARP LQ084S3LG01 is a TFT LCD used on the P1022DS (revision "C") board.
This device only supports 800x600 resolution, so if that resolution is selected,
assume that this is the device.  The device is attached to the LVDS port
on the P1022DS board.

The existing 800x600 entry (for the PDM360NG board) is actually 800x480,
so we fix that.  To support two different 800x resolutions, the Y-resolution
is now passed to fsl_diu_init() and both values are used to pick the proper
fb_videomode structure.

The data for the 800x600 video mode is originally from Jiang Yutang.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
2011-08-04 22:55:33 +02:00
Shaohui Xie
a3a3e7b2c3 powerpc/85xx: enable USB2 gadget mode for corenet ds board
to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to
'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break
out if it cannot find 'usb1', so drop the 'else' clause to make driver scan
all the 'usbx'.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:43 -05:00
Wolfgang Denk
21cd5815a7 MPC8xxx: drop redundant boot messages
Current code would print RAM size information like this:

	DRAM:  DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off)

Turn a number of printf()s into debug() to get rid of the redundant
"DDR: " string like this:

	DRAM:  256 MiB (DDR1, 64-bit, CL=2, ECC off)

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:39 -05:00
Stephen George
f110fe940c powerpc/85xx: Adding configuration for DCSRCR to enable 32M access
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Most DCSR registers are within 4M but the Nexus trace buffer
is located at offset 16M within the DCSR.

Configuring the LAW to be 32M to allow access to the Nexus
trace buffer. No TLB modification is required since accessing
the Nexus trace buffer from within u-boot is not required.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:37 -05:00
Mike Williams
1626308797 cleanup: Fix typos and misspellings in various files.
Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address

Signed-off-by: Mike Williams <mike@mikebwilliams.com>
2011-07-28 21:27:36 +02:00
Wolfgang Denk
cdf1a2328a Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  ARM: MX5: Fix broken leftover TO-2 errata workaround
  MX31: Cleanup clock function
  scb9328: Add ARM relocation support
  am3517evm: change console device from ttyS2 to ttyO2
  Remove volatile qualifier in get_ram_size() calls
  TI: TNETV107X Fix Build Error
  ARM: add missing CONFIG_SKIP_LOWLEVEL_INIT for armv7
  arm: add CONFIG_MACH_TYPE setting and documentation
  arm: add __ilog2 function
  Timer: Fix misuse of ARM *timer_masked() functions outside arch/arm
  EfikaMX: Enable EXT2 booting
  EfikaMX: Add missing CONFIG_SYS_TEXT_BASE
  EfikaMX: Use correct imximage.cfg
  MX27: Update to autogenerated asm-offsets.h
  MX5: Update to autogenerated asm-offsets.h
  imx: Add support for zmx25 board
  imx: Make imx25 compatible to mxc_gpio driver and fix in tx25
  imx: Add auto generation of asm-offsets.h for imx25
  imx: Add support for USB EHCI on imx25
  imx: Use correct imx25 reset.c
  imx: Add get_tbclk() function for imx25
  ARM: Update maintainer of board scb9328
  mx27: Make the UART port number explicit
  build: Add targets for auto gen of asm-offsets.h and use it in imx35
  mx31pdk: cosmetic: Fix line over 80 characters
2011-07-18 21:04:56 +02:00
Mingkai Hu
4f1d1b7d1e powerpc/p2041rdb: Add p2041rdb board support
P2041RDB Specification:
-----------------------
Memory subsystem:
 * 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 256 Kbit M24256 I2C EEPROM
 * 16 Mbyte SPI memory
 * SD connector to interface with the SD memory card

Ethernet:
 * dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
 * dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
 * dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
 * dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
 * dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)

PCIe:
 * Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
 * Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2

SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors

USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces

I2C:
 * I2C1: Real time clock, Temperature sensor, Memory module
 * I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-17 11:03:36 -05:00
Albert ARIBAUD
a55d23ccf6 Remove volatile qualifier in get_ram_size() calls
Checkpatch.pl complains about the volatile qualifier in calls to
get_ram_size(). Remove this qualifier in the prototype and in the
calls where it is useless, and leave it only in the function body
where it is needed.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2011-07-17 17:11:53 +02:00
Ramneek Mehresh
86dda50484 qoriq/p1_p2_rdb: USB device-tree fixups for P1020
Resolve P1020 second USB controller multiplexing with eLBC
	- mandatory to mention USB2 in hwconfig string to select it
	  over eLBC, otherwise USB2 node is removed
	- works only for SPI and SD boot

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
Roy Zang
3f7f6b8592 powerpc/85xx: Add basic support for P1023RDS board
The P1023RDS board is the reference board for the P1023 SoC.

Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe,
UART, I2C, etc.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
York Sun
939e5bf9b3 powerpc/mpc85xx: Display a warning for unsupported DDR data rates
If DDR initialziation uses a speed table and the speed is not matched,
print a warning message instead of silently ignoring.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
York Sun
79fa00af5d powerpc/corenet_ds: Fix RCW overriding for RDIMM
Allow overriding RCW for all RDIMM, not only quad-rank ones.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
Timur Tabi
26fd33b9be powerpc/86xx: display boot device and bank on the MPC8610 HPCD
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Kumar Gala
58b2f96e38 powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't set
Add ifdef protection for qp_info and liodn associated with Q/BMan.  Also
rearrange setting of _tbl_sz variables to utilize existing ifdef
protection for things like FMAN.

Also add protection around setup_portals() call in corenet_ds board
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Kumar Gala
be1ff615ea powerpc/85xx: Fix compile errors if CONFIG_SYS_{B,Q}MAN_MEM_PHYS aren't set
Add ifdef protection in LAW & TLB code to handle the case in which
CONFIG_SYS_BMAN_MEM_PHYS or CONFIG_SYS_QMAN_MEM_PHYS arent defined for a
build.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Timur Tabi
f5f30dea2a powerpc/83xx: remove empty board_early_init_f()
Remove an empty board_early_init_f() from the MPC8323ERD and MPC360ERDK boards.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2011-07-06 19:09:28 -05:00
Fabio Estevam
47c3e074ad MX53: Add initial support for MX53ARD
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04 10:55:26 +02:00
Timur Tabi
29b83d9833 powerpc/p1022ds: set the clock-frequency prop only if the clock is enabled
The clock-frequency property in an audio codec's device tree node is set to
the input clock frequency for that codec.  On the Freescale P1022DS board,
the input clock is enabled only if the hwconfig 'audclk' option is set.
Therefore, the property should only be set in the device tree if the clock
is actually enabled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-06-09 15:53:38 -05:00
Fabio Estevam
4ac2e2d69f mx31ads: Use the new relocation scheme
This fixes the MX31ADS build by using the new relocation scheme.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Felix Radensky <felix@embedded-sol.com>
2011-06-06 09:35:25 +02:00
Jason Liu
5195890440 mx5: board: code clean up for checkboard code
The boot cause code has been factor out to soc common
code,we need drop the part from the board support code

This patch also remove the redundant cpu version print

Signed-off-by: Jason Liu <jason.hui@linaro.org>
2011-05-23 08:36:46 +02:00
Fabio Estevam
860b32ee50 MX53: Add initial support for MX53SMD board.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-05-23 08:36:46 +02:00
Jason Liu
938080dc4b MX53: support for freescale MX53LOCO board
This patch add initial support for freescale MX53LOCO board.
Network(FEC),SD/MMC,UART have been supported by this patch

Signed-off-by: Jason Liu <jason.hui@linaro.org>
2011-05-23 08:36:46 +02:00
Wolfgang Denk
cd6881b519 Minor coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-05-19 22:22:44 +02:00
Shaohui Xie
be827c7ab0 powerpc/85xx: add support for env in MMC/SPI on corenet ds boards
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-05-18 09:15:25 -05:00
Fabio Estevam
b73850f764 MX31: mx31pdk: Add watchdog support
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-05-11 23:03:15 +02:00
Wolfgang Denk
aeabdeb7a3 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2011-04-30 22:45:55 +02:00