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mx35pdk: Add support for OTG

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Add support for the OTG port on the mx35pdk Personality board.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
This commit is contained in:
Benoît Thébaudeau 2012-11-13 09:58:25 +00:00 committed by Stefano Babic
parent 71a5c55bfa
commit 961a762838
3 changed files with 39 additions and 0 deletions
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4
board/freescale/mx35pdk/lowlevel_init.S
View file

@ -94,6 +94,10 @@
orr r1, r1, #0x00000C00
orr r1, r1, #0x00000003
str r1, [r0, #CLKCTL_CGR1]
ldr r1, [r0, #CLKCTL_CGR2]
orr r1, r1, #0x00C00000
str r1, [r0, #CLKCTL_CGR2]
.endm
.macro setup_sdram

21
board/freescale/mx35pdk/mx35pdk.c
View file

@ -98,6 +98,26 @@ static void setup_iomux_spi(void)
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
}
static void setup_iomux_usbotg(void)
{
int in_pad, out_pad;
/* Set up pins for USBOTG. */
mxc_request_iomux(MX35_PIN_USBOTG_PWR,
MUX_CONFIG_SION | MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_USBOTG_OC,
MUX_CONFIG_SION | MUX_CONFIG_FUNC);
in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
}
static void setup_iomux_fec(void)
{
int pad;
@ -189,6 +209,7 @@ int board_early_init_f(void)
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
setup_iomux_i2c();
setup_iomux_usbotg();
setup_iomux_fec();
setup_iomux_spi();

14
include/configs/mx35pdk.h
View file

@ -112,6 +112,8 @@
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_CMD_DATE
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
@ -244,6 +246,18 @@
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
/* EHCI driver */
#define CONFIG_USB_EHCI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_MXC
#define CONFIG_MXC_USB_PORT 0
#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
MXC_EHCI_POWER_PINS_ENABLED | \
MXC_EHCI_OC_PIN_ACTIVE_LOW)
#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC