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ARMv8/ls2085a: Enable secondary cores

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Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.

Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
This commit is contained in:
York Sun 2014-09-08 12:20:01 -07:00
parent 40f8dec54d
commit 8bfa301b0a
2 changed files with 8 additions and 3 deletions
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2
board/freescale/ls2085a/ls2085a.c
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@ -105,6 +105,8 @@ void ft_board_setup(void *blob, bd_t *bd)
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
/* limit the memory size to bank 1 until Linux can handle 40-bit PA */
base = getenv_bootm_low();
size = getenv_bootm_size();

9
include/configs/ls2085a_common.h
View file

@ -47,15 +47,17 @@
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
/* SMP Definitions */
#define CPU_RELEASE_ADDR CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
/*
* SMP Definitinos
*/
#define CPU_RELEASE_ADDR secondary_boot_func
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
/*
@ -241,6 +243,7 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_ARCH_EARLY_INIT_R
/* Physical Memory Map */
/* fixme: these need to be checked against the board */