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mx6sabred: Add PFUZE100 PMIC support
mx6sabresd boards have a PFUZE100 PMIC connected to I2C2 bus. Add support for it Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
186feb0b4d
commit
66ca09fc41
3 changed files with 100 additions and 0 deletions
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@ -12,6 +12,7 @@
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#include <asm/arch/mx6-pins.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/video.h>
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@ -23,6 +24,9 @@
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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@ -39,6 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define I2C_PMIC 1
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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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@ -129,6 +141,19 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
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MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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static void setup_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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@ -426,6 +451,64 @@ int board_init(void)
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#ifdef CONFIG_MXC_SPI
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setup_spi();
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#endif
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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return 0;
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}
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static int pfuze_init(void)
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{
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struct pmic *p;
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int ret;
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unsigned int reg;
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ret = power_pfuze100_init(I2C_PMIC);
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if (ret)
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return ret;
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p = pmic_get("PFUZE100_PMIC");
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ret = pmic_probe(p);
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if (ret)
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return ret;
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pmic_reg_read(p, PFUZE100_DEVICEID, ®);
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printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
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/* Increase VGEN3 from 2.5 to 2.8V */
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pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
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reg &= ~0xf;
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reg |= 0xa;
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pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
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/* Increase VGEN5 from 2.8 to 3V */
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pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
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reg &= ~0xf;
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reg |= 0xc;
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pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
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/* Set SW1AB stanby volage to 0.975V */
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pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
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reg &= ~0x3f;
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reg |= 0x1b;
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pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
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/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
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pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
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reg &= ~0xc0;
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reg |= 0x40;
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pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
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/* Set SW1C standby voltage to 0.975V */
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pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
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reg &= ~0x3f;
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reg |= 0x1b;
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pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
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/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
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pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
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reg &= ~0xc0;
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reg |= 0x40;
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pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
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return 0;
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}
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@ -446,6 +529,7 @@ int board_late_init(void)
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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pfuze_init();
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return 0;
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}
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@ -59,4 +59,16 @@
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#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
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#endif
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/* I2C Configs */
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_SPEED 100000
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/* PMIC */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PFUZE100
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#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
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#endif /* __MX6QSABRESD_CONFIG_H */
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@ -15,7 +15,11 @@ enum {
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PFUZE100_FABID = 0x04,
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PFUZE100_SW1ABVOL = 0x20,
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PFUZE100_SW1ABSTBY = 0x21,
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PUZE_100_SW1ABCONF = 0x24,
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PFUZE100_SW1CVOL = 0x2e,
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PFUZE100_SW1CSTBY = 0x2f,
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PFUZE100_SW1CCONF = 0x32,
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PFUZE100_SW2VOL = 0x35,
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PFUZE100_SW3AVOL = 0x3c,
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PFUZE100_SW3BVOL = 0x43,
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