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t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdm

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qe-tdm is muxed with diu, if hwconfig setted as qe-tdm,
assign muxed pins to qe-tdm, then delete diu node from
device tree.

Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Zhao Qiang 2015-08-28 10:31:50 +08:00 committed by York Sun
parent a61047370d
commit d468377672
4 changed files with 33 additions and 0 deletions
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11
arch/powerpc/cpu/mpc85xx/fdt.c
View file

@ -13,6 +13,7 @@
#include <asm/processor.h>
#include <linux/ctype.h>
#include <asm/io.h>
#include <asm/fsl_fdt.h>
#include <asm/fsl_portals.h>
#include <hwconfig.h>
#ifdef CONFIG_FSL_ESDHC
@ -943,3 +944,13 @@ int ft_verify_fdt(void *fdt)
return 1;
}
void fdt_del_diu(void *blob)
{
int nodeoff = 0;
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
"fsl,diu")) >= 0) {
fdt_del_node(blob, nodeoff);
}
}

11
arch/powerpc/include/asm/fsl_fdt.h Normal file
View file

@ -0,0 +1,11 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _FSL_FDT_H_
#define _FSL_FDT_H_
void fdt_del_diu(void *blob);
#endif

1
board/freescale/t104xrdb/cpld.h
View file

@ -44,3 +44,4 @@ void cpld_write(unsigned int reg, u8 value);
cpld_write(offsetof(struct cpld_data, reg), value)
#define MISC_CTL_SG_SEL 0x80
#define MISC_CTL_AURORA_SEL 0x02
#define MISC_MUX_QE_TDM 0xc0

10
board/freescale/t104xrdb/t104xrdb.c
View file

@ -6,12 +6,14 @@
#include <common.h>
#include <command.h>
#include <hwconfig.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_fdt.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
@ -110,6 +112,12 @@ int misc_init_r(void)
MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
#if defined(CONFIG_T1040D4RDB)
if (hwconfig("qe-tdm")) {
CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
MISC_MUX_QE_TDM);
printf("QECSR : 0x%02x, mux to qe-tdm\n",
CPLD_READ(sfp_ctl_status));
}
/* Mask all CPLD interrupt sources, except QSGMII interrupts */
if (CPLD_READ(sw_ver) < 0x03) {
debug("CPLD SW version 0x%02x doesn't support int_mask\n",
@ -149,5 +157,7 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
#endif
if (hwconfig("qe-tdm"))
fdt_del_diu(blob);
return 0;
}