mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 22:20:45 +00:00
nand_spl: remove P1023RDS_NAND support
Commit 3d5a335c announced that all the nand_spl boards
would be removed before v2014.07 release.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
ba8dd7755e
commit
26bf6d77a6
6 changed files with 1 additions and 236 deletions
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@ -182,11 +182,6 @@ void ft_board_setup(void *blob, bd_t *bd)
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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/* By default NOR is on, and NAND is disabled */
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#ifdef CONFIG_NAND_U_BOOT
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do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
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do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
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#endif
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#ifdef CONFIG_HAS_FSL_DR_USB
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fdt_fixup_dr_usb(blob, bd);
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#endif
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@ -36,7 +36,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_4M, 1),
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#ifndef CONFIG_NAND_SPL
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/* *W*G* - BCSR and NOR flash on local bus*/
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/* This will be changed to *I*G* after relocation to RAM. */
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SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
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@ -79,7 +78,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
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CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 10, BOOKE_PAGESZ_1M, 1),
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#endif
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/* *I*G - NAND */
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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@ -833,7 +833,6 @@ Active powerpc mpc85xx - freescale p1022ds
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Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
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Active powerpc mpc85xx - freescale p1023rdb P1023RDB - -
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Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com>
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Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com>
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Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
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Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
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Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -
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@ -14,23 +14,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_NAND
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#define CONFIG_NAND_U_BOOT
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#define CONFIG_RAMBOOT_NAND
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#endif
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#ifdef CONFIG_NAND_U_BOOT
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#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
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#else
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#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif /* CONFIG_NAND_SPL */
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff40000
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#endif
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@ -162,7 +145,6 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
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#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
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#ifndef CONFIG_NAND
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#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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@ -179,11 +161,8 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#else
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#define CONFIG_SYS_NO_FLASH
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#endif
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#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
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#if defined(CONFIG_SYS_SPL)
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#define CONFIG_SYS_RAMBOOT
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#endif
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@ -239,17 +218,6 @@ extern unsigned long get_clock_freq(void);
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#ifdef CONFIG_RAMBOOT_NAND
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/* NAND Base Address */
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#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
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#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
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/* chip select 1 - BCSR */
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#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
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| BR_MS_GPCM | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
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| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
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| OR_GPCM_EAD)
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#else
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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/* chip select 1 - BCSR */
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@ -258,7 +226,6 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
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| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
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| OR_GPCM_EAD)
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#endif
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/* Serial Port
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* open - index 2
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@ -381,15 +348,9 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_SYS_RAMBOOT)
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#if defined(CONFIG_RAMBOOT_NAND)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
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#else
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#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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@ -496,15 +457,10 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_PHY_MARVELL
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#endif
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#ifndef CONFIG_NAND
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/* Default address of microcode for the Linux Fman driver */
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/* QE microcode/firmware address */
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
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#else
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#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000
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#endif
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
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@ -1,87 +0,0 @@
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#
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# Copyright 2010-2011 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PAD_TO := 0xfff01000
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nandobj := $(objtree)/nand_spl/
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LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
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LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
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$(LDFLAGS) $(LDFLAGS_FINAL)
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asflags-y += -DCONFIG_NAND_SPL
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ccflags-y += -DCONFIG_NAND_SPL
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SOBJS = start.o resetvec.o
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COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
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nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
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OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(nandobj)board/$(BOARDDIR)
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targets += $(__OBJS)
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all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
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$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
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-Map $(nandobj)u-boot-spl.map -o $@
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$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
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$(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
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-ansi -D__ASSEMBLY__ -P - <$< >$@
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# create symbolic links for common files
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$(obj)/cache.c:
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@rm -f $@
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ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
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$(obj)/cpu_init_early.c:
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@rm -f $@
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ln -sf $(srctree)/$(CPUDIR)/cpu_init_early.c $@
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$(obj)/spl_minimal.c:
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@rm -f $@
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ln -sf $(srctree)/$(CPUDIR)/spl_minimal.c $@
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$(obj)/fsl_law.c:
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@rm -f $@
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ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
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$(obj)/law.c:
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@rm -f $@
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ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
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$(obj)/nand_boot_fsl_elbc.c:
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@rm -f $@
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ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
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$(obj)/ns16550.c:
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@rm -f $@
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ln -sf $(srctree)/drivers/serial/ns16550.c $@
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$(obj)/resetvec.S:
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@rm -f $@
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ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
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$(obj)/start.S:
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@rm -f $@
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ln -sf $(srctree)/$(CPUDIR)/start.S $@
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$(obj)/tlb.c:
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@rm -f $@
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ln -sf $(srctree)/$(CPUDIR)/tlb.c $@
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$(obj)/tlb_table.c:
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@rm -f $@
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ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
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@ -1,96 +0,0 @@
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Author: Roy Zang <tie-fei.zang@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <asm/fsl_law.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Fixed sdram init -- doesn't use serial presence detect. */
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void sdram_init(void)
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{
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struct ccsr_ddr __iomem *ddr =
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(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
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set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
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__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
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__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
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__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
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__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
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__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
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__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
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__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
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__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
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__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
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__raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
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__raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
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__raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
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/* Set, but do not enable the memory */
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__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
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asm volatile("sync;isync");
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udelay(500);
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/* Let the controller go */
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out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* initialize selected port with appropriate baud rate */
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio >>= 1;
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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gd->bus_clk / 16 / CONFIG_BAUDRATE);
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puts("\nNAND boot... ");
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/* Initialize the DDR3 */
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sdram_init();
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
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CONFIG_SYS_NAND_U_BOOT_RELOC);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (c == '\n')
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
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}
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void puts(const char *str)
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{
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while (*str)
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putc(*str++);
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}
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