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armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY

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To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Shaohui Xie 2016-01-28 15:38:15 +08:00 committed by York Sun
parent 2b690b9837
commit abc7d0f75c
3 changed files with 9 additions and 0 deletions
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4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View file

@ -98,6 +98,10 @@
#define DCFG_DCSR_BASE 0X700100000ULL
#define DCFG_DCSR_PORCR1 0x000
/* Interrupt Sampling Control */
#define ISC_BASE 0x01F70000
#define IRQCR_OFFSET 0x14
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000

4
board/freescale/ls2080ardb/ls2080ardb.c
View file

@ -149,6 +149,7 @@ int board_init(void)
{
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
u32 val;
init_final_memctl_regs();
@ -170,6 +171,9 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
return 0;
}

1
include/configs/ls2080ardb.h
View file

@ -355,6 +355,7 @@ unsigned long get_board_sys_clk(void);
#define AQ_PHY_ADDR2 0x01
#define AQ_PHY_ADDR3 0x02
#define AQ_PHY_ADDR4 0x03
#define AQR405_IRQ_MASK 0x36
#define CONFIG_MII
#define CONFIG_ETHPRIME "DPNI1"