mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
parent
a6bbee6619
commit
5f98d0b5d3
3 changed files with 16 additions and 3 deletions
|
@ -323,7 +323,7 @@ static u32 get_mmdc_ch0_clk(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int enable_fec_anatop_clock(void)
|
||||
int enable_fec_anatop_clock(enum enet_freq freq)
|
||||
{
|
||||
u32 reg = 0;
|
||||
s32 timeout = 100000;
|
||||
|
@ -331,7 +331,13 @@ int enable_fec_anatop_clock(void)
|
|||
struct anatop_regs __iomem *anatop =
|
||||
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
|
||||
|
||||
if (freq < ENET_25MHz || freq > ENET_125MHz)
|
||||
return -EINVAL;
|
||||
|
||||
reg = readl(&anatop->pll_enet);
|
||||
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
|
||||
reg |= freq;
|
||||
|
||||
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
|
||||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
|
||||
reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
|
||||
|
|
|
@ -42,6 +42,13 @@ enum mxc_clock {
|
|||
MXC_I2C_CLK,
|
||||
};
|
||||
|
||||
enum enet_freq {
|
||||
ENET_25MHz,
|
||||
ENET_50MHz,
|
||||
ENET_100MHz,
|
||||
ENET_125MHz,
|
||||
};
|
||||
|
||||
u32 imx_get_uartclk(void);
|
||||
u32 imx_get_fecclk(void);
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
@ -50,5 +57,5 @@ void enable_usboh3_clk(unsigned char enable);
|
|||
int enable_sata_clock(void);
|
||||
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
|
||||
void enable_ipu_clock(void);
|
||||
int enable_fec_anatop_clock(void);
|
||||
int enable_fec_anatop_clock(enum enet_freq freq);
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
|
|
|
@ -120,7 +120,7 @@ static int setup_fec(void)
|
|||
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
|
||||
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
|
||||
|
||||
ret = enable_fec_anatop_clock();
|
||||
ret = enable_fec_anatop_clock(ENET_50MHz);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
Loading…
Reference in a new issue