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https://github.com/AsahiLinux/u-boot
synced 2024-11-24 13:43:28 +00:00
powerpc/t1023rdb: add support for T1023RDB RevC
Add support for NOR flash and GPIO/I2C switch control on RevC. - NOR support - bank0/bank4 switch - SD/eMMC switch - board version Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shengzhou Liu
York Sun
parent
5050f6f0e5
commit
ff7ea2d18b
5 changed files with 123 additions and 56 deletions
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@ -70,6 +70,7 @@ Deep Sleep: yes no
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I2C controller: 4 3
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DDR: 64-bit 32-bit
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IFC: 32-bit 28-bit
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Package: 23x23 19x19
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T1024RDB board Overview
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@ -192,7 +193,7 @@ Software configurations and board settings
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on T1024RDB:
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set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
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on T1023RDB:
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set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot
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set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
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Switching between default bank0 and alternate bank4 on NOR flash
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To change boot source to vbank4:
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@ -200,7 +201,7 @@ Software configurations and board settings
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via software: run command 'cpld reset altbank' in u-boot.
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via DIP-switch: set SW3[5:7] = '100'
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on T1023RDB:
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via software: run command 'gpio vbank4' in u-boot.
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via software: run command 'switch bank4' in u-boot.
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via DIP-switch: set SW3[5:7] = '100'
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To change boot source to vbank0:
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@ -208,7 +209,7 @@ Software configurations and board settings
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via software: run command 'cpld reset' in u-boot.
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via DIP-Switch: set SW3[5:7] = '000'
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on T1023RDB:
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via software: run command 'gpio vbank0' in u-boot.
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via software: run command 'switch bank0' in u-boot.
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via DIP-switch: set SW3[5:7] = '000'
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2. NAND Boot:
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@ -219,7 +220,7 @@ Software configurations and board settings
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> nand erase 0 $filesize
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=> nand write 1000000 0 $filesize
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set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot
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set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
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3. SPI Boot:
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a. build PBL image for SPI boot
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@ -241,11 +242,14 @@ Software configurations and board settings
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$ make
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b. program u-boot-with-spl-pbl.bin to SD/MMC card
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> mmc write 1000000 8 0x800
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=> mmc write 1000000 8 0x7f0
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=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
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=> mmc write 1000000 0x820 80
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set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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SW3[3] = '1' for SD card(or 'switch sd' by software)
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SW3[3] = '0' for eMMC (or 'switch emmc' by software)
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2-stage NAND/SPI/SD boot loader
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-------------------------------
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@ -292,7 +296,7 @@ Start End Definition Size
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0x160000 0x17FFFF FMAN Ucode 128KB
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SD Card memory Map on T1024RDB
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SD Card memory Map on T102xRDB
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----------------------------------------------------
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Block #blocks Definition Size
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0x008 2048 u-boot img 1MB
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@ -313,5 +317,5 @@ Start End Definition Size
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0xa00000 0x3FFFFFF rootfs 54MB
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For more details, please refer to T1024RDB Reference Manual
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For more details, please refer to T1024RDB/T1023RDB User Guide
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and Freescale QorIQ SDK Infocenter document.
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@ -4,5 +4,5 @@ aa55aa55 010e0100
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#Core/DDR: 1400Mhz/1600MT/s with single source clock
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0810000e 00000000 00000000 00000000
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3b800003 00000012 e8104000 21000000
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00000000 00000000 00000000 00020800
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00000000 00000000 00000000 00022800
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00000130 04020200 00000000 00000006
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@ -20,6 +20,9 @@
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#include "t102xrdb.h"
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#ifdef CONFIG_T1024RDB
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#include "cpld.h"
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#elif defined(CONFIG_T1023RDB)
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#include <i2c.h>
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#include <mmc.h>
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#endif
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#include "../common/sleep.h"
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@ -27,13 +30,14 @@ DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_T1023RDB
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enum {
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GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */
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GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
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GPIO1_EMMC_SEL,
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GPIO1_VBANK0,
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GPIO1_VBANK4 = 0x00008000, /* GPIO1_16/20/22, 100:vBank4 */
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GPIO1_VBANK_MASK = 0x00008a00,
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GPIO1_DIR_OUTPUT = 0x00028a00,
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GPIO1_GET_VAL,
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GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
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GPIO3_BRD_VER_MASK = 0x0c000000,
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GPIO3_OFFSET = 0x2000,
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I2C_GET_BANK,
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I2C_SET_BANK0,
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I2C_SET_BANK4,
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};
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#endif
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@ -48,9 +52,11 @@ int checkboard(void)
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srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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printf("Board: %sRDB, ", cpu->name);
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#ifdef CONFIG_T1024RDB
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#if defined(CONFIG_T1024RDB)
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printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
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CPLD_READ(hw_ver), CPLD_READ(sw_ver));
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#elif defined(CONFIG_T1023RDB)
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printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
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#endif
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printf("boot from ");
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@ -73,8 +79,7 @@ int checkboard(void)
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#ifdef CONFIG_NAND
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puts("NAND\n");
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#else
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printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) &
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GPIO1_VBANK4) >> 15 ? 4 : 0);
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printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
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#endif
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#endif
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@ -196,64 +201,126 @@ int ft_board_setup(void *blob, bd_t *bd)
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fdt_fixup_board_enet(blob);
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#endif
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#ifdef CONFIG_T1023RDB
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if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
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fdt_enable_nor(blob);
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#endif
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return 0;
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}
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#ifdef CONFIG_T1023RDB
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static u32 t1023rdb_gpio_ctrl(u32 ctrl_type)
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/* Enable NOR flash for RevC */
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static void fdt_enable_nor(void *blob)
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{
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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u32 gpioval;
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int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
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setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT);
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gpioval = in_be32(&pgpio->gpdat);
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if (nodeoff >= 0)
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fdt_status_okay(blob, nodeoff);
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else
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printf("WARNING unable to set status for NOR\n");
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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u32 val = in_be32(&pgpio->gpdat);
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/* GPIO1_14, 0: eMMC, 1: SD/MMC */
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val &= GPIO1_SD_SEL;
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return val ? -1 : 1;
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}
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int board_mmc_getwp(struct mmc *mmc)
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{
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ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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u32 val = in_be32(&pgpio->gpdat);
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val &= GPIO1_SD_SEL;
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return val ? -1 : 0;
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}
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static u32 t1023rdb_ctrl(u32 ctrl_type)
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{
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ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 val, orig_bus = i2c_get_bus_num();
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u8 tmp;
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switch (ctrl_type) {
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case GPIO1_SD_SEL:
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gpioval |= GPIO1_SD_SEL;
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val = in_be32(&pgpio->gpdat);
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val |= GPIO1_SD_SEL;
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out_be32(&pgpio->gpdat, val);
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setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
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break;
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case GPIO1_EMMC_SEL:
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gpioval &= ~GPIO1_SD_SEL;
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val = in_be32(&pgpio->gpdat);
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val &= ~GPIO1_SD_SEL;
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out_be32(&pgpio->gpdat, val);
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setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
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break;
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case GPIO1_VBANK0:
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gpioval &= ~GPIO1_VBANK_MASK;
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case GPIO3_GET_VERSION:
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pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
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+ GPIO3_OFFSET);
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val = in_be32(&pgpio->gpdat);
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val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
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if (val == 0x3) /* GPIO3_4/5 not used on RevB */
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val = 0;
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return val;
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case I2C_GET_BANK:
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i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
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i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
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tmp &= 0x7;
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tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
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i2c_set_bus_num(orig_bus);
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return tmp;
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case I2C_SET_BANK0:
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i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
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tmp = 0x0;
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i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
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tmp = 0xf8;
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i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
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/* asserting HRESET_REQ */
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out_be32(&gur->rstcr, 0x2);
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break;
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case GPIO1_VBANK4:
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gpioval &= ~GPIO1_VBANK_MASK;
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gpioval |= GPIO1_VBANK4;
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case I2C_SET_BANK4:
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i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
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tmp = 0x1;
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i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
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tmp = 0xf8;
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i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
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out_be32(&gur->rstcr, 0x2);
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break;
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case GPIO1_GET_VAL:
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return gpioval;
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default:
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break;
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}
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out_be32(&pgpio->gpdat, gpioval);
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return 0;
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}
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static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
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static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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if (argc < 2)
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return CMD_RET_USAGE;
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if (!strcmp(argv[1], "vbank0"))
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t1023rdb_gpio_ctrl(GPIO1_VBANK0);
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else if (!strcmp(argv[1], "vbank4"))
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t1023rdb_gpio_ctrl(GPIO1_VBANK4);
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if (!strcmp(argv[1], "bank0"))
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t1023rdb_ctrl(I2C_SET_BANK0);
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else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
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t1023rdb_ctrl(I2C_SET_BANK4);
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else if (!strcmp(argv[1], "sd"))
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t1023rdb_gpio_ctrl(GPIO1_SD_SEL);
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else if (!strcmp(argv[1], "EMMC"))
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t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL);
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t1023rdb_ctrl(GPIO1_SD_SEL);
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else if (!strcmp(argv[1], "emmc"))
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t1023rdb_ctrl(GPIO1_EMMC_SEL);
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else
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return CMD_RET_USAGE;
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return 0;
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}
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U_BOOT_CMD(
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gpio, 2, 0, gpio_cmd,
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"for vbank0/vbank4/SD/eMMC switch control in runtime",
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"command (e.g. gpio vbank4)"
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switch, 2, 0, switch_cmd,
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"for bank0/bank4/sd/emmc switch control in runtime",
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"command (e.g. switch bank4)"
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);
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#endif
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@ -10,6 +10,7 @@
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void fdt_fixup_board_enet(void *blob);
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void pci_of_setup(void *blob, bd_t *bd);
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#ifdef CONFIG_T1023RDB
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static u32 t1023rdb_gpio_ctrl(u32 ctrl_type);
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static u32 t1023rdb_ctrl(u32 ctrl_type);
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static void fdt_enable_nor(void *blob);
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#endif
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#endif
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@ -11,12 +11,6 @@
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#ifndef __T1024RDB_H
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#define __T1024RDB_H
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#if defined(CONFIG_T1023RDB)
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#ifdef CONFIG_SPL
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#define CONFIG_SYS_NO_FLASH
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#endif
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#endif
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/* High Level Configuration Options */
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_DISPLAY_BOARDINFO
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@ -320,7 +314,7 @@ unsigned long get_board_ddr_clk(void);
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#if defined(CONFIG_T1024RDB)
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#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
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#elif defined(CONFIG_T1023RDB)
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#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
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CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
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#endif
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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@ -559,9 +553,8 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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#define I2C_MUX_PCA_ADDR 0x77
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
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#define I2C_PCA6408_BUS_NUM 1
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#define I2C_PCA6408_ADDR 0x20
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/* I2C bus multiplexer */
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#define I2C_MUX_CH_DEFAULT 0x8
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@ -759,8 +752,10 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_DPAA_FMAN
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#ifdef CONFIG_T1024RDB
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#define CONFIG_QE
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#define CONFIG_U_QE
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#endif
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/* Default address of microcode for the Linux FMan driver */
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#if defined(CONFIG_SPIFLASH)
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/*
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