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https://github.com/AsahiLinux/u-boot
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board/ls2085qds: Add support ethernet
Add support of ethernet: - eth.c: mapping lane to slot for (0x2A, 0x07) - ls2085a.c: To enable/disable dpmac and get link type Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Prabhakar Kushwaha
York Sun
parent
e2b65ea975
commit
e60476a01e
7 changed files with 488 additions and 13 deletions
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@ -6,3 +6,4 @@
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obj-y += ls2085aqds.o
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obj-y += ddr.o
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obj-y += eth.o
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380
board/freescale/ls2085aqds/eth.c
Normal file
380
board/freescale/ls2085aqds/eth.c
Normal file
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@ -0,0 +1,380 @@
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch-fsl-lsch3/immap_lsch3.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl-mc/ldpaa_wriop.h>
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#include "../common/qixis.h"
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#include "ls2085aqds_qixis.h"
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#ifdef CONFIG_FSL_MC_ENET
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/* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
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* Bank 1 -> Lanes A, B, C, D, E, F, G, H
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* Bank 2 -> Lanes A,B, C, D, E, F, G, H
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*/
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/* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
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* means that the mapping must be determined dynamically, or that the lane
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* maps to something other than a board slot.
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*/
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static u8 lane_to_slot_fsm2[] = {
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0, 0, 0, 0, 0, 0, 0, 0
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};
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/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
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* housed.
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*/
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static int riser_phy_addr[] = {
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SGMII_CARD_PORT1_PHY_ADDR,
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SGMII_CARD_PORT2_PHY_ADDR,
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SGMII_CARD_PORT3_PHY_ADDR,
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SGMII_CARD_PORT4_PHY_ADDR,
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};
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/* Slot2 does not have EMI connections */
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#define EMI_NONE 0xFFFFFFFF
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#define EMI1_SLOT1 0
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#define EMI1_SLOT2 1
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#define EMI1_SLOT3 2
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#define EMI1_SLOT4 3
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#define EMI1_SLOT5 4
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#define EMI1_SLOT6 5
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#define EMI2 6
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#define SFP_TX 1
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static const char * const mdio_names[] = {
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"LS2085A_QDS_MDIO0",
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"LS2085A_QDS_MDIO1",
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"LS2085A_QDS_MDIO2",
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"LS2085A_QDS_MDIO3",
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"LS2085A_QDS_MDIO4",
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"LS2085A_QDS_MDIO5",
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DEFAULT_WRIOP_MDIO2_NAME,
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};
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struct ls2085a_qds_mdio {
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u8 muxval;
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struct mii_dev *realbus;
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};
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static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
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{
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return mdio_names[muxval];
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}
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struct mii_dev *mii_dev_for_muxval(u8 muxval)
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{
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struct mii_dev *bus;
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const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
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if (!name) {
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printf("No bus for muxval %x\n", muxval);
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return NULL;
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}
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bus = miiphy_get_dev_by_name(name);
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if (!bus) {
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printf("No bus by name %s\n", name);
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return NULL;
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}
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return bus;
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}
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static void ls2085a_qds_enable_SFP_TX(u8 muxval)
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{
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u8 brdcfg9;
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brdcfg9 = QIXIS_READ(brdcfg[9]);
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brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
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brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
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QIXIS_WRITE(brdcfg[9], brdcfg9);
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}
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static void ls2085a_qds_mux_mdio(u8 muxval)
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{
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u8 brdcfg4;
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if (muxval <= 5) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
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brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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}
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static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
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int devad, int regnum)
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{
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struct ls2085a_qds_mdio *priv = bus->priv;
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ls2085a_qds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct ls2085a_qds_mdio *priv = bus->priv;
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ls2085a_qds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
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{
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struct ls2085a_qds_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval)
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{
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struct ls2085a_qds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate ls2085a_qds MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate ls2085a_qds private data\n");
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free(bus);
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return -1;
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}
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bus->read = ls2085a_qds_mdio_read;
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bus->write = ls2085a_qds_mdio_write;
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bus->reset = ls2085a_qds_mdio_reset;
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sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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/*
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* Initialize the dpmac_info array.
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*
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*/
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static void initialize_dpmac_to_slot(void)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
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FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
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>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
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int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
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FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
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>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
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switch (serdes1_prtcl) {
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case 0x2A:
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printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
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serdes1_prtcl);
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break;
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default:
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printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
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serdes1_prtcl);
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break;
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}
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switch (serdes2_prtcl) {
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case 0x07:
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case 0x08:
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printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
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serdes2_prtcl);
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lane_to_slot_fsm2[0] = EMI1_SLOT4;
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lane_to_slot_fsm2[1] = EMI1_SLOT4;
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lane_to_slot_fsm2[2] = EMI1_SLOT4;
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lane_to_slot_fsm2[3] = EMI1_SLOT4;
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/* No MDIO physical connection */
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lane_to_slot_fsm2[4] = EMI1_SLOT6;
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lane_to_slot_fsm2[5] = EMI1_SLOT6;
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lane_to_slot_fsm2[6] = EMI1_SLOT6;
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lane_to_slot_fsm2[7] = EMI1_SLOT6;
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break;
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default:
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printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
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serdes2_prtcl);
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break;
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}
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}
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void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
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{
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int lane, slot;
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struct mii_dev *bus;
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
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FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
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>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
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int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
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FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
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>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
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switch (serdes1_prtcl) {
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}
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switch (serdes2_prtcl) {
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case 0x07:
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case 0x08:
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lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
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(dpmac_id - 9));
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slot = lane_to_slot_fsm2[lane];
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switch (++slot) {
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case 1:
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break;
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case 3:
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break;
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case 4:
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/* Slot housing a SGMII riser card? */
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wriop_set_phy_address(dpmac_id,
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riser_phy_addr[dpmac_id - 9]);
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dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
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bus = mii_dev_for_muxval(EMI1_SLOT4);
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wriop_set_mdio(dpmac_id, bus);
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dpmac_info[dpmac_id].phydev = phy_connect(
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dpmac_info[dpmac_id].bus,
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dpmac_info[dpmac_id].phy_addr,
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NULL,
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dpmac_info[dpmac_id].enet_if);
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phy_config(dpmac_info[dpmac_id].phydev);
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break;
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case 5:
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break;
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case 6:
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/* Slot housing a SGMII riser card? */
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wriop_set_phy_address(dpmac_id,
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riser_phy_addr[dpmac_id - 13]);
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dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
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bus = mii_dev_for_muxval(EMI1_SLOT6);
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wriop_set_mdio(dpmac_id, bus);
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break;
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}
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break;
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default:
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printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
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serdes2_prtcl);
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break;
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}
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}
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void ls2085a_handle_phy_interface_xsgmii(int i)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
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FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
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>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
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switch (serdes1_prtcl) {
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case 0x2A:
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/*
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* XFI does not need a PHY to work, but to avoid U-boot use
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* default PHY address which is zero to a MAC when it found
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* a MAC has no PHY address, we give a PHY address to XFI
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* MAC, and should not use a real XAUI PHY address, since
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* MDIO can access it successfully, and then MDIO thinks
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* the XAUI card is used for the XFI MAC, which will cause
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* error.
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*/
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wriop_set_phy_address(i, i + 4);
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ls2085a_qds_enable_SFP_TX(SFP_TX);
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break;
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default:
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printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
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serdes1_prtcl);
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break;
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}
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int error;
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#ifdef CONFIG_FSL_MC_ENET
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struct memac_mdio_info *memac_mdio0_info;
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struct memac_mdio_info *memac_mdio1_info;
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unsigned int i;
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initialize_dpmac_to_slot();
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memac_mdio0_info = (struct memac_mdio_info *)malloc(
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sizeof(struct memac_mdio_info));
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memac_mdio0_info->regs =
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(struct memac_mdio_controller *)
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CONFIG_SYS_FSL_WRIOP1_MDIO1;
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memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
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/* Register the real MDIO1 bus */
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fm_memac_mdio_init(bis, memac_mdio0_info);
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memac_mdio1_info = (struct memac_mdio_info *)malloc(
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sizeof(struct memac_mdio_info));
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memac_mdio1_info->regs =
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(struct memac_mdio_controller *)
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CONFIG_SYS_FSL_WRIOP1_MDIO2;
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memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
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/* Register the real MDIO2 bus */
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fm_memac_mdio_init(bis, memac_mdio1_info);
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/* Register the muxing front-ends to the MDIO buses */
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ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
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ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
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ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
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ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
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ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
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ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
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ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
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for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
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switch (wriop_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_QSGMII:
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break;
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case PHY_INTERFACE_MODE_SGMII:
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ls2085a_handle_phy_interface_sgmii(i);
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break;
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case PHY_INTERFACE_MODE_XGMII:
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ls2085a_handle_phy_interface_xsgmii(i);
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break;
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default:
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break;
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}
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}
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error = cpu_eth_init(bis);
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#endif
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error = pci_eth_init(bis);
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return error;
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}
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@ -214,19 +214,6 @@ unsigned long get_dram_size_to_hide(void)
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return dram_to_hide;
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}
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int board_eth_init(bd_t *bis)
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{
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int error = 0;
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#ifdef CONFIG_FSL_MC_ENET
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error = cpu_eth_init(bis);
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#endif
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error = pci_eth_init(bis);
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return error;
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}
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#ifdef CONFIG_FSL_MC_ENET
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void fdt_fixup_board_enet(void *fdt)
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{
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@ -23,4 +23,8 @@
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#define QIXIS_DDRCLK_125 0x2
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#define QIXIS_DDRCLK_133 0x3
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#define BRDCFG4_EMISEL_MASK 0xE0
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#define BRDCFG4_EMISEL_SHIFT 5
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#define BRDCFG9_SFPTX_MASK 0x10
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#define BRDCFG9_SFPTX_SHIFT 4
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#endif /*__LS2_QDS_QIXIS_H__*/
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@ -6,3 +6,4 @@
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obj-y += ldpaa_wriop.o
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obj-y += ldpaa_eth.o
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obj-$(CONFIG_LS2085A) += ls2085a.o
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83
drivers/net/ldpaa_eth/ls2085a.c
Normal file
83
drivers/net/ldpaa_eth/ls2085a.c
Normal file
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|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <phy.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
|
||||
u32 dpmac_to_devdisr[] = {
|
||||
[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
|
||||
[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
|
||||
[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
|
||||
[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
|
||||
[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
|
||||
[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
|
||||
[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
|
||||
[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
|
||||
[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
|
||||
[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
|
||||
[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
|
||||
[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
|
||||
[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
|
||||
[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
|
||||
[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
|
||||
[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
|
||||
[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
|
||||
[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
|
||||
[WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19,
|
||||
[WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20,
|
||||
[WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21,
|
||||
[WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22,
|
||||
[WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23,
|
||||
[WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24,
|
||||
};
|
||||
|
||||
static int is_device_disabled(int dpmac_id)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
u32 devdisr2 = in_le32(&gur->devdisr2);
|
||||
|
||||
return dpmac_to_devdisr[dpmac_id] & devdisr2;
|
||||
}
|
||||
|
||||
void wriop_dpmac_disable(int dpmac_id)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
|
||||
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
|
||||
}
|
||||
|
||||
void wriop_dpmac_enable(int dpmac_id)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
|
||||
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
|
||||
}
|
||||
|
||||
phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
|
||||
{
|
||||
enum srds_prtcl;
|
||||
|
||||
if (is_device_disabled(dpmac_id + 1))
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
|
||||
if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
|
||||
return PHY_INTERFACE_MODE_SGMII;
|
||||
|
||||
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
|
||||
return PHY_INTERFACE_MODE_XGMII;
|
||||
|
||||
if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2)
|
||||
return PHY_INTERFACE_MODE_XGMII;
|
||||
|
||||
if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
|
||||
return PHY_INTERFACE_MODE_QSGMII;
|
||||
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
}
|
||||
|
|
@ -280,4 +280,23 @@ unsigned long get_board_ddr_clk(void);
|
|||
"kernel_load=0xa0000000\0" \
|
||||
"kernel_size=0x1000000\0"
|
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
#define CONFIG_FSL_MEMAC
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHYLIB_10G
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_PHY_VITESSE
|
||||
#define CONFIG_PHY_REALTEK
|
||||
#define CONFIG_PHY_TERANETICS
|
||||
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
||||
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
|
||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_ETHPRIME "DPNI1"
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __LS2_QDS_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue