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powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map

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- Sort by address, and fix column alignment

- Don't label things as localbus that aren't.  Instead, put chipselect
  info at the end of the description for localbus windows.  Note that
  NAND/NOR have their chipselects swapped when booting from NAND, and CS2
  can be either PMC or VSC7385 depending on hwconfig.

- Shrink NAND to the 32K that's actually mapped in the localbus

- Assign an address and size to L2 SRAM.  Remove the similarly named
  but unintelligible "L2 SDRAM(REV.)".

- Remove the untrue comment about L1 stack being mapped with TLB0.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Scott Wood 2012-10-02 19:35:18 -05:00
parent a796e72c78
commit d674bccf73
2 changed files with 10 additions and 14 deletions
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2
board/freescale/p1_p2_rdb_pc/law.c
View file

@ -32,7 +32,7 @@ struct law_entry law_table[] = {
#endif
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
};

22
include/configs/p1_p2_rdb_pc.h
View file

@ -331,21 +331,17 @@
/*
* Memory map
*
* 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
* 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
* 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
* 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
*
* Localbus cacheable (TBD)
* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
*
* Localbus non-cacheable
* 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
* 0xff80_0000 0xff8f_ffff NAND flash 1M non-cacheable
* 0xff90_0000 0xff97_ffff L2 SDRAM(REV.) 512K cacheable(optional)
* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
* 0xffd8_0000 0xffdf_ffff L2 SRAM Up to 512K cacheable
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
*/