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powerpc/t2080qds: fix for 1000BASE-KX
1000BASE-KX(1G-KX) uses SGMII protocol but the serdes lane runs in 1G-KX mode. By default, the lane runs in SGMII mode, when a MAC uses a lane in 1G-KX mode, corresponding bit in PCCR1 for the lane needs to be set, and needs to fixup dtb accordingly for kernel to do proper initialization. Hwconfig "fsl_1gkx" is used to indicate a MAC runs in 1G-KX mode, FM1 MAC 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a MAC runs in 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1' stands for FM1-MAC1, 'fm1_1g2' stands for FM1-MAC2, etc. If all MAC 1/2/5/6/9/10 run in 1G-KX mode, the hwconfig should has below setting: fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10 Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> [York Sun: Fix compiling warning] Reviewed-by: York Sun <yorksun@freescale.com>
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2 changed files with 99 additions and 0 deletions
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@ -104,6 +104,18 @@ XFI:
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set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
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XFI ports will use copper cable, the other two XFI ports will use fiber
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cable.
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1000BASE-KX(1G-KX):
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- T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
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runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
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in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
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Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper
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initialization.
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Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
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1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
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MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
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stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
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For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
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hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
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System Memory map
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----------------
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@ -47,6 +47,15 @@
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#define EMI2 8
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#endif
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#define PCCR1_SGMIIA_KX_MASK 0x00008000
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#define PCCR1_SGMIIB_KX_MASK 0x00004000
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#define PCCR1_SGMIIC_KX_MASK 0x00002000
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#define PCCR1_SGMIID_KX_MASK 0x00001000
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#define PCCR1_SGMIIE_KX_MASK 0x00000800
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#define PCCR1_SGMIIF_KX_MASK 0x00000400
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#define PCCR1_SGMIIG_KX_MASK 0x00000200
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#define PCCR1_SGMIIH_KX_MASK 0x00000100
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static int mdio_mux[NUM_FM_PORTS];
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static const char * const mdio_names[] = {
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@ -195,6 +204,11 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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int off;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#ifdef CONFIG_T2080QDS
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serdes_corenet_t *srds_regs =
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(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
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#endif
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u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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@ -205,9 +219,54 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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switch (port) {
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#if defined(CONFIG_T2080QDS)
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case FM1_DTSEC1:
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if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
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media_type = 1;
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fdt_set_phy_handle(fdt, compat, addr,
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"phy_1gkx1");
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fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
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sprintf(buf, "%s%s%s", buf, "lane-c,",
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(char *)lane_mode[0]);
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out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
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PCCR1_SGMIIH_KX_MASK);
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break;
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}
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case FM1_DTSEC2:
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if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
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media_type = 1;
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fdt_set_phy_handle(fdt, compat, addr,
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"phy_1gkx2");
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fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
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sprintf(buf, "%s%s%s", buf, "lane-d,",
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(char *)lane_mode[0]);
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out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
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PCCR1_SGMIIG_KX_MASK);
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break;
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}
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case FM1_DTSEC9:
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if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
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media_type = 1;
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fdt_set_phy_handle(fdt, compat, addr,
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"phy_1gkx9");
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fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
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sprintf(buf, "%s%s%s", buf, "lane-a,",
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(char *)lane_mode[0]);
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out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
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PCCR1_SGMIIE_KX_MASK);
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break;
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}
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case FM1_DTSEC10:
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if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
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media_type = 1;
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fdt_set_phy_handle(fdt, compat, addr,
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"phy_1gkx10");
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fdt_status_okay_by_alias(fdt,
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"1gkx_pcs_mdio10");
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sprintf(buf, "%s%s%s", buf, "lane-b,",
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(char *)lane_mode[0]);
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out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
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PCCR1_SGMIIF_KX_MASK);
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break;
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}
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if (mdio_mux[port] == EMI1_SLOT2) {
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sprintf(alias, "phy_sgmii_s2_%x", phy);
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fdt_set_phy_handle(fdt, compat, addr, alias);
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@ -219,7 +278,29 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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}
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break;
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case FM1_DTSEC5:
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if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
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media_type = 1;
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fdt_set_phy_handle(fdt, compat, addr,
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"phy_1gkx5");
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fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
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sprintf(buf, "%s%s%s", buf, "lane-g,",
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(char *)lane_mode[0]);
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out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
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PCCR1_SGMIIC_KX_MASK);
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break;
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}
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case FM1_DTSEC6:
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if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
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media_type = 1;
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fdt_set_phy_handle(fdt, compat, addr,
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"phy_1gkx6");
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fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
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sprintf(buf, "%s%s%s", buf, "lane-h,",
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(char *)lane_mode[0]);
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out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
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PCCR1_SGMIID_KX_MASK);
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break;
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}
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if (mdio_mux[port] == EMI1_SLOT1) {
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sprintf(alias, "phy_sgmii_s1_%x", phy);
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fdt_set_phy_handle(fdt, compat, addr, alias);
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@ -263,6 +344,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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default:
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break;
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}
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if (media_type) {
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/* set property for 1000BASE-KX in dtb */
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off = fdt_node_offset_by_compat_reg(fdt,
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"fsl,fman-memac-mdio", addr + 0x1000);
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fdt_setprop_string(fdt, off, "lane-instance", buf);
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}
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} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
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switch (srds_s1) {
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