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board/t104xrdb: Add support of CPLD
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Prabhakar Kushwaha
York Sun
parent
d616fc58e5
commit
55153d6c30
5 changed files with 174 additions and 0 deletions
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@ -6,6 +6,7 @@
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obj-y += t104xrdb.o
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obj-y += cpld.o
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obj-y += ddr.o
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obj-y += eth.o
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obj-$(CONFIG_PCI) += pci.o
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112
board/freescale/t104xrdb/cpld.c
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112
board/freescale/t104xrdb/cpld.c
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@ -0,0 +1,112 @@
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/**
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This file provides support for the board-specific CPLD used on some Freescale
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* reference boards.
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*
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* The following macros need to be defined:
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*
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* CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include "cpld.h"
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u8 cpld_read(unsigned int reg)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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return in_8(p + reg);
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}
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void cpld_write(unsigned int reg, u8 value)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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out_8(p + reg, value);
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}
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/**
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* Set the boot bank to the alternate bank
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*/
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void cpld_set_altbank(void)
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{
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u8 reg = CPLD_READ(flash_ctl_status);
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reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
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CPLD_WRITE(flash_ctl_status, reg);
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CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
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}
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/**
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* Set the boot bank to the default bank
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*/
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void cpld_set_defbank(void)
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{
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u8 reg = CPLD_READ(flash_ctl_status);
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reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
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CPLD_WRITE(flash_ctl_status, reg);
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CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
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}
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#ifdef DEBUG
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static void cpld_dump_regs(void)
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{
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printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
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printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
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printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
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printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
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printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
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printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
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printf("int_status = 0x%02x\n", CPLD_READ(int_status));
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printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
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printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
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printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
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printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
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printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
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printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
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printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
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printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
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putc('\n');
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}
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#endif
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int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rc = 0;
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if (argc <= 1)
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return cmd_usage(cmdtp);
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if (strcmp(argv[1], "reset") == 0) {
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if (strcmp(argv[2], "altbank") == 0)
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cpld_set_altbank();
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else
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cpld_set_defbank();
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#ifdef DEBUG
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} else if (strcmp(argv[1], "dump") == 0) {
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cpld_dump_regs();
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#endif
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} else
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rc = cmd_usage(cmdtp);
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return rc;
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}
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U_BOOT_CMD(
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cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
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"Reset the board or alternate bank",
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"reset - hard reset to default bank\n"
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"cpld reset altbank - reset to alternate bank\n"
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#ifdef DEBUG
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"cpld dump - display the CPLD registers\n"
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#endif
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);
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40
board/freescale/t104xrdb/cpld.h
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40
board/freescale/t104xrdb/cpld.h
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@ -0,0 +1,40 @@
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/**
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* Copyright 2013 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This file provides support for the ngPIXIS, a board-specific FPGA used on
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* some Freescale reference boards.
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*/
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/*
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* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
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*/
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struct cpld_data {
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u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
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u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
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u8 hw_ver; /* 0x02 - Hardware Revision Register */
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u8 sw_ver; /* 0x03 - Software Revision register */
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u8 res0[12]; /* 0x04 - 0x0F - not used */
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u8 reset_ctl1; /* 0x10 - Reset control Register1 */
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u8 reset_ctl2; /* 0x11 - Reset control Register2 */
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u8 int_status; /* 0x12 - Interrupt status Register */
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u8 flash_ctl_status; /* 0x13 - Flash control and status register */
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u8 fan_ctl_status; /* 0x14 - Fan control and status register */
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u8 led_ctl_status; /* 0x15 - LED control and status register */
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u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
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u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
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u8 boot_override; /* 0x18 - Boot override register */
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u8 boot_config1; /* 0x19 - Boot config override register*/
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u8 boot_config2; /* 0x1A - Boot config override register*/
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} cpld_data_t;
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/* Pointer to the CPLD register set */
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value)\
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cpld_write(offsetof(struct cpld_data, reg), value)
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@ -19,14 +19,27 @@
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#include <fm_eth.h>
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#include "t104xrdb.h"
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#include "cpld.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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struct cpu_type *cpu = gd->arch.cpu;
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u8 sw;
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printf("Board: %sRDB\n", cpu->name);
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printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
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CPLD_READ(hw_ver), CPLD_READ(sw_ver));
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sw = CPLD_READ(flash_ctl_status);
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sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
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if (sw <= 7)
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printf("vBank: %d\n", sw);
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else
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printf("Unsupported Bank=%x\n", sw);
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return 0;
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}
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@ -179,6 +179,14 @@
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
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/* CPLD on IFC */
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#define CPLD_LBMAP_MASK 0x3F
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_OVERRIDE 0x40
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#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
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#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
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#define CPLD_LBMAP_RESET 0xFF
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#define CPLD_LBMAP_SHIFT 0x03
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#define CONFIG_SYS_CPLD_BASE 0xffdf0000
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#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
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#define CONFIG_SYS_CSPR2_EXT (0xf)
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