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https://github.com/AsahiLinux/u-boot
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powerpc: p1_p2_rdb_pc: Enable p1_p2_rdb_pc to boot from SD Card with SPL
Enable p1_p2_rdb_pc to start from eSDHC with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
This commit is contained in:
Ying Zhang
York Sun
parent
ffee1dde3c
commit
3e6e69834a
4 changed files with 155 additions and 26 deletions
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@ -21,6 +21,9 @@ ifdef MINIMAL
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COBJS-y += spl_minimal.o tlb.o law.o
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else
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ifdef CONFIG_SPL_BUILD
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COBJS-y += spl.o
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endif
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COBJS-y += $(BOARD).o
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COBJS-y += ddr.o
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98
board/freescale/p1_p2_rdb_pc/spl.c
Normal file
98
board/freescale/p1_p2_rdb_pc/spl.c
Normal file
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@ -0,0 +1,98 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <nand.h>
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#include <i2c.h>
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#include <fsl_esdhc.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const u32 sysclk_tbl[] = {
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66666000, 7499900, 83332500, 8999900,
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99999000, 11111000, 12499800, 13333200
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};
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ulong get_effective_memsize(void)
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{
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return CONFIG_SYS_L2_SIZE;
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio, bus_clk;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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console_init_f();
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/* Set pmuxcr to allow both i2c1 and i2c2 */
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setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
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setbits_be32(&gur->pmuxcr,
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in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
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/* Read back the register to synchronize the write. */
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in_be32(&gur->pmuxcr);
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/* initialize selected port with appropriate baud rate */
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio >>= 1;
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bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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gd->bus_clk = bus_clk;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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bus_clk / 16 / CONFIG_BAUDRATE);
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#ifdef CONFIG_SPL_MMC_BOOT
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puts("\nSD boot...\n");
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#endif
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *)CONFIG_SPL_GD_ADDR;
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bd_t *bd;
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memset(gd, 0, sizeof(gd_t));
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bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
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memset(bd, 0, sizeof(bd_t));
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gd->bd = bd;
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bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
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bd->bi_memsize = CONFIG_SYS_L2_SIZE;
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probecpu();
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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env_init();
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_initialize(bd);
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#endif
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/* relocate environment function pointers etc. */
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env_relocate();
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#ifdef CONFIG_SYS_I2C
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i2c_init_all();
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#else
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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#endif
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gd->ram_size = initdram(0);
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puts("Second program loader running in sram...\n");
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_boot();
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#endif
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}
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@ -78,17 +78,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
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0, 7, BOOKE_PAGESZ_1M, 1),
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#endif
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#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
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#ifdef CONFIG_SYS_INIT_L2_ADDR
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/* L2SRAM */
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 8, BOOKE_PAGESZ_256K, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
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CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 12, BOOKE_PAGESZ_256K, 1),
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#else
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#if defined(CONFIG_SYS_RAMBOOT) || \
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(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
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/* *I*G - eSDHC/eSPI/NAND boot */
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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@ -101,8 +92,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 9, BOOKE_PAGESZ_1G, 1),
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#endif /* P1020MBG */
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#endif /* not L2 SRAM */
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#endif /* RAMBOOT/SPL */
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#ifdef CONFIG_SYS_INIT_L2_ADDR
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/* *I*G - L2SRAM */
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
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0, 11, BOOKE_PAGESZ_256K, 1)
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -144,19 +144,33 @@
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#define CONFIG_SYS_L2_SIZE (512 << 10)
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#endif
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#if CONFIG_SYS_L2_SIZE >= (512 << 10)
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/* must be 32-bit */
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RAMBOOT_SDCARD
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_SYS_TEXT_BASE 0x11000000
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#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
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#define CONFIG_SPL
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_PAD_TO 0x18000
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#define CONFIG_SPL_MAX_SIZE (96 * 1024)
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
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#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
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#define CONFIG_SPL_MMC_BOOT
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_COMMON_INIT_DDR
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#endif
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#endif
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#ifdef CONFIG_SPIFLASH
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@ -526,6 +540,23 @@
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#define CONFIG_VSC7385_IMAGE_SIZE 8192
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#endif
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/*
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* Config the L2 Cache as L2 SRAM
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*/
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#if defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_SDCARD)
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
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#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
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#endif
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#endif
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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@ -536,7 +567,7 @@
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#ifdef CONFIG_SPL_BUILD
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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@ -742,7 +773,7 @@
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#elif defined(CONFIG_RAMBOOT_SDCARD)
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#elif defined(CONFIG_SDCARD)
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_FSL_FIXED_MMC_LOCATION
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#define CONFIG_ENV_SIZE 0x2000
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