fsl_esdhc: Remove cache snooping for i.MX

The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so
disable it globally for this architecture. This avoids setting no_snoop for all
i.MX boards, and it prevents setting a reserved bit of a reserved register if
fsl_esdhc_mmc_init() is used on i.MX, like in
arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init().

Since no_snoop was only used on i.MX, get rid of it BTW.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Benoît Thébaudeau 2012-08-13 07:28:16 +00:00 committed by Albert ARIBAUD
parent 8e99ecd74b
commit 16e43f354d
12 changed files with 20 additions and 20 deletions

View file

@ -172,7 +172,7 @@ static void setup_iomux_fec(void)
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 };
struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR };
int board_mmc_getcd(struct mmc *mmc)
{

View file

@ -47,8 +47,8 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR, 1},
{MMC_SDHC2_BASE_ADDR, 1},
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
};
#endif

View file

@ -79,8 +79,8 @@ static void setup_iomux_uart(void)
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR, 1 },
{MMC_SDHC2_BASE_ADDR, 1 },
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)

View file

@ -205,8 +205,8 @@ static void setup_iomux_fec(void)
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR, 1},
{MMC_SDHC3_BASE_ADDR, 1},
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC3_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)

View file

@ -165,8 +165,8 @@ static void setup_iomux_fec(void)
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR, 1},
{MMC_SDHC3_BASE_ADDR, 1},
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC3_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)

View file

@ -129,7 +129,7 @@ static void setup_iomux_fec(void)
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{MMC_SDHC1_BASE_ADDR, 1},
{MMC_SDHC1_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)

View file

@ -116,8 +116,8 @@ static void setup_iomux_enet(void)
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR, 1},
{USDHC4_BASE_ADDR, 1},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)

View file

@ -239,8 +239,8 @@ int board_ehci_hcd_init(int port)
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR, 1},
{USDHC4_BASE_ADDR, 1},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)

View file

@ -268,8 +268,8 @@ static inline void power_init(void) { }
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR, 1},
{MMC_SDHC2_BASE_ADDR, 1},
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
};
static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {

View file

@ -521,7 +521,7 @@ static void setup_fec(void)
}
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{MMC_SDHC1_BASE_ADDR, 1},
{MMC_SDHC1_BASE_ADDR},
};
int get_mmc_getcd(u8 *cd, struct mmc *mmc)

View file

@ -479,9 +479,10 @@ static int esdhc_init(struct mmc *mmc)
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000);
#ifndef ARCH_MXC
/* Enable cache snooping */
if (cfg && !cfg->no_snoop)
esdhc_write32(&regs->scr, 0x00000040);
esdhc_write32(&regs->scr, 0x00000040);
#endif
esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);

View file

@ -167,7 +167,6 @@
struct fsl_esdhc_cfg {
u32 esdhc_base;
u32 no_snoop;
};
/* Select the correct accessors depending on endianess */