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https://github.com/AsahiLinux/u-boot
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armv8/ls1043ardb: Add nand boot support
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Gong Qianyu
York Sun
parent
f3a8e2b7d4
commit
3ad4472923
10 changed files with 123 additions and 0 deletions
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@ -630,6 +630,7 @@ config TARGET_LS1021ATWR
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config TARGET_LS1043ARDB
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bool "Support ls1043ardb"
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select ARM64
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select SUPPORT_SPL
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help
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Support for Freescale LS1043ARDB platform.
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@ -71,6 +71,9 @@ void board_init_f(ulong dummy)
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/* Clear the BSS */
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memset(__bss_start, 0, __bss_end - __bss_start);
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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board_init_r(NULL, 0);
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}
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#endif
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@ -83,3 +83,4 @@ Start Address End Address Description Size
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Booting Options
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---------------
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a) NOR boot
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b) NAND boot
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@ -45,6 +45,22 @@ void cpld_set_defbank(void)
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CPLD_WRITE(global_rst, 1);
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}
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void cpld_set_nand(void)
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{
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u16 reg = CPLD_CFG_RCW_SRC_NAND;
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u8 reg5 = (u8)(reg >> 1);
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u8 reg6 = (u8)(reg & 1);
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cpld_rev_bit(®5);
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CPLD_WRITE(soft_mux_on, 1);
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CPLD_WRITE(cfg_rcw_src1, reg5);
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CPLD_WRITE(cfg_rcw_src2, reg6);
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CPLD_WRITE(system_rst, 1);
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}
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#ifdef DEBUG
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static void cpld_dump_regs(void)
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{
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@ -91,6 +107,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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if (strcmp(argv[1], "reset") == 0) {
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if (strcmp(argv[2], "altbank") == 0)
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cpld_set_altbank();
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else if (strcmp(argv[2], "nand") == 0)
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cpld_set_nand();
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else
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cpld_set_defbank();
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#ifdef DEBUG
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@ -109,6 +127,7 @@ U_BOOT_CMD(
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"Reset the board or alternate bank",
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"reset: reset to default bank\n"
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"cpld reset altbank: reset to alternate bank\n"
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"cpld reset nand: reset to boot from NAND flash\n"
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#ifdef DEBUG
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"cpld dump - display the CPLD registers\n"
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#endif
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@ -40,4 +40,5 @@ void cpld_rev_bit(unsigned char *value);
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#define CPLD_SW_MUX_BANK_SEL 0x40
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_SEL_ALTBANK 0x04
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#define CPLD_CFG_RCW_SRC_NAND 0x106
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#endif
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14
board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
Normal file
14
board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
Normal file
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@ -0,0 +1,14 @@
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#Configure Scratch register
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09570600 00000000
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09570604 10000000
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#Alt base register
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09570158 00001000
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#Disable CCI barrier tranaction
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09570178 0000e010
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09180000 00000008
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#USB PHY frequency sel
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09570418 0000009e
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0957041c 0000009e
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09570420 0000009e
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#flush PBI data
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096100c0 000fffff
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7
board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
Normal file
7
board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
Normal file
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@ -0,0 +1,7 @@
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#PBL preamble and RCW header
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aa55aa55 01ee0100
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# serdes protocol
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0810000f 0c000000 00000000 00000000
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14550002 80004012 e0106000 61002000
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00000000 00000000 00000000 00038800
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00000000 00001100 00000096 00000001
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4
configs/ls1043ardb_nand_defconfig
Normal file
4
configs/ls1043ardb_nand_defconfig
Normal file
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@ -0,0 +1,4 @@
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
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CONFIG_ARM=y
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CONFIG_TARGET_LS1043ARDB=y
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@ -60,6 +60,33 @@
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* NAND SPL */
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SPL_PBL_PAD
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN 0xa0000
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#endif
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/* IFC */
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#define CONFIG_FSL_IFC
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/*
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@ -12,7 +12,11 @@
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#if defined(CONFIG_NAND_BOOT)
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#define CONFIG_SYS_TEXT_BASE 0x82000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x60100000
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#endif
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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@ -33,6 +37,14 @@
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
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#endif
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
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#endif
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/*
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* NOR Flash Definitions
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*/
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@ -116,6 +128,12 @@
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
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#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
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#endif
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/*
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* CPLD
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*/
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@ -144,6 +162,25 @@
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#define CONFIG_SYS_CPLD_FTIM3 0x0
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/* IFC Timing Params */
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#else
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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@ -161,6 +198,7 @@
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
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#endif
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
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@ -183,9 +221,17 @@
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/*
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* Environment
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*/
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_NAND_BOOT)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x20000
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#endif
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#endif /* __LS1043ARDB_H__ */
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