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https://github.com/AsahiLinux/u-boot
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board/freescale/mpc8266ads/mpc8266ads.c: CodingStyle cleanup
Make (mostly) checkpatch clean. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Rune Torgersen <runet@innovsys.com>
This commit is contained in:
Wolfgang Denk
parent
f58902d0aa
commit
55e33279ce
1 changed files with 290 additions and 276 deletions
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2001
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* (C) Copyright 2001-2011
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Modified during 2001 by
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@ -61,8 +61,8 @@
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
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/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
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/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
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@ -95,10 +95,10 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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@ -131,10 +131,10 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
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@ -167,10 +167,10 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
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},
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
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/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
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@ -203,7 +203,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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}
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};
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typedef struct bscr_ {
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@ -224,317 +224,331 @@ typedef struct pci_ic_s {
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void reset_phy(void)
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{
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volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
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volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
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/* reset the FEC port */
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bcsr->bcsr1 &= ~FETH_RST;
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bcsr->bcsr1 |= FETH_RST;
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/* reset the FEC port */
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bcsr->bcsr1 &= ~FETH_RST;
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bcsr->bcsr1 |= FETH_RST;
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}
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int board_early_init_f (void)
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int board_early_init_f(void)
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{
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volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
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volatile pci_ic_t *pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
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volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR;
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volatile pci_ic_t *pci_ic = (pci_ic_t *)CONFIG_SYS_PCI_INT;
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bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
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bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
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/* mask all PCI interrupts */
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pci_ic->pci_int_mask |= 0xfff00000;
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/* mask all PCI interrupts */
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pci_ic->pci_int_mask |= 0xfff00000;
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return 0;
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return 0;
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}
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int checkboard(void)
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{
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puts ("Board: Motorola MPC8266ADS\n");
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return 0;
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puts("Board: Motorola MPC8266ADS\n");
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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/* Autoinit part stolen from board/sacsng/sacsng.c */
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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volatile uchar c = 0xff;
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volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
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uint psdmr = CONFIG_SYS_PSDMR;
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int i;
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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volatile uchar c = 0xff;
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volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
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uint psdmr = CONFIG_SYS_PSDMR;
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int i;
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uint psrt = 0x21; /* for no SPD */
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uint chipselects = 1; /* for no SPD */
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uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
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uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
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uint data_width;
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uint rows;
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uint banks;
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uint cols;
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uint caslatency;
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uint width;
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uint rowst;
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uint sdam;
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uint bsma;
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uint sda10;
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u_char spd_size;
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u_char data;
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u_char cksum;
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int j;
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uint psrt = 0x21; /* for no SPD */
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uint chipselects = 1; /* for no SPD */
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uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
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uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
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uint data_width;
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uint rows;
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uint banks;
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uint cols;
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uint caslatency;
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uint width;
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uint rowst;
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uint sdam;
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uint bsma;
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uint sda10;
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u_char spd_size;
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u_char data;
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u_char cksum;
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int j;
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/* Keep the compiler from complaining about potentially uninitialized vars */
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data_width = rows = banks = cols = caslatency = 0;
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/*
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* Keep the compiler from complaining about
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* potentially uninitialized vars
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*/
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data_width = rows = banks = cols = caslatency = 0;
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/*
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* Read the SDRAM SPD EEPROM via I2C.
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*/
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i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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/*
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* Read the SDRAM SPD EEPROM via I2C.
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*/
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
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spd_size = data;
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cksum = data;
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for(j = 1; j < 64; j++)
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{ /* read only the checksummed bytes */
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/* note: the I2C address autoincrements when alen == 0 */
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i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
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spd_size = data;
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cksum = data;
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for (j = 1; j < 64; j++) { /* read only the checksummed bytes */
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/* note: the I2C address autoincrements when alen == 0 */
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i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
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/*printf("addr %d = 0x%02x\n", j, data);*/
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if(j == 5) chipselects = data & 0x0F;
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else if(j == 6) data_width = data;
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else if(j == 7) data_width |= data << 8;
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else if(j == 3) rows = data & 0x0F;
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else if(j == 4) cols = data & 0x0F;
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else if(j == 12)
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{
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/*printf("addr %d = 0x%02x\n", j, data); */
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if (j == 5)
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chipselects = data & 0x0F;
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else if (j == 6)
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data_width = data;
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else if (j == 7)
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data_width |= data << 8;
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else if (j == 3)
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rows = data & 0x0F;
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else if (j == 4)
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cols = data & 0x0F;
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else if (j == 12) {
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/*
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* Refresh rate: this assumes the prescaler is set to
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* approximately 0.39uSec per tick and the target refresh period
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* is about 85% of maximum.
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* Refresh rate: this assumes the prescaler is set to
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* approximately 0.39uSec per tick and the target
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* refresh period is about 85% of maximum.
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*/
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switch(data & 0x7F)
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{
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default:
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case 0: psrt = 0x21; /* 15.625uS */ break;
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case 1: psrt = 0x07; /* 3.9uS */ break;
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case 2: psrt = 0x0F; /* 7.8uS */ break;
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case 3: psrt = 0x43; /* 31.3uS */ break;
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case 4: psrt = 0x87; /* 62.5uS */ break;
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case 5: psrt = 0xFF; /* 125uS */ break;
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switch (data & 0x7F) {
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default:
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case 0:
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psrt = 0x21; /* 15.625uS */
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break;
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case 1:
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psrt = 0x07; /* 3.9uS */
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break;
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case 2:
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psrt = 0x0F; /* 7.8uS */
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break;
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case 3:
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psrt = 0x43; /* 31.3uS */
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break;
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case 4:
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psrt = 0x87; /* 62.5uS */
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break;
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case 5:
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psrt = 0xFF; /* 125uS */
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break;
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}
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}
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else if(j == 17) banks = data;
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else if(j == 18)
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{
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caslatency = 3; /* default CL */
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# if(PESSIMISTIC_SDRAM)
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if((data & 0x04) != 0) caslatency = 3;
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else if((data & 0x02) != 0) caslatency = 2;
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else if((data & 0x01) != 0) caslatency = 1;
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# else
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if((data & 0x01) != 0) caslatency = 1;
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else if((data & 0x02) != 0) caslatency = 2;
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else if((data & 0x04) != 0) caslatency = 3;
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# endif
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else
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{
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printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
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} else if (j == 17)
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banks = data;
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else if (j == 18) {
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caslatency = 3; /* default CL */
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#if (PESSIMISTIC_SDRAM)
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if ((data & 0x04) != 0)
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caslatency = 3;
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else if ((data & 0x02) != 0)
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caslatency = 2;
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else if ((data & 0x01) != 0)
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caslatency = 1;
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#else
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if ((data & 0x01) != 0)
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caslatency = 1;
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else if ((data & 0x02) != 0)
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caslatency = 2;
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else if ((data & 0x04) != 0)
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caslatency = 3;
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#endif
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else {
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printf("WARNING: Unknown CAS latency 0x%02X, using 3\n",
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data);
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}
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}
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else if(j == 63)
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{
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if(data != cksum)
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{
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printf ("WARNING: Configuration data checksum failure:"
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} else if (j == 63) {
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if (data != cksum) {
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printf("WARNING: Configuration data checksum failure:"
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" is 0x%02x, calculated 0x%02x\n",
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data, cksum);
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data, cksum);
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}
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}
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cksum += data;
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}
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}
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/* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
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if(caslatency < 2) {
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/* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
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if (caslatency < 2) {
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printf("CL was %d, forcing to 2\n", caslatency);
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caslatency = 2;
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}
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if(rows > 14) {
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printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
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}
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if (rows > 14) {
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printf("This doesn't look good, rows = %d, should be <= 14\n",
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rows);
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rows = 14;
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}
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if(cols > 11) {
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printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
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}
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if (cols > 11) {
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printf("This doesn't look good, columns = %d, should be <= 11\n",
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cols);
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cols = 11;
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}
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}
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if((data_width != 64) && (data_width != 72))
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{
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if ((data_width != 64) && (data_width != 72)) {
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printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
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data_width);
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}
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width = 3; /* 2^3 = 8 bytes = 64 bits wide */
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/*
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* Convert banks into log2(banks)
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*/
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if (banks == 2) banks = 1;
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else if(banks == 4) banks = 2;
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else if(banks == 8) banks = 3;
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}
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width = 3; /* 2^3 = 8 bytes = 64 bits wide */
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/*
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* Convert banks into log2(banks)
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*/
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if (banks == 2)
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banks = 1;
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else if (banks == 4)
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banks = 2;
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else if (banks == 8)
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banks = 3;
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sdram_size = 1 << (rows + cols + banks + width);
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/* hack for high density memory (512MB per CS) */
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/* !!!!! Will ONLY work with Page Based Interleave !!!!!
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( PSDMR[PBI] = 1 )
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*/
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/* mamory actually has 11 column addresses, but the memory controller
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doesn't really care.
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the calculations that follow will however move the rows so that
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they are muxed one bit off if you use 11 bit columns.
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The solution is to tell the memory controller the correct size of the memory
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but change the number of columns to 10 afterwards.
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The 11th column addre will still be mucxed correctly onto the bus.
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sdram_size = 1 << (rows + cols + banks + width);
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/* hack for high density memory (512MB per CS) */
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/* !!!!! Will ONLY work with Page Based Interleave !!!!!
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( PSDMR[PBI] = 1 )
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*/
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/*
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* memory actually has 11 column addresses, but the memory
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* controller doesn't really care.
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*
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* the calculations that follow will however move the rows so
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* that they are muxed one bit off if you use 11 bit columns.
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*
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* The solution is to tell the memory controller the correct
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* size of the memory but change the number of columns to 10
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* afterwards.
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*
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* The 11th column addre will still be mucxed correctly onto
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* the bus.
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*
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* Also be aware that the MPC8266ADS board Rev B has not
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* connected Row address 13 to anything.
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*
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* The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
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*/
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if (cols > 10)
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cols = 10;
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Also be aware that the MPC8266ADS board Rev B has not connected
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Row address 13 to anything.
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The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
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*/
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if (cols > 10)
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cols = 10;
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#if(CONFIG_PBI == 0) /* bank-based interleaving */
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rowst = ((32 - 6) - (rows + cols + width)) * 2;
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#if (CONFIG_PBI == 0) /* bank-based interleaving */
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rowst = ((32 - 6) - (rows + cols + width)) * 2;
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#else
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rowst = 32 - (rows + banks + cols + width);
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rowst = 32 - (rows + banks + cols + width);
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#endif
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or = ~(sdram_size - 1) | /* SDAM address mask */
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((banks-1) << 13) | /* banks per device */
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(rowst << 9) | /* rowst */
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((rows - 9) << 6); /* numr */
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or = ~(sdram_size - 1) | /* SDAM address mask */
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((banks - 1) << 13) | /* banks per device */
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(rowst << 9) | /* rowst */
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((rows - 9) << 6); /* numr */
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/*printf("memctl->memc_or2 = 0x%08x\n", or);*/
|
||||
/*printf("memctl->memc_or2 = 0x%08x\n", or); */
|
||||
|
||||
/*
|
||||
* SDAM specifies the number of columns that are multiplexed
|
||||
* (reference AN2165/D), defined to be (columns - 6) for page
|
||||
* interleave, (columns - 8) for bank interleave.
|
||||
*
|
||||
* BSMA is 14 - max(rows, cols). The bank select lines come
|
||||
* into play above the highest "address" line going into the
|
||||
* the SDRAM.
|
||||
*/
|
||||
#if(CONFIG_PBI == 0) /* bank-based interleaving */
|
||||
sdam = cols - 8;
|
||||
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
|
||||
sda10 = sdam + 2;
|
||||
/*
|
||||
* SDAM specifies the number of columns that are multiplexed
|
||||
* (reference AN2165/D), defined to be (columns - 6) for page
|
||||
* interleave, (columns - 8) for bank interleave.
|
||||
*
|
||||
* BSMA is 14 - max(rows, cols). The bank select lines come
|
||||
* into play above the highest "address" line going into the
|
||||
* the SDRAM.
|
||||
*/
|
||||
#if (CONFIG_PBI == 0) /* bank-based interleaving */
|
||||
sdam = cols - 8;
|
||||
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
|
||||
sda10 = sdam + 2;
|
||||
#else
|
||||
sdam = cols + banks - 8;
|
||||
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
|
||||
sda10 = sdam;
|
||||
sdam = cols + banks - 8;
|
||||
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
|
||||
sda10 = sdam;
|
||||
#endif
|
||||
#if(PESSIMISTIC_SDRAM)
|
||||
psdmr = (CONFIG_PBI |\
|
||||
PSDMR_RFEN |\
|
||||
PSDMR_RFRC_16_CLK |\
|
||||
PSDMR_PRETOACT_8W |\
|
||||
PSDMR_ACTTORW_8W |\
|
||||
PSDMR_WRC_4C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_BUFCMD) |\
|
||||
caslatency |\
|
||||
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
|
||||
(sdam << 24) |\
|
||||
(bsma << 21) |\
|
||||
(sda10 << 18);
|
||||
#if (PESSIMISTIC_SDRAM)
|
||||
psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
|
||||
PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
|
||||
PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
|
||||
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
|
||||
(sdam << 24) | (bsma << 21) | (sda10 << 18);
|
||||
#else
|
||||
psdmr = (CONFIG_PBI |\
|
||||
PSDMR_RFEN |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
|
||||
PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
|
||||
PSDMR_WRC_1C | /* 1 clock + 7nSec */
|
||||
EAMUX |\
|
||||
BUFCMD) |\
|
||||
caslatency |\
|
||||
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
|
||||
(sdam << 24) |\
|
||||
(bsma << 21) |\
|
||||
(sda10 << 18);
|
||||
psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
|
||||
PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */
|
||||
PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */
|
||||
PSDMR_WRC_1C | /* 1 clock + 7nSec */
|
||||
EAMUX | BUFCMD) | caslatency |
|
||||
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
|
||||
(sdam << 24) | (bsma << 21) | (sda10 << 18);
|
||||
#endif
|
||||
/*printf("psdmr = 0x%08x\n", psdmr);*/
|
||||
/*printf("psdmr = 0x%08x\n", psdmr); */
|
||||
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
|
||||
*
|
||||
* "At system reset, initialization software must set up the
|
||||
* programmable parameters in the memory controller banks registers
|
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
|
||||
* system software should execute the following initialization sequence
|
||||
* for each SDRAM device.
|
||||
*
|
||||
* 1. Issue a PRECHARGE-ALL-BANKS command
|
||||
* 2. Issue eight CBR REFRESH commands
|
||||
* 3. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* Quote from Micron MT48LC8M16A2 data sheet:
|
||||
*
|
||||
* "...the SDRAM requires a 100uS delay prior to issuing any
|
||||
* command other than a COMMAND INHIBIT or NOP. Starting at some
|
||||
* point during this 100uS period and continuing at least through
|
||||
* the end of this period, COMMAND INHIBIT or NOP commands should
|
||||
* be applied."
|
||||
*
|
||||
* "Once the 100uS delay has been satisfied with at least one COMMAND
|
||||
* INHIBIT or NOP command having been applied, a /PRECHARGE command/
|
||||
* should be applied. All banks must then be precharged, thereby
|
||||
* placing the device in the all banks idle state."
|
||||
*
|
||||
* "Once in the idle state, /two/ AUTO REFRESH cycles must be
|
||||
* performed. After the AUTO REFRESH cycles are complete, the
|
||||
* SDRAM is ready for mode register programming."
|
||||
*
|
||||
* (/emphasis/ mine, gvb)
|
||||
*
|
||||
* The way I interpret this, Micron start up sequence is:
|
||||
* 1. Issue a PRECHARGE-BANK command (initial precharge)
|
||||
* 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
|
||||
* 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
|
||||
* 4. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* --------
|
||||
*
|
||||
* The initial commands are executed by setting P/LSDMR[OP] and
|
||||
* accessing the SDRAM with a single-byte transaction."
|
||||
*
|
||||
* The appropriate BRx/ORx registers have already been set when we
|
||||
* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
|
||||
*/
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
|
||||
*
|
||||
* "At system reset, initialization software must set up the
|
||||
* programmable parameters in the memory controller banks registers
|
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
|
||||
* system software should execute the following initialization sequence
|
||||
* for each SDRAM device.
|
||||
*
|
||||
* 1. Issue a PRECHARGE-ALL-BANKS command
|
||||
* 2. Issue eight CBR REFRESH commands
|
||||
* 3. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* Quote from Micron MT48LC8M16A2 data sheet:
|
||||
*
|
||||
* "...the SDRAM requires a 100uS delay prior to issuing any
|
||||
* command other than a COMMAND INHIBIT or NOP. Starting at some
|
||||
* point during this 100uS period and continuing at least through
|
||||
* the end of this period, COMMAND INHIBIT or NOP commands should
|
||||
* be applied."
|
||||
*
|
||||
* "Once the 100uS delay has been satisfied with at least one COMMAND
|
||||
* INHIBIT or NOP command having been applied, a /PRECHARGE command/
|
||||
* should be applied. All banks must then be precharged, thereby
|
||||
* placing the device in the all banks idle state."
|
||||
*
|
||||
* "Once in the idle state, /two/ AUTO REFRESH cycles must be
|
||||
* performed. After the AUTO REFRESH cycles are complete, the
|
||||
* SDRAM is ready for mode register programming."
|
||||
*
|
||||
* (/emphasis/ mine, gvb)
|
||||
*
|
||||
* The way I interpret this, Micron start up sequence is:
|
||||
* 1. Issue a PRECHARGE-BANK command (initial precharge)
|
||||
* 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
|
||||
* 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
|
||||
* 4. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* --------
|
||||
*
|
||||
* The initial commands are executed by setting P/LSDMR[OP] and
|
||||
* accessing the SDRAM with a single-byte transaction."
|
||||
*
|
||||
* The appropriate BRx/ORx registers have already been set
|
||||
* when we get here. The SDRAM can be accessed at the address
|
||||
* CONFIG_SYS_SDRAM_BASE.
|
||||
*/
|
||||
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
memctl->memc_psrt = psrt;
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
memctl->memc_psrt = psrt;
|
||||
|
||||
memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
|
||||
memctl->memc_or2 = or;
|
||||
memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
|
||||
memctl->memc_or2 = or;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
|
||||
for (i = 0; i < 8; i++)
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
|
||||
*ramaddr = c;
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
|
||||
for (i = 0; i < 8; i++)
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||
*ramaddr = c;
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
|
||||
*ramaddr = c;
|
||||
|
||||
/*
|
||||
* Do it a second time for the second set of chips if the DIMM has
|
||||
* two chip selects (double sided).
|
||||
*/
|
||||
if(chipselects > 1)
|
||||
{
|
||||
ramaddr += sdram_size;
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||
*ramaddr = c;
|
||||
|
||||
/*
|
||||
* Do it a second time for the second set of chips if the DIMM has
|
||||
* two chip selects (double sided).
|
||||
*/
|
||||
if (chipselects > 1) {
|
||||
ramaddr += sdram_size;
|
||||
|
||||
memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
|
||||
memctl->memc_or3 = or;
|
||||
|
|
@ -551,28 +565,28 @@ phys_size_t initdram(int board_type)
|
|||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||
*ramaddr = c;
|
||||
}
|
||||
}
|
||||
|
||||
/* print info */
|
||||
printf("SDRAM configuration read from SPD\n");
|
||||
printf("\tSize per side = %dMB\n", sdram_size >> 20);
|
||||
printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
|
||||
printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n",
|
||||
chipselects, 1 << (banks), cols, rows, data_width);
|
||||
printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
|
||||
#if(CONFIG_PBI == 0) /* bank-based interleaving */
|
||||
printf(", Using Bank Based Interleave\n");
|
||||
#if (CONFIG_PBI == 0) /* bank-based interleaving */
|
||||
printf(", Using Bank Based Interleave\n");
|
||||
#else
|
||||
printf(", Using Page Based Interleave\n");
|
||||
printf(", Using Page Based Interleave\n");
|
||||
#endif
|
||||
printf("\tTotal size: ");
|
||||
|
||||
/* this delay only needed for original 16MB DIMM...
|
||||
* Not needed for any other memory configuration */
|
||||
if ((sdram_size * chipselects) == (16 *1024 *1024))
|
||||
udelay (250000);
|
||||
return (sdram_size * chipselects);
|
||||
/*return (16 * 1024 * 1024);*/
|
||||
}
|
||||
/* this delay only needed for original 16MB DIMM...
|
||||
* Not needed for any other memory configuration */
|
||||
if ((sdram_size * chipselects) == (16 * 1024 * 1024))
|
||||
udelay(250000);
|
||||
|
||||
return sdram_size * chipselects;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
struct pci_controller hose;
|
||||
|
|
|
|||
Loading…
Reference in a new issue