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Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx

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Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2013-11-18 10:29:32 -08:00
parent 5614e71b49
commit 9a17eb5b7e
29 changed files with 175 additions and 308 deletions
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4
arch/powerpc/cpu/mpc83xx/ecc.c
View file

@ -16,7 +16,7 @@ void ecc_print_status(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef CONFIG_SYS_FSL_DDR2
ccsr_ddr_t *ddr = &immap->ddr;
struct ccsr_ddr __iomem *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;
#endif
@ -100,7 +100,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef CONFIG_SYS_FSL_DDR2
ccsr_ddr_t *ddr = &immap->ddr;
struct ccsr_ddr __iomem *ddr = &immap->ddr;
#else
ddr83xx_t *ddr = &immap->ddr;
#endif

4
arch/powerpc/cpu/mpc85xx/cpu.c
View file

@ -416,7 +416,7 @@ static void dump_spd_ddr_reg(void)
int i, j, k, m;
u8 *p_8;
u32 *p_32;
ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
generic_spd_eeprom_t
spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
@ -482,7 +482,7 @@ static void dump_spd_ddr_reg(void)
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {

106
arch/powerpc/include/asm/immap_83xx.h
View file

@ -14,6 +14,7 @@
#ifndef __IMMAP_83xx__
#define __IMMAP_83xx__
#include <fsl_immap.h>
#include <asm/types.h>
#include <asm/fsl_i2c.h>
#include <asm/mpc8xxx_spi.h>
@ -277,107 +278,10 @@ typedef struct qesba83xx {
} qesba83xx_t;
/*
* DDR Memory Controller Memory Map
* DDR Memory Controller Memory Map for DDR1
* The structure of DDR2, or DDR3 is defined in fsl_immap.h
*/
#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
typedef struct ccsr_ddr {
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
u8 res1[4];
u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
u8 res2[4];
u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
u8 res3[4];
u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
u8 res4[100];
u32 cs0_config; /* Chip Select Configuration */
u32 cs1_config; /* Chip Select Configuration */
u32 cs2_config; /* Chip Select Configuration */
u32 cs3_config; /* Chip Select Configuration */
u8 res4a[48];
u32 cs0_config_2; /* Chip Select Configuration 2 */
u32 cs1_config_2; /* Chip Select Configuration 2 */
u32 cs2_config_2; /* Chip Select Configuration 2 */
u32 cs3_config_2; /* Chip Select Configuration 2 */
u8 res5[48];
u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
u32 sdram_cfg; /* SDRAM Control Configuration */
u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
u32 sdram_mode; /* SDRAM Mode Configuration */
u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
u32 sdram_md_cntl; /* SDRAM Mode Control */
u32 sdram_interval; /* SDRAM Interval Configuration */
u32 sdram_data_init; /* SDRAM Data initialization */
u8 res6[4];
u32 sdram_clk_cntl; /* SDRAM Clock Control */
u8 res7[20];
u32 init_addr; /* training init addr */
u32 init_ext_addr; /* training init extended addr */
u8 res8_1[16];
u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
u8 reg8_1a[8];
u32 ddr_zq_cntl; /* ZQ calibration control*/
u32 ddr_wrlvl_cntl; /* write leveling control*/
u8 reg8_1aa[4];
u32 ddr_sr_cntr; /* self refresh counter */
u32 ddr_sdram_rcw_1; /* Control Words 1 */
u32 ddr_sdram_rcw_2; /* Control Words 2 */
u8 reg_1ab[8];
u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
u8 res8_1b[104];
u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
u8 res8_1ba[0x908];
u32 ddr_dsr1; /* Debug Status 1 */
u32 ddr_dsr2; /* Debug Status 2 */
u32 ddr_cdr1; /* Control Driver 1 */
u32 ddr_cdr2; /* Control Driver 2 */
u8 res8_1c[200];
u32 ip_rev1; /* IP Block Revision 1 */
u32 ip_rev2; /* IP Block Revision 2 */
u32 eor; /* Enhanced Optimization Register */
u8 res8_2[252];
u32 mtcr; /* Memory Test Control Register */
u8 res8_3[28];
u32 mtp1; /* Memory Test Pattern 1 */
u32 mtp2; /* Memory Test Pattern 2 */
u32 mtp3; /* Memory Test Pattern 3 */
u32 mtp4; /* Memory Test Pattern 4 */
u32 mtp5; /* Memory Test Pattern 5 */
u32 mtp6; /* Memory Test Pattern 6 */
u32 mtp7; /* Memory Test Pattern 7 */
u32 mtp8; /* Memory Test Pattern 8 */
u32 mtp9; /* Memory Test Pattern 9 */
u32 mtp10; /* Memory Test Pattern 10 */
u8 res8_4[184];
u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
u8 res9[20];
u32 capture_data_hi; /* Data Path Read Capture High */
u32 capture_data_lo; /* Data Path Read Capture Low */
u32 capture_ecc; /* Data Path Read Capture ECC */
u8 res10[20];
u32 err_detect; /* Error Detect */
u32 err_disable; /* Error Disable */
u32 err_int_en;
u32 capture_attributes; /* Error Attrs Capture */
u32 capture_address; /* Error Addr Capture */
u32 capture_ext_address; /* Error Extended Addr Capture */
u32 err_sbe; /* Single-Bit ECC Error Management */
u8 res11[164];
u32 debug[32]; /* debug_1 to debug_32 */
u8 res12[128];
} ccsr_ddr_t;
#else
#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
typedef struct ddr_cs_bnds {
u32 csbnds;
u8 res0[4];
@ -740,7 +644,7 @@ typedef struct immap {
u8 dll_lbc[0x100];
u8 res1[0xE00];
#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
struct ccsr_ddr ddr; /* DDR Memory Controller Memory */
#else
ddr83xx_t ddr; /* DDR Memory Controller Memory */
#endif

100
arch/powerpc/include/asm/immap_85xx.h
View file

@ -18,6 +18,7 @@
#include <asm/fsl_ifc.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_fman.h>
#include <fsl_immap.h>
typedef struct ccsr_local {
u32 ccsrbarh; /* CCSR Base Addr High */
@ -112,105 +113,6 @@ typedef struct ccsr_local_ecm {
u8 res24[492];
} ccsr_local_ecm_t;
/* DDR memory controller registers */
typedef struct ccsr_ddr {
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
u8 res1[4];
u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
u8 res2[4];
u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
u8 res3[4];
u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
u8 res4[100];
u32 cs0_config; /* Chip Select Configuration */
u32 cs1_config; /* Chip Select Configuration */
u32 cs2_config; /* Chip Select Configuration */
u32 cs3_config; /* Chip Select Configuration */
u8 res4a[48];
u32 cs0_config_2; /* Chip Select Configuration 2 */
u32 cs1_config_2; /* Chip Select Configuration 2 */
u32 cs2_config_2; /* Chip Select Configuration 2 */
u32 cs3_config_2; /* Chip Select Configuration 2 */
u8 res5[48];
u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
u32 sdram_cfg; /* SDRAM Control Configuration */
u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
u32 sdram_mode; /* SDRAM Mode Configuration */
u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
u32 sdram_md_cntl; /* SDRAM Mode Control */
u32 sdram_interval; /* SDRAM Interval Configuration */
u32 sdram_data_init; /* SDRAM Data initialization */
u8 res6[4];
u32 sdram_clk_cntl; /* SDRAM Clock Control */
u8 res7[20];
u32 init_addr; /* training init addr */
u32 init_ext_addr; /* training init extended addr */
u8 res8_1[16];
u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
u8 reg8_1a[8];
u32 ddr_zq_cntl; /* ZQ calibration control*/
u32 ddr_wrlvl_cntl; /* write leveling control*/
u8 reg8_1aa[4];
u32 ddr_sr_cntr; /* self refresh counter */
u32 ddr_sdram_rcw_1; /* Control Words 1 */
u32 ddr_sdram_rcw_2; /* Control Words 2 */
u8 reg_1ab[8];
u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
u8 res8_1b[104];
u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
u8 res8_1ba[0x908];
u32 ddr_dsr1; /* Debug Status 1 */
u32 ddr_dsr2; /* Debug Status 2 */
u32 ddr_cdr1; /* Control Driver 1 */
u32 ddr_cdr2; /* Control Driver 2 */
u8 res8_1c[200];
u32 ip_rev1; /* IP Block Revision 1 */
u32 ip_rev2; /* IP Block Revision 2 */
u32 eor; /* Enhanced Optimization Register */
u8 res8_2[252];
u32 mtcr; /* Memory Test Control Register */
u8 res8_3[28];
u32 mtp1; /* Memory Test Pattern 1 */
u32 mtp2; /* Memory Test Pattern 2 */
u32 mtp3; /* Memory Test Pattern 3 */
u32 mtp4; /* Memory Test Pattern 4 */
u32 mtp5; /* Memory Test Pattern 5 */
u32 mtp6; /* Memory Test Pattern 6 */
u32 mtp7; /* Memory Test Pattern 7 */
u32 mtp8; /* Memory Test Pattern 8 */
u32 mtp9; /* Memory Test Pattern 9 */
u32 mtp10; /* Memory Test Pattern 10 */
u8 res8_4[184];
u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
u8 res9[20];
u32 capture_data_hi; /* Data Path Read Capture High */
u32 capture_data_lo; /* Data Path Read Capture Low */
u32 capture_ecc; /* Data Path Read Capture ECC */
u8 res10[20];
u32 err_detect; /* Error Detect */
u32 err_disable; /* Error Disable */
u32 err_int_en;
u32 capture_attributes; /* Error Attrs Capture */
u32 capture_address; /* Error Addr Capture */
u32 capture_ext_address; /* Error Extended Addr Capture */
u32 err_sbe; /* Single-Bit ECC Error Management */
u8 res11[164];
u32 debug[32]; /* debug_1 to debug_32 */
u8 res12[128];
} ccsr_ddr_t;
#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */

74
arch/powerpc/include/asm/immap_86xx.h
View file

@ -10,6 +10,7 @@
#ifndef __IMMAP_86xx__
#define __IMMAP_86xx__
#include <fsl_immap.h>
#include <asm/types.h>
#include <asm/fsl_dma.h>
#include <asm/fsl_lbc.h>
@ -89,75 +90,6 @@ typedef struct ccsr_local_mcm {
char res31[488];
} ccsr_local_mcm_t;
/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
typedef struct ccsr_ddr {
uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
char res1[4];
uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
char res2[4];
uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
char res3[4];
uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
char res4[4];
uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */
char res5[4];
uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */
char res6[84];
uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
char res7[104];
uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
char res8[4];
uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
char res9[12];
uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
uint init_addr; /* 0x2148 - DDR training initialzation address */
uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */
char res10[2728];
uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
char res11[512];
uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
char res12[20];
uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
char res13[20];
uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */
uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
char res14[164];
uint debug_1; /* 0x2f00 */
uint debug_2;
uint debug_3;
uint debug_4;
uint debug_5;
char res15[236];
} ccsr_ddr_t;
/* Daul I2C Registers(0x3000-0x4000) */
typedef struct ccsr_i2c {
struct fsl_i2c i2c[2];
@ -1225,11 +1157,11 @@ typedef struct ccsr_wdt {
typedef struct immap {
ccsr_local_mcm_t im_local_mcm;
ccsr_ddr_t im_ddr1;
struct ccsr_ddr im_ddr1;
ccsr_i2c_t im_i2c;
ccsr_duart_t im_duart;
fsl_lbc_t im_lbc;
ccsr_ddr_t im_ddr2;
struct ccsr_ddr im_ddr2;
char res1[4096];
ccsr_pex_t im_pex1;
ccsr_pex_t im_pex2;

3
board/exmeritus/hww1u1a/hww1u1a.c
View file

@ -37,6 +37,7 @@ int checkboard(void)
unsigned int gpio_low = 0;
unsigned int gpio_in = 0;
unsigned int i;
struct ccsr_ddr __iomem *ddr;
puts("Board: HWW-1U-1A ");
@ -89,7 +90,7 @@ int checkboard(void)
* and delay a while before we continue.
*/
if (mpc85xx_gpio_get(GPIO_RESETS)) {
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
puts("Debugger detected... extra device reset enabled!\n");

3
board/freescale/bsc9131rdb/spl_minimal.c
View file

@ -20,7 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);

14
board/freescale/bsc9132qds/bsc9132qds.c
View file

@ -133,16 +133,16 @@ void dsp_ddr_configure(void)
*copy the ddr controller settings from PowerPC side DDR controller
*to the DSP DDR controller as connected DDR memories are similar.
*/
ccsr_ddr_t __iomem *pa_ddr =
(ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_ddr_t temp_ddr;
ccsr_ddr_t __iomem *dsp_ddr =
(ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
struct ccsr_ddr __iomem *pa_ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr temp_ddr;
struct ccsr_ddr __iomem *dsp_ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t));
memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t));
memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
}

3
board/freescale/bsc9132qds/spl_minimal.c
View file

@ -17,7 +17,8 @@ DECLARE_GLOBAL_DATA_PTR;
static void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if CONFIG_DDR_CLK_FREQ == 100000000
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);

2
board/freescale/mpc8536ds/mpc8536ds.c
View file

@ -90,7 +90,7 @@ int checkboard (void)
phys_size_t fixed_sdram (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
uint d_init;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;

3
board/freescale/mpc8540ads/mpc8540ads.c
View file

@ -168,7 +168,8 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

3
board/freescale/mpc8569mds/mpc8569mds.c
View file

@ -231,7 +231,8 @@ int checkboard (void)
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);

2
board/freescale/mpc8572ds/mpc8572ds.c
View file

@ -62,7 +62,7 @@ int checkboard (void)
phys_size_t fixed_sdram (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
uint d_init;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;

2
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View file

@ -143,7 +143,7 @@ phys_size_t fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
uint d_init;
ddr->cs0_bnds = 0x0000001f;

2
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View file

@ -64,7 +64,7 @@ fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

3
board/freescale/p1010rdb/spl_minimal.c
View file

@ -19,7 +19,8 @@ DECLARE_GLOBAL_DATA_PTR;
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 ddr_ratio;
unsigned long ddr_freq_mhz;

3
board/freescale/p1023rds/p1023rds.c
View file

@ -58,7 +58,8 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);

3
board/freescale/p2020ds/p2020ds.c
View file

@ -68,7 +68,8 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

3
board/sbc8548/ddr.c
View file

@ -91,7 +91,8 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
*/
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
out_be32(&ddr->cs0_bnds, 0x0000007f);
out_be32(&ddr->cs1_bnds, 0x008000ff);

6
board/sbc8641d/sbc8641d.c
View file

@ -93,7 +93,7 @@ long int fixed_sdram (void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
@ -111,7 +111,7 @@ long int fixed_sdram (void)
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
@ -142,7 +142,7 @@ long int fixed_sdram (void)
ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;

3
board/socrates/sdram.c
View file

@ -24,7 +24,8 @@
*/
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
/*
* Disable memory controller.

3
drivers/ddr/fsl/ctrl_regs.c
View file

@ -14,13 +14,14 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
#include <fsl_immap.h>
#include <asm/io.h>
#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
static u32 fsl_ddr_get_version(void)
{
ccsr_ddr_t *ddr;
struct ccsr_ddr __iomem *ddr;
u32 ver_major_minor_errata;
ddr = (void *)_DDR_ADDR;

6
drivers/ddr/fsl/mpc85xx_ddr_gen1.c
View file

@ -18,7 +18,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i;
volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@ -73,7 +74,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
void
ddr_enable_ecc(unsigned int dram_size)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);

3
drivers/ddr/fsl/mpc85xx_ddr_gen2.c
View file

@ -19,7 +19,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i;
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

2
drivers/ddr/fsl/mpc85xx_ddr_gen3.c
View file

@ -29,7 +29,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i, bus_width;
volatile ccsr_ddr_t *ddr;
struct ccsr_ddr __iomem *ddr;
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;

4
drivers/ddr/fsl/mpc86xx_ddr.c
View file

@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step)
{
unsigned int i;
volatile ccsr_ddr_t *ddr;
struct ccsr_ddr __iomem *ddr;
switch (ctrl_num) {
case 0:
@ -58,7 +58,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);

4
drivers/ddr/fsl/util.c
View file

@ -11,6 +11,7 @@
#include <div64.h>
#include <fsl_ddr.h>
#include <fsl_immap.h>
#include <asm/io.h>
/* To avoid 64-bit full-divides, we factor this here */
@ -134,7 +135,8 @@ u32 fsl_ddr_get_intl3r(void)
void board_add_ram_info(int use_default)
{
ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);

112
include/fsl_immap.h Normal file
View file

@ -0,0 +1,112 @@
/*
* Common internal memory map for some Freescale SoCs
*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSL_IMMAP_H
#define __FSL_IMMAP_H
/*
* DDR memory controller registers
* This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
*/
struct ccsr_ddr {
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
u8 res_04[4];
u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
u8 res_0c[4];
u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
u8 res_14[4];
u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
u8 res_1c[100];
u32 cs0_config; /* Chip Select Configuration */
u32 cs1_config; /* Chip Select Configuration */
u32 cs2_config; /* Chip Select Configuration */
u32 cs3_config; /* Chip Select Configuration */
u8 res_90[48];
u32 cs0_config_2; /* Chip Select Configuration 2 */
u32 cs1_config_2; /* Chip Select Configuration 2 */
u32 cs2_config_2; /* Chip Select Configuration 2 */
u32 cs3_config_2; /* Chip Select Configuration 2 */
u8 res_d0[48];
u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
u32 sdram_cfg; /* SDRAM Control Configuration */
u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
u32 sdram_mode; /* SDRAM Mode Configuration */
u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
u32 sdram_md_cntl; /* SDRAM Mode Control */
u32 sdram_interval; /* SDRAM Interval Configuration */
u32 sdram_data_init; /* SDRAM Data initialization */
u8 res_12c[4];
u32 sdram_clk_cntl; /* SDRAM Clock Control */
u8 res_134[20];
u32 init_addr; /* training init addr */
u32 init_ext_addr; /* training init extended addr */
u8 res_150[16];
u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
u8 reg_168[8];
u32 ddr_zq_cntl; /* ZQ calibration control*/
u32 ddr_wrlvl_cntl; /* write leveling control*/
u8 reg_178[4];
u32 ddr_sr_cntr; /* self refresh counter */
u32 ddr_sdram_rcw_1; /* Control Words 1 */
u32 ddr_sdram_rcw_2; /* Control Words 2 */
u8 reg_188[8];
u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
u8 res_198[104];
u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
u8 res_218[0x908];
u32 ddr_dsr1; /* Debug Status 1 */
u32 ddr_dsr2; /* Debug Status 2 */
u32 ddr_cdr1; /* Control Driver 1 */
u32 ddr_cdr2; /* Control Driver 2 */
u8 res_b30[200];
u32 ip_rev1; /* IP Block Revision 1 */
u32 ip_rev2; /* IP Block Revision 2 */
u32 eor; /* Enhanced Optimization Register */
u8 res_c04[252];
u32 mtcr; /* Memory Test Control Register */
u8 res_d04[28];
u32 mtp1; /* Memory Test Pattern 1 */
u32 mtp2; /* Memory Test Pattern 2 */
u32 mtp3; /* Memory Test Pattern 3 */
u32 mtp4; /* Memory Test Pattern 4 */
u32 mtp5; /* Memory Test Pattern 5 */
u32 mtp6; /* Memory Test Pattern 6 */
u32 mtp7; /* Memory Test Pattern 7 */
u32 mtp8; /* Memory Test Pattern 8 */
u32 mtp9; /* Memory Test Pattern 9 */
u32 mtp10; /* Memory Test Pattern 10 */
u8 res_d48[184];
u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
u8 res_e0c[20];
u32 capture_data_hi; /* Data Path Read Capture High */
u32 capture_data_lo; /* Data Path Read Capture Low */
u32 capture_ecc; /* Data Path Read Capture ECC */
u8 res_e2c[20];
u32 err_detect; /* Error Detect */
u32 err_disable; /* Error Disable */
u32 err_int_en;
u32 capture_attributes; /* Error Attrs Capture */
u32 capture_address; /* Error Addr Capture */
u32 capture_ext_address; /* Error Extended Addr Capture */
u32 err_sbe; /* Single-Bit ECC Error Management */
u8 res_e5c[164];
u32 debug[32]; /* debug_1 to debug_32 */
u8 res_f80[128];
};
#endif /* __FSL_IMMAP_H */

3
nand_spl/board/freescale/p1023rds/nand_boot.c
View file

@ -18,7 +18,8 @@ DECLARE_GLOBAL_DATA_PTR;
/* Fixed sdram init -- doesn't use serial presence detect. */
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);