mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 00:21:06 +00:00
i.MX6: mx6qsabrelite: Add splash screen support
Adds support for HDMI, two LVDS panels and one RGB panel to
the SABRE-Lite board.
Displays supported:
HDMI - 1024 x 768 for maximum compatibility
Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
Since the ipuv3_fb display driver currently supports only a single display,
this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
or the I2C touch controller of the LVDS and RGB displays in the priority
listed above.
Setting 'panel' environment variable to one of the names above will
override auto-detection.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This commit is contained in:
Eric Nelson
Stefano Babic
parent
f95c960bcc
commit
e58010b554
2 changed files with 343 additions and 1 deletions
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@ -36,6 +36,12 @@
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#include <micrel.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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@ -375,14 +381,337 @@ int setup_sata(void)
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}
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#endif
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#if defined(CONFIG_VIDEO_IPUV3)
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static iomux_v3_cfg_t const backlight_pads[] = {
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/* Backlight on RGB connector: J15 */
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MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
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#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
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/* Backlight on LVDS connector: J6 */
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MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
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#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
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};
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static iomux_v3_cfg_t const rgb_pads[] = {
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MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
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MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
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MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
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MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
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MX6Q_PAD_DI0_PIN4__GPIO_4_20,
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MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
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MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
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MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
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MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
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MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
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MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
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MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
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MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
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MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
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MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
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MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
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MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
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MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
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MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
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MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
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MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
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MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
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MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
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MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
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MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
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MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
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MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
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MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
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MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
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};
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struct display_info_t {
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int bus;
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int addr;
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int pixfmt;
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int (*detect)(struct display_info_t const *dev);
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void (*enable)(struct display_info_t const *dev);
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struct fb_videomode mode;
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};
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static int detect_hdmi(struct display_info_t const *dev)
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{
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return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD;
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}
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static void enable_hdmi(struct display_info_t const *dev)
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{
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u8 reg;
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printf("%s: setup HDMI monitor\n", __func__);
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reg = __raw_readb(
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HDMI_ARB_BASE_ADDR
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+HDMI_PHY_CONF0);
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reg |= HDMI_PHY_CONF0_PDZ_MASK;
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__raw_writeb(reg,
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HDMI_ARB_BASE_ADDR
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+HDMI_PHY_CONF0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
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__raw_writeb(reg,
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HDMI_ARB_BASE_ADDR
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+HDMI_PHY_CONF0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
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__raw_writeb(reg,
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HDMI_ARB_BASE_ADDR
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+HDMI_PHY_CONF0);
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__raw_writeb(HDMI_MC_PHYRSTZ_ASSERT,
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HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
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}
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static int detect_i2c(struct display_info_t const *dev)
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{
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return ((0 == i2c_set_bus_num(dev->bus))
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&&
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(0 == i2c_probe(dev->addr)));
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}
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static void enable_lvds(struct display_info_t const *dev)
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{
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struct iomuxc *iomux = (struct iomuxc *)
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IOMUXC_BASE_ADDR;
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u32 reg = readl(&iomux->gpr[2]);
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reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
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writel(reg, &iomux->gpr[2]);
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gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
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}
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static void enable_rgb(struct display_info_t const *dev)
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{
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imx_iomux_v3_setup_multiple_pads(
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rgb_pads,
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ARRAY_SIZE(rgb_pads));
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gpio_direction_output(RGB_BACKLIGHT_GP, 1);
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}
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static struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} }, {
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.bus = 2,
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.addr = 0x4,
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.pixfmt = IPU_PIX_FMT_LVDS666,
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.detect = detect_i2c,
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.enable = enable_lvds,
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.mode = {
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.name = "Hannstar-XGA",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} }, {
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.bus = 2,
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.addr = 0x38,
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.pixfmt = IPU_PIX_FMT_LVDS666,
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.detect = detect_i2c,
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.enable = enable_lvds,
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.mode = {
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.name = "wsvga-lvds",
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.refresh = 60,
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.xres = 1024,
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.yres = 600,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} }, {
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.bus = 2,
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.addr = 0x48,
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.pixfmt = IPU_PIX_FMT_RGB666,
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.detect = detect_i2c,
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.enable = enable_rgb,
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.mode = {
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.name = "wvga-rgb",
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.refresh = 57,
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.xres = 800,
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.yres = 480,
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.pixclock = 37037,
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.left_margin = 40,
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.right_margin = 60,
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.upper_margin = 10,
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.lower_margin = 10,
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.hsync_len = 20,
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.vsync_len = 10,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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int board_video_skip(void)
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{
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int i;
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int ret;
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char const *panel = getenv("panel");
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if (!panel) {
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for (i = 0; i < ARRAY_SIZE(displays); i++) {
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struct display_info_t const *dev = displays+i;
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if (dev->detect(dev)) {
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panel = dev->mode.name;
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printf("auto-detected panel %s\n", panel);
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break;
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}
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}
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if (!panel) {
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panel = displays[0].mode.name;
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printf("No panel detected: default to %s\n", panel);
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}
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} else {
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for (i = 0; i < ARRAY_SIZE(displays); i++) {
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if (!strcmp(panel, displays[i].mode.name))
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break;
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}
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}
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if (i < ARRAY_SIZE(displays)) {
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ret = ipuv3_fb_init(&displays[i].mode, 0,
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displays[i].pixfmt);
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if (!ret) {
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displays[i].enable(displays+i);
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printf("Display: %s (%ux%u)\n",
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displays[i].mode.name,
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displays[i].mode.xres,
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displays[i].mode.yres);
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} else
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printf("LCD %s cannot be configured: %d\n",
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displays[i].mode.name, ret);
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} else {
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printf("unsupported panel %s\n", panel);
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ret = -EINVAL;
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}
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return (0 != ret);
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}
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int reg;
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/* Turn on LDB0,IPU,IPU DI0 clocks */
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reg = __raw_readl(&mxc_ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
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|MXC_CCM_CCGR3_LDB_DI0_MASK;
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writel(reg, &mxc_ccm->CCGR3);
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/* Turn on HDMI PHY clock */
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reg = __raw_readl(&mxc_ccm->CCGR2);
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reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
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|MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
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writel(reg, &mxc_ccm->CCGR2);
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/* clear HDMI PHY reset */
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__raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT,
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HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
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/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
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writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
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writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
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/* set LDB0, LDB1 clk select to 011/011 */
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reg = readl(&mxc_ccm->cs2cdr);
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
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|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
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reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
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|(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->cs2cdr);
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reg = readl(&mxc_ccm->cscmr2);
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reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
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writel(reg, &mxc_ccm->cscmr2);
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reg = readl(&mxc_ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
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|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
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|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
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|(CHSCCDR_PODF_DIVIDE_BY_3
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<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
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|(CHSCCDR_IPU_PRE_CLK_540M_PFD
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<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
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|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
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|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
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|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
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|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
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|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
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|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
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|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
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|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
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writel(reg, &iomux->gpr[2]);
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reg = readl(&iomux->gpr[3]);
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reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
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| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
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<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
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writel(reg, &iomux->gpr[3]);
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/* backlights off until needed */
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imx_iomux_v3_setup_multiple_pads(backlight_pads,
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ARRAY_SIZE(backlight_pads));
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gpio_direction_input(LVDS_BACKLIGHT_GP);
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gpio_direction_input(RGB_BACKLIGHT_GP);
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_buttons();
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#if defined(CONFIG_VIDEO_IPUV3)
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setup_display();
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#endif
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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@ -37,7 +37,7 @@
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#define CONFIG_REVISION_TAG
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_MISC_INIT_R
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@ -119,6 +119,19 @@
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/* Miscellaneous commands */
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#define CONFIG_CMD_BMODE
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/* Framebuffer and LCD */
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 260000000
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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