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T4/serdes: fix the serdes clock frequency
Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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1 changed files with 2 additions and 2 deletions
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@ -110,7 +110,7 @@ int checkboard(void)
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for (i = 0; i < MAX_SERDES; i++) {
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static const char *freq[] = {
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"100", "125", "156.25", "161.1328125"};
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unsigned int clock = (sw >> (2 * i)) & 3;
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unsigned int clock = (sw >> (6 - 2 * i)) & 3;
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printf("SERDES%u=%sMHz ", i+1, freq[clock]);
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}
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@ -357,7 +357,7 @@ int misc_init_r(void)
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sw = QIXIS_READ(brdcfg[2]);
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for (i = 0; i < MAX_SERDES; i++) {
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unsigned int clock = (sw >> (2 * i)) & 3;
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unsigned int clock = (sw >> (6 - 2 * i)) & 3;
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switch (clock) {
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case 0:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
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