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powerpc/corenet_ds: Update DDR timing for single-rank DIMMs

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Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun 2012-10-26 16:40:14 +00:00 committed by Andy Fleming
parent 0118033b67
commit 765ad3cf4d
1 changed files with 2 additions and 2 deletions
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4
board/freescale/corenet_ds/ddr.c
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@ -139,8 +139,8 @@ static const struct board_specific_parameters udimm0[] = {
{2, 1250, 4, 6, 0xff, 2, 0},
{2, 1350, 5, 7, 0xff, 2, 0},
{2, 1666, 5, 8, 0xff, 2, 0},
{1, 850, 4, 5, 0xff, 2, 0},
{1, 950, 4, 7, 0xff, 2, 0},
{1, 1250, 4, 6, 0xff, 2, 0},
{1, 1335, 4, 7, 0xff, 2, 0},
{1, 1666, 4, 8, 0xff, 2, 0},
{}
};