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imx: mx6qsabreauto: support lvds display
Move setup_display from board_early_init_f to board_init. Add more clock settings. Add blacklight iomux setting. Add display_info_t info for the lvds screen. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
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aee3fddb67
commit
ccf4326bac
1 changed files with 84 additions and 3 deletions
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@ -412,12 +412,42 @@ u32 get_board_rev(void)
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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static void disable_lvds(struct display_info_t const *dev)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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clrbits_le32(&iomux->gpr[2],
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IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
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IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
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}
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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disable_lvds(dev);
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imx_enable_hdmi_phy();
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}
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struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB666,
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.detect = NULL,
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.enable = NULL,
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.mode = {
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.name = "Hannstar-XGA",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} }, {
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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@ -440,18 +470,69 @@ struct display_info_t const displays[] = {{
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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iomux_v3_cfg_t const backlight_pads[] = {
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MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static void setup_iomux_backlight(void)
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{
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gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
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imx_iomux_v3_setup_multiple_pads(backlight_pads,
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ARRAY_SIZE(backlight_pads));
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}
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int reg;
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setup_iomux_backlight();
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enable_ipu_clock();
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imx_setup_hdmi();
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/* Turn on LDB_DI0 and LDB_DI1 clocks */
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reg = readl(&mxc_ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
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writel(reg, &mxc_ccm->CCGR3);
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/* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
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reg = readl(&mxc_ccm->cs2cdr);
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
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MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
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reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
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(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->cs2cdr);
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reg = readl(&mxc_ccm->cscmr2);
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reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
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writel(reg, &mxc_ccm->cscmr2);
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reg = readl(&mxc_ccm->chsccdr);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
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MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
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IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
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IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
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IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
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IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
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IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
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writel(reg, &iomux->gpr[2]);
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reg = readl(&iomux->gpr[3]);
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reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
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IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
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reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
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IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
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(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
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IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
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writel(reg, &iomux->gpr[3]);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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@ -467,9 +548,6 @@ int overwrite_console(void)
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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#ifdef CONFIG_VIDEO_IPUV3
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setup_display();
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#endif
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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@ -494,6 +572,9 @@ int board_init(void)
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gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
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imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
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#ifdef CONFIG_VIDEO_IPUV3
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setup_display();
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#endif
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setup_iomux_eimnor();
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return 0;
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}
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