The generic code in common/spl/spl.c allows TPL/SPL banners to be
silenced by unsetting CONFIG_TPL_BANNER_PRINT or CONFIG_SPL_BANNER_PRINT
respectively. However, arch/arm/mach-rockchip/tpl.c prints this banner
unconditionally.
Fix the rockchip-specific tpl.c so that the TPL banner depends on
CONFIG_TPL_BANNER_PRINT in the same way as the generic code.
Signed-off-by: <chris@arachsys.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
If CONFIG_DEBUG_UART is set but CONFIG_TPL_SERIAL_SUPPORT is not, the
serial output should be available in SPL and full U-Boot, but not built
in TPL. However, the rockchip tpl.c instead fails to compile with
undefined references to the debug UART.
Instead, initialise the debug UART and print the TPL banner only if both
CONFIG_DEBUG_UART and CONFIG_TPL_SERIAL_SUPPORT are set.
Signed-off-by: <chris@arachsys.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
For STM32 QSPI driver, "st,stm32-qspi" compatible string was first
introduced in U-boot. But later in kernel side, "st,stm32f469-qspi"
was used.
To simplify, align U-boot QSPI compatible string with kernel one.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
For STM32 QSPI driver, "st,stm32-qspi" compatible string was first
introduced in U-boot. But later in kernel side, "st,stm32f469-qspi"
was used.
To simplify, align U-boot QSPI compatible string with kernel one.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add the following functions to translate DMA address to CPU address:
- dev_translate_dma_address()
- ofnode_translate_dma_address()
- of_translate_dma_address()
- fdt_translate_dma_address()
These functions work the same way as xxx_translate_address(), with the
difference that the translation relies on the "dma-ranges" property
instead of the "ranges" property.
Add related test. Test report:
=> ut dm fdt_translation
Test: dm_test_fdt_translation: test-fdt.c
Test: dm_test_fdt_translation: test-fdt.c (flat tree)
Failures: 0
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
- rk3399 lpddr4 support
- rk3399-rock960 board support improvement
- Eliminate pyelftools dependency by make_fit_atf.py
- clean up rockchip dts to use -u-boot.dtsi
- use ARM arch/generic timer instead of rk_timer
- clean up Kconfig options for board support
This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga
to a UCLASS_SYSRESET based dm driver.
A side effect is that gen5 and a10 can now select between cold and warm
reset.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This adds a define for the bit in rstmgr's ctrl regiser that issues
a cold reset (we had a define for the warm reset bit only) in preparation
for a proper sysrese driver.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Series changes: 2
- separate this patch to the register descriptions from the actual
sysreset driver patch
make_fit_aft.py depends on the non-standard library pyelftools to pull
out PT_LOAD segments from ELF files. However, this is as easy to do
manually, without imposing the extra dependency on users.
Structures in the ELF file are unpacked into variables named to exactly
match the ELF spec to ensure the destructuring code is reasonably
self-documenting.
Signed-off-by: Chris Webb <chris@arachsys.com>
Reviewed-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
SPL/TPL share the same secure_timer_init(), update to use
one copy source code and update to use CONFIG_ROCKCHIP_STIMER_BASE
as base address and rename to function name to rockchip_stimer_init().
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
common board is a basic TPL board init which can be shared for most
of SoCs to avoid copy-pase for different SoCs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The SoC related init will move to SPL and keep TPL clean,
so that we can reuse the common TPL board file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We have convert all SoC to use DM timer or ARM arch/generic
timer, we can remove this rk_timer now.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track the boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We share the same default SPL boot order for all rk3288 boards,
use dts instead of hard code in board file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The fdt interfaces are actuall depends on OF_LIBFDT instead
of OF_CONTROL, some boards may enable OF_CONTROL while disable
OF_LIBFDT.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The rk3288-firefly board have different setting for sdmmc
io, sync then from kernel mainline:
6fbc7275c7a9 Linux 5.2-rc7
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Add arch_cpu_init() in SPL for soc related init, and
move configure_l2ctlr() into it.
The arch_cpu_init() only need to run once, so no need
to run in TPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip SoCs have different ROCKCHIP_BOOT_MODE_REG value,
move it to SoC's own Kconfig, and add address for rk3128 and
rk3328 so that all SoCs have available address.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use LPDDR4-100 sdram timings dtsi for RockPI-4 board.
All these timings are processed during TPL stage of rock-pi-4 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.
Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.
Bootchain after and before this change are:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Use LPDDR4-100 sdram timings dtsi for Rockpro64 board.
All these timings are processed during TPL stage of rockpro64 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file.
all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin
Associated LPDDR4 board -u-boot.dtsi can include this to make these
timings available during SPL or TPL stages.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi
so-that SPL can access pmu.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add pmu compatible with relevant U_BOOT_DRIVER for rk3399
via syscon rk3399 driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add pmu header file for rk3399 SoC, this will help
to configure pmu in sdram driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add DdrMode structure with associated bit fields.
These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add DdrTimingC0 structure with associated bit fields.
These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add dram config macro for handling ddr version number.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
cs0_row, cs1_row and cs1_col needs more bits to show its
correct value, update to make use of both sys_reg2,
sys_reg3.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash similar patches into one patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
Add simplified and meaningful macro for all setting.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash the similar patches into 1 patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>
For a single binary approach for imx6 quad/dual/duallite/solo it
is necessary to enable CONFIG_SATA for quad/dual. On the other hand
on imx6 duallite/sole SATA is not available.
Therefore sata_remove() is skipped according to a blacklist scheme.
Adding further imx derivates is probably not recessary as they are
usually not pin-compatible and therefore a different board with its
own configuration.
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
According to iMX6DQ RM, the minor field (low 8 bits) in DIGPROG is not
aligned on silicon revision 1.3. So update get_cpu_rev to correct the
revision.
0x00630002 Silicon revision 1.2
0x00630005 Silicon revision 1.3
0x00630006 Silicon revision 1.6
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This device tree adds support for DHCOM iMX6 duallite and solo
deriviates.
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
To use the device tree definitions imx6q-dhcom-som.dtsi for all imx6 derivatives rename
it to imx6qdl-dhcom.dtsi. We omit the '-som', because it simplifies further mainlinening
of already existing device trees.
To reuse board level common stuff imx6qdl-dhcom-pdk2.dtsi is created and included by
imx6q-dhcom-pdk2.dts.
Signed-off-by Ludwig Zenz <lzenz@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
The gpio command currently uses equal bank names "GPIO0_"
for all existing gpio banks, i. e.:
U-Boot# gpio status -a
Bank GPIO0_:
GPIO0_0: input: 0 [ ]
GPIO0_1: output: 1 [x] dbg1.gpios
...
Bank GPIO0_:
GPIO0_0: input: 0 [ ]
GPIO0_1: input: 0 [ ]
...
So the command is broken, it is not possible to address
a desired bank. Add gpio aliases to fix this.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
New imx8 boards started adding duplicated UART init code.
Factor out this to common function sc_pm_setup_uart().
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This file setups UART5 based serial to be used as pre-relocation
console in the U-Boot proper.
On purpose pinux configuration is omitted here as it has been already
done in SPL. For early pre-relocation code we only need the serial
device from DTS.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit ports from Linux kernel - tag: v5.1 - the device tree
description for display5 board.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Those properties are U-Boot specific as the mxs gpio Linux driver (up to
version v5.1.11) is not supporting them.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch copies from the Linux kernel stable (tag v5.1.11)
SHA1: 17bb763e7eaf i.MX28 related device tree files.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Currently, when the spl_boot_device checks the boot device, it
will only return MMC1 when it's either sd or eMMC regardless
of whether or not it's MMC1 or MMC2. This is a problem when
booting from MMC2 if MMC isn't being manually configured like in
the DM_SPL case with SPL_OF_CONTROL.
This patch will check the register and return either MMC1 or MMC2.
Signed-off-by: Adam Ford <aford173@gmail.com>
Writing/updating boot image in nand device is not
straight forward in i.MX6 platform and it requires
boot control block(BCB) to be configured.
It becomes difficult to use uboot 'nand' command to
write BCB since it requires platform specific attributes
need to be taken care of.
It is even difficult to use existing msx-nand.c driver by
incorporating BCB attributes like mxs_dma_desc does
because it requires change in mtd and nand command.
So, cmd_nandbcb implemented in arch/arm/mach-imx
BCB contains two data structures, Firmware Configuration Block(FCB)
and Discovered Bad Block Table(DBBT). FCB has nand timings,
DBBT search area, page address of firmware.
On summary, nandbcb update will
- erase the entire partition
- create BCB by creating 2 FCB/DBBT block followed by
1 FW block based on partition size and erasesize.
- fill FCB/DBBT structures
- write FW/SPL on FW1
- write FCB/DBBT in first 2 blocks
for nand boot, up on reset bootrom look for FCB structure in
first block's if FCB found the nand timings are loaded for
further reads. once FCB read done, DTTB will load and finally
firmware will be loaded which is boot image.
Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage
information.
Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
This patch provides code to implement the CCF clock tree in sandbox. It
uses all the introduced primitives; some generic ones are reused, some
sandbox specific were developed.
In that way (after introducing the real CCF tree in sandbox) the recently
added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested
in their natural work environment.
Usage (sandbox_defconfig and sandbox_flattree_defconfig):
./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf"
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This patch adds the 'osc' fixed clock to facilitate the CCF testing in
the sandbox U-Boot. It is a starting point for building CCF hierarchy of
clocks.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add code to print the channel stride, this would help to
print the stride of associated channel.
Here is sample print on LPDDR4, 50MHz.
256B stride
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add sdram ddr info print support, this would help to
observe the sdram base parameters.
Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add sdram driver to handle debug across rockchip SoCs.
This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add DDR4 enum number in common header.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
dramtype enum numbers as common across all dram controllers
in rockchip, so move the eneum values in common header.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Move common sdram structures like sdram_cap_info, sdram_base_params
into sdram_common header, this would help to reuse the same
from another controllers like px30.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Most of the ddr parameters are common in rk3399_base_params
structure and which would reuse it in another controller like
px30 in future.
So, rename the structure from rk3399_base_params into
sdram_base_params.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Group common ddr attributes like
- rank
- col
- bk
- bw
- dbw
- row_3_4
- cs0_row
- cs1_row
- ddrconfig
into a common cap_info structure for more code readability and extend
if possible based on the new features.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Let the board continue boot from the storage device where
it bootup.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
RK3399 use sdhci for eMMC and DW MMC for SD Card, and
spl will only try to boot from SDMMC if we don't specify
other boot device for spl-boot-order. So add sdhci and sdmmc
for spl-boot-order here.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync the dts files for the Rock960 boards from Linux to get the
latest changes and fixes for the devices.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Adds a test using a makeshift MDIO MUX. The test is based on the existing
MDIO test. It uses the last emulated PHY register to verify MUX selection.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Various FS/disk related fixes with security implications.
- Proper fix for the pci_ep test.
- Assorted bugfixes
- Some MediaTek updates.
- 'env erase' support.
The timer0 node has its two clocks written in reversed order. The timer0
is used as the tick timer which causes a problem that the time a delay
function used is 4 times longer.
This patch reverses these two clocks to solve this issue.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch sets CNTVOFF of ARM CP15 timer to zero to make sure the virtual
counter is fully usable for linux kernel.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
If U-Boot is loaded and started from TF-A (you need to change
SYS_TEXT_BASE to 0x60000000), it will hang up at flash initialization.
If secure mode is off (default, or -machine virt,secure=off) at qemu,
it will provide dtb with two flash memory banks:
flash@0 {
bank-width = <0x4>;
reg = <0x0 0x0 0x0 0x4000000 0x0 0x4000000 0x0 0x4000000>;
compatible = "cfi-flash";
};
If secure mode is on, on the other hand, qemu provides dtb with 1 bank:
flash@0 {
bank-width = <0x4>;
reg = <0x0 0x4000000 0x0 0x4000000>;
compatible = "cfi-flash";
};
As a result, flash_init()/flash_get_size() will eventually fail.
With this patch applied, relevant CONFIG values are modified.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Currently, CONFIG_TFABOOT is located in armv8/fsl-layerscape Kconfig,
but it will be also useful for other targets if some additional
configuration are necessary.
So move it to arch/arm/Kconfig.
Please note that CONFIG_TFABOOT still depends on
CONFIG_ARCH_SUPPORT_TFABOOT and so the menu won't come up
if any target doesn't need its own customization for TF-A boot.
This will maintain the compatibility.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Sriram Dash <sriram.dash@nxp.com>
Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Cc: Peng Ma <peng.ma@nxp.com>
Cc: Yuantian Tang <andy.tang@nxp.com>
Cc: Pankit Garg <pankit.garg@nxp.com>
When a crash occurs in thumb mode the crash dump is incorrect. This is due
to the usage of a non-existing configuration variable CONFIG_ARM_THUMB in
the definition of macro thumb_mode(regs).
Use CONFIG_IS_ENABLED(SYS_THUMB_BUILD) to detect that the code has been
compiled for thumb mode. Remove ARM_THUMB from config_whitelist.txt.
With the patch crash dumps indicate thumb mode correctly.
On a system with thumb mode:
=> exception unaligned
data abort
pc : [<8f7a2b52>] lr : [<8f7ab1ef>]
reloc pc : [<1780cb52>] lr : [<178151ef>]
sp : 8ed8c3f8 ip : 8f7a2b4d fp : 00000002
r10: 8f7f8228 r9 : 8ed95ea8 r8 : 8ed99488
r7 : 8f7ab141 r6 : 00000000 r5 : 8ed8c3f9 r4 : 8f7f6390
r3 : 8ed9948c r2 : 00000001 r1 : 00000000 r0 : 8f7f6390
Flags: nzCv IRQs off FIQs off Mode SVC_32 (T)
Code: 8f7e 466d f105 0501 (e9d5) 6700
The Flags line has '(T)' and in the Code line the output is in u16 groups.
On a system without thumb mode:
=> exception breakpoint
prefetch abort
pc : [<7ff5a5c8>] lr : [<7ff675ec>]
reloc pc : [<0000e5c8>] lr : [<0001b5ec>]
sp : 7ee0ad80 ip : 7ff5a5cc fp : 7ff674cc
r10: 00000002 r9 : 7ef0bed8 r8 : 7ffd6214
r7 : 7ef0e080 r6 : 00000000 r5 : 7ffd4090 r4 : 00000000
r3 : 7ef0e084 r2 : 00000001 r1 : 00000000 r0 : 7ffd4090
Flags: nzCv IRQs off FIQs off Mode SVC_32
Code: e1a0500d e2855001 e1c560d0 e3a00001 (e12fff1e)
The Flags line does not show '(T)' and in the Code line the output is in
u32 groups.
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
The TI AM654x EVM base board and the associated daughtercards have on-
board I2C-based EEPROMs containing board configuration data. Use the
board detection infrastructure introduced earlier to do the following:
1) Parse the AM654x EVM base board EEPROM and populate items like board
name and MAC addresses into the TI common EEPROM data structure
residing in SRAM scratch space
2) Check for presence of daughter card(s) by probing the associated
presence signals via an I2C-based GPIO expander. Then, if such a
card is found, parse the data such as additional Ethernet MAC
addresses from its on-board EEPROM and populate into U-Boot
accordingly
3) Dynamically create an U-Boot ENV variable called overlay_files
containing a list of daugherboard-specific DTB overlays based on
daughercards found.
This patch adds support for the AM654x base board ("AM6-COMPROCEVM")
as well as for the IDK ("AM6-IDKAPPEVM"), OLDI LCD ("OLDI-LCD1EVM")
PCIe/USB3.0 ("SER-PCIEUSBEVM"), 2 Lane PCIe/USB2.0 ("SER-PCIE2LEVM"),
and general purpuse ("AM6-GPAPPEVM") daughtercards.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The board detection scheme employed on various TI EVMs makes use of
SRAM scratch space to share data read from an on-board EEPROM between
the different bootloading stages. Map the associated definition that's
used to locate this data into the SRAM scratch space we use on AM654x.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
The AM654 base board has a TCA9554/PCA9554-type GPIO expander on the
wkup_i2c0 bus at address 0x38 that is used to detect the presence of
daughter cards. Add a respective DTS description of this expander
to enable its use.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
To enable the use of an EEPROM-based board detection scheme we need to
be able to access the I2C bus associated with the EEPROMs across all
3 stages of U-Boot: R5 SPL, A53 SPL, and A53 U-Boot (proper). So go
ahead and add/update the wkup_i2c0 peripheral module DTS definitions
and its associated pinmux node accordingly.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Only U-Boot specifc DT properties or overrides, must be in -u-boot.dtsi.
Pinctrl nodes does not belong here. Now that pinctrl nodes are in kernel
DT, there is no reason to be keep these in -u-boot.dtsi. Move them to
proper places so that it would ease copying DT entries from kernel DT.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
There is no need for to include this header here, so drop it.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Use the System Firmware (SYSFW) loader framework to load and start
the SYSFW as part of the AM654 early initialization sequence. While
at it also initialize the WKUP_UART0 pinmux as it is used by SYSFW
to print diagnostic messages.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Introduce a framework that allows loading the System Firmware (SYSFW)
binary as well as the associated configuration data from an image tree
blob named "sysfw.itb" from an FS-based MMC boot media or from an MMC
RAW mode partition or sector.
To simplify the handling of and loading from the different boot media
we tap into the existing U-Boot SPL framework usually used for loading
U-Boot by building on an earlier commit that exposes some of that
functionality.
Note that this initial implementation only supports FS and RAW-based
eMMC/SD card boot.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On some platform we have sufficient memory available early on to allow
setting up and using a basic BSS prior to entering board_init_f(). Doing
so can for example be used to carry state over to board_init_r() without
having to resort to extending U-Boot's global data structure.
To support such scenarios add a Kconfig option called CONFIG_SPL_EARLY_BSS
to allow moving the initialization of BSS prior to entering board_init_f(),
if enabled. Note that using this option usually should go along with using
CONFIG_SPL_SEPARATE_BSS and configuring BSS to be located in memory
actually available prior to board_init_f().
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
With changes in the driver requiring phy related properties,
add the same for the SD card node to prevent breaking boot with
the driver update.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sync the sdhci0 node from kernel. This changes the compatible that is
required to be there in the driver. Change the same for the SD card node
which is not yet supported in kernel. This also syncs the main_pmx0 node
as a side effect.
Also change the name of the driver to match the compatible in kernel.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
We should use predefined constants instead of magic numbers.
Move some constant definitions from include/pe.h to
include/asm-generic/pe.h.
Use these constants in crt0_*_efi.S.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
So far USB was not enabled for the Allwinner H6 boards, as the PHY
driver was not ready and the clock gates were missing. Since this is now
fixed, let's add the PHY and the OHCI/EHCI drivers to the build, for
all existing H6 boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Probably for no particular reason SUNXI_GPIO was still defined the "old
way", in header files only.
Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove
another line from our dreadful config_whitelist.txt.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add some basic line delay values to be used with DDR3 DRAM chips on
some H6 TV boxes.
Taken from a register dump after boot0 initialised the DRAM.
Put them as the default delay values for DDR3 DRAM until we know better.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add a routine to program the timing parameters for DDR3-1333 DRAM chips
connected to the H6 DRAM controller.
The values were gathered from doing back-calculations from a register
dump, trying to match them up with the official JEDEC DDDR3 spec.
If in doubt, the register dump values were taken for now, but the JEDEC
recommendation were added as a comment.
Many thanks to Jernej for contributing fixes!
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
At the moment the H6 DRAM driver only supports LPDDR3 DRAM.
Extend the driver to cover DDR3 DRAM as well.
The changes are partly motivated by looking at the ZynqMP register
documentation, partly by looking at register dumps after boot0/libdram
has initialised the controller.
Many thanks to Jernej for contributing some fixes!
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM.
Split the timing parameters for this LPDDR3 configuration into a
separate file, to allow selecting an alternative later at compile time
(as the sunxi-dw driver does).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The DRAM controller manual suggests to first program the PHY
initialisation parameters to the PHY_PIR register, and then set bit 0 to
trigger the initialisation. This is also used in boot0.
Follow this recommendation by setting bit 0 in a separate step.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Using memcpy() is, however tempting, not a good idea: It depends on the
specific implementation of memcpy, also lacks barriers. In this
particular case the first registers were written using 64-bit writes,
and the last register using four separate single-byte writes.
Replace the memcpy with a proper loop using the writel() accessor.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add mcu cpsw and its components along with scm_conf node
to have ethernet functional.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
A very simple test for DM_MDIO, mimicks a register write/read through the
sandbox bus to a dummy PHY.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a
dual colour LED and an optical S/PDIF connector.
Linux commit details about the sun8i-h3-beelink-x2.dts sync:
"ARM: dts: sun8i: h3: Add ethernet0 alias to Beelink X2"
(sha1: cc4bddade114b696ab27c1a77cfc7040151306da)
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Since we have limited resources in SPL, it is the best interest
to keep the SPL as small as possible and that includes the DTB.
There are a few items in the device tree that can be removed,
because these boards don't use them.
Signed-off-by: Adam Ford <aford173@gmail.com>
The MMC card-detect pin was incorrectly defined which was fixed.
This patch resync's the dts and removes the u-boot specific fix.
Signed-off-by: Adam Ford <aford173@gmail.com>
The USE_TINY_PRINTF symbol only changes things within SPL and TPL
builds, so make it depend on that support. Next, make it default as
within these cases we should rarely have need of more advanced print
formats outside of the debug context.
To do this, in a few cases we need to correct our Kconfig dependencies
as we had cases of non-SPL targets select'ing this symbol. Finally, in
the case of a few boards we really do need the full printf
functionality.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts LEGO MINDSTORMS EV3 to the driver model. MMC, SERIAL, SPI
and SPI_FLASH are converted.
The device tree contains only the minimal nodes required by U-Boot
since the size of U-Boot is limited to 256K on this device.
Signed-off-by: David Lechner <david@lechnology.com>
Since pinctrl_stm32 driver update, each gpio bank is now binded
by pinctrl driver. The compatible string "st,stm32-gpio" becomes
useless, remove it.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch solves the following warnings:
arch/arm/mach-stm32mp/bsec.c: In function 'stm32mp_bsec_read':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (offset >= STM32_BSEC_OTP_OFFSET) {
^~
arch/arm/mach-stm32mp/bsec.c: In function 'stm32mp_bsec_write':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (offset >= STM32_BSEC_OTP_OFFSET) {
^~
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch solves the following warnings:
arch/arm/mach-stm32mp/cpu.c:378:16: warning: comparison between signed
and unsigned integer expressions [-Wsign-compare]
if (instance > ARRAY_SIZE(serial_addr))
^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add support of Trusted boot chain with OP-TEE
- reserved 32MB at the end of the DDR for OP-TEE
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Synchronize device tree with v5.2-rc4 label and
update the associated u-boot dtsi.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Pierre-Jean Texier <pjtexier@koncepto.io>
U-Boot should disable nodes in device tree if needed according
ETZPC status in ft_system_setup().
ETZPC itself use an array on addresses to do the match between the status
bits and the node.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add IPCC mailbox support on stm32mp157 eval and disco boards.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
- Minor tracing and PCI improvements
- Various other minor fixes
- Conversion of patman, dtoc and binman to support Python 3
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Merge tag 'dm-pull-9jul19-take2' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
- Sandbox improvements including .dts refactor
- Minor tracing and PCI improvements
- Various other minor fixes
- Conversion of patman, dtoc and binman to support Python 3
- SPL SATA enhancements to allow booting from RAW SATA device
needed for Clearfog (Baruch)
- Enable SATA booting on Clearfog (Baruch)
- Misc changes to Turris Omnia (Marek)
- Enable CMD_BOOTZ and increase SYS_BOOTM_LEN on crs305-1g-4s
(Luka)
- Enable FIT support for db-xc3-24g4xg (Chris)
- Enable DM_SPI on Keymile Kirkwood board with necessary changes
for this (Pascal)
- Set 38x and 39x AVS on lower frequency (Baruch)
- import DT updates from Linux
- add UniPhier SPI controller driver
- make U-Boot image for 64bit SoCs position independent
- tidy up various init code for next generation SoCs
- misc cleanups
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Merge tag 'uniphier-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2019.10
- import DT updates from Linux
- add UniPhier SPI controller driver
- make U-Boot image for 64bit SoCs position independent
- tidy up various init code for next generation SoCs
- misc cleanups
The board_early_init_f() inits clock before initing pinmux. However,
the clock configuration code might need to adjust PMIC settings of a
PMIC on I2C bus (e.g. board/ti/am335x/board.c does that). If the I2C
bus pin muxing is not configured before attempting to communicate
with the PMIC, the communication will silently fail and the prcm_init()
may configure fast enough CPU clock that the default voltage provided
by the PMIC would be insufficient and the platform would become
unstable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Tom Rini <trini@konsulko.com>
The name CONFIG_LEGACY_IMAGE_FORMAT reads slightly better along with
allowing us to avoid a rather nasty Kbuild/Kconfig issue down the line
with CONFIG_IS_ENABLED(IMAGE_FORMAT_LEGACY). In a few places outside of
cmd/ switch to using CONFIG_IS_ENABLED() to test what is set.
Signed-off-by: Tom Rini <trini@konsulko.com>
Overload the weak function board_boot_order() so that besides choosing
the main boot device, we can fallback on USB boot by returning in the
BootROM, eg. if the NOR flash is empty while it was the primary boot
medium.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The _main call is not supposed to return at all: don't link the
branch.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Implement the weak board_return_to_bootrom() function so that when
enabling the spl_bootrom.c driver, one can make use of usbboot on
spear platforms. All necessary information to return to the BootROM
are stored in the BootROM's stack. The SPL stack pointer is reset so
we save the BootROM's stack pointer into the SPL .data section.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
There is no reason to do the few spear-related initialization, in a
different procedure than 'reset'. Spare one branching and get a linear
code flow by removing this indirection.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The link register is stored in R14. ARM assembly code allows to use
the 'lr' name to reference it instead of 'r14' which is not very
meaningful. Do the substitution to ease the reading.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Quoting ARM "RealView Compilation Tools Assembler Guide v4.0":
PUSH and POP are synonyms for STMDB and LDM (or LDMIA), with
the base register sp (r13), and the adjusted address written
back to the base register.
PUSH and POP are the preferred mnemonic in these cases.
Let's follow this recommandation to ease the reading and substitute
LDMIA/STMDB operations with PUSH/POP mnemonics.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Before cleaning a bit further the spear/start.S file, apply a few
cosmetic changes: capital letters, comment indentation and small
rewriting.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This comment describes the board state at the moment where we enter
the SPL. The description is entirely wrong; re-write it to fit the
reality.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
SPL BSS lies in SRAM and is actually initialized to 0 by the SPL in
arch/arm/lib/crt0.S:_main(), which is called by cpu_init_crit.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
It is clearly stated that board_init_f should *not* call
board_init_r. Indeed, board_init_f should return. The code will
continue through arch/arm/lib/crt0.S which will do more setup before
calling board_init_r.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add a dummy PCI endpoint for sandbox.
Supporting only a single function, it allows setting
and reading header configuration.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reduce Auto Voltage Scaling VDD limit when core frequency is lower than
1600MHz. This reduces core voltage level from 1.25V to 1.15V, which
saves power.
The code is taken from Marvell's U-Boot 2013.01 revision 18.06.
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
KM Kirkwood boards now implement the driver model for its SPI flash
interface. Therefore, the old board specific claim and release functions
can be deleted. The preprocessor definition CONFIG_SYS_KW_SPI_MPP is yet
unused as well. All its appearances and dependencies are removed in the
kirkwood_spi driver, header files and finally the configuration whitelist.
Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
In order to migrate the SPI flash interface to the driver model, the SPI
configuration needs to be added in the KM Kirkwood device tree file.
Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
As preparation for the upcoming transferring of configurations from header
files to Kconfig, a common Kconfig file for all KM boards was created. For
the moment, it only sources the other three, more specific, Kconfig files.
Therefore, the architecture Kconfig files now include the common Kconfig
file. Also, the configuration selection for KM boards was moved from the
architecture Kconfig files to the board specific Kconfig files.
Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Enable SATA peripherals in SPL to allow boot from SATA.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add the required Kconfig and macro definitions to allow boot from SATA
on Armada 38x systems.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
SPL does not initialize mbus_dram_info. Don't change the ahci mbus
settings of the ROM. This allows the ahci to work in SPL.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This test is built on top of the existing swap_case driver. It adds EA
capability structure support to swap_case and uses that to map BARs.
BAR1 works as it used to, swapping upper/lower case. BARs 2,4 map to a
couple of magic values.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a test to check the management of the U-boot relocation properties
for device tree SPL generation (fdtgrep result) and platdata:
- 'dm-pre-proper' and 'dm-tpl' not included in SPL
- 'dm-pre-reloc' and 'dm-spl' included in SPL
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This struct is not defined in this header file. Add a forward declaration
so that it can be included in any context.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since the SPI nor conversion, 'sf probe' does not work on sandbox. Fix
this by using the expected compatible string in the flash node.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: cd35365762 (mtd: sf_probe: remove spi-flash compatible)
When cross-compiling, sometimes sdl-config must come from a different path
from the default. Add a way to override it, by adding SDL_CONFIG to the
environment before building U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
We normally want to load U-Boot from SPL, but if a board wants to do
something else, it is currently not possible since the standard loader
has the top priority. Lower it to allow other SPL_LOAD_IMAGE_METHOD()
declarations to override it.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present 'sf probe' does not work since it cannot find SPI bus 0. Add
an alias to correct this, now that we no-longer have the --spi_sf option.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present sandbox and sandbox64 have duplicated nodes. This is hard to
maintain since changes in one need to be manually added to the other.
Create a common file to solve this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Various nodes have been added and adjusted with sandbox. Move these
changes over to sandbox64.dts to keep these in sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
The base of DRAM will be changed for the next generation SoC.
The addresses needed for booting the kernel should be shifted
according to the DRAM base.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The base of DRAM will be changed for the next generation SoC.
Set the base address to the 'dram_base' environment variable, which
will be useful for scripting.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The base of DRAM will be changed for the next generation SoC.
To support it along with existing SoCs in the single defconfig,
set 'loadaddr' at boot-time by adding the offset to the DRAM base.
CONFIG_SYS_LOAD_ADDR is still hard-coded for compilation, but the
value from environment variable 'loadaddr' should be used.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The base address of DRAM was 0x80000000 for all the ARM SoCs of this
family in the past. It will be changed to 0x20000000 for a planned new
SoC. To support multiple SoCs by the single uniphier_v8_defconfig, the
base must be run-time determined.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, mem_map is hard-coded, and it worked well until the last
SoC. For a planned new SoC, the addresses of peripherals and DRAM
will be changed. Set it up run-time.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, dram_init() code relies on the fact the DRAM size
configuration exists in the SG_MEMCONF register.
This will no longer be true for a planned new SoC, which will
replace SG_MEMCONF with a different register.
Refactor the hook in a more generic way.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Until the last SoC, the register addresses have been hard-coded because
they are always constant. For a planned new SoC, the register bases
will be completely changed. I insist on supporting multiple SoCs/boards
by a single defconfig (uniphier_v8_defconfig) since duplicating similar
defconfig files is a maintenance burden. The base addresses must be
fixed-up at run-time somehow.
Previously, the board init code identified the SoC by reading out the
SG_REVISION register. This is much easier than parsing DT.
You cannot do it any more because the base address of SG will be
changed. The SG_REVISION register exists to read out the SoC ID, but
you never know its address before identifying the SoC. Oh well.
So, the possible solution is to parse the DT, and find out the node
with "*-soc-glue" compatible string. Then, sg_base is set to the value
of the "reg" property. The sc_base is set up likewise.
It is worth noting a pit-fall. Having sc_base and sg_base in the global
scope will make the life easier, but the global variables are poorly
supported before the relocation. In fact, the .bss section overwraps
with DT. Allocating them in the .bss section would break DT. So, I gave
dummy initializers to assign them in the .data section.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The SC_* macros represent the address of SysCtrl registers.
For a planned new SoC, its base address will be changed.
Turn the SC_* macros into the offset from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The SG_* macros represent the address of SoC-glue registers.
For a planned new SoC, its base address will be changed.
Turn the SG_* macros into the offset from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The planned new SoC does not have SBC (System Bus Controller) block.
Make boot_is_swapped() an optional hook.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_MICRO_SUPPORT_CARD is enabled, U-Boot initialize SBC
(System Bus Controller), which may not be really necessary.
Check the "socionext,uniphier-system-bus" node in DT run-time.
If and only if it is found and its "status" property is okay,
initialize the SBC block.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_MICRO_SUPPORT_CARD is enabled, U-Boot tries to get access
to the devices on the support card, which may not actually exist.
Check the DT and search for the on-board devices run-time. If the
nodes are not found in DT, then disable the code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This file calls readl(), so needs to include <linux/io.h>.
Currently, it relies on someone else including it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now that 64-bit SoCs of this SoC family no longer support SPL,
this Makefile can be slightly simpler.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The .boot_device_fixup() is only called by SPL.
Now that 64-bit SoCs of this SoC family no longer support SPL,
debug-uart-ld20.c is never compiled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[ Linux commit aa38571246c6ac279ebebd141157297bcb959d76 ]
The memory regions specified by /memreserve/ are passed to
early_init_dt_reserve_memory_arch() with nomap=false, so it is
not suitable for reserving memory for Trusted Firmware-A etc.
Use the more robust /reserved-memory node with the no-map property
to prevent the kernel from mapping it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
By default, CONFIG_SYS_INIT_SP_BSS_OFFSET was made invisible by not
giving a prompt to it.
The only way to define it is to hard-code an extra entry in SoC/board
Kconfig, like arch/arm/mach-tegra/tegra{186,210}/Kconfig.
Add a prompt to it in order to allow defconfig files to specify the
value of CONFIG_SYS_INIT_SP_BSS_OFFSET.
With this, CONFIG_SYS_INIT_SP_BSS_OFFSET would become always visible.
So, we need a new bool option to turn it off by default.
I move the 'default 524288' to the common place. This value is not too
big, but is big enough to avoid the overwrap of DT in most platforms.
If 512KB is not a suitable choice for your platform, you can change it
from your defconfig or menuconfig etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
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Merge tag 'u-boot-atmel-2019.10-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features and fixes for 2019.10 cycle
This includes the Atmel QSPI driver and support for the at91 boards.
This is the port of the driver from Linux, mostly done by Tudor Ambarus.
Fix the following:
- use "jedec,spi-nor" binding, we use jedec compatible flashes
- set bus width to 4, we use quad capable flashes
- differentiate bewteen data and clk and cs pins
- drop partions as we don't use them in u-boot.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
[tudor.ambarus@microchip.com: use "jedec,spi-nor", edit commit message]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
- add support for unique generated MAC adresses from SoC serial,
limited to Amlogic GXL/GXM boards for now
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Merge tag 'u-boot-amlogic-20190704' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- fix khadas-vim README
- add support for unique generated MAC adresses from SoC serial,
limited to Amlogic GXL/GXM boards for now
The watchdog of mediatek chips is enabled by bootrom before u-boot is
running. Previously we choose to enable the wdt driver only to disable the
watchdog hardware.
Now wdt service is enabled by default. The function arch_misc_init which is
only used to disable wdt is no longer needed.
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
With commit 06985289d4 ("watchdog: Implement generic watchdog_reset()
version") the init sequence has changed in arch_misc_init(), resulting
in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena).
When this happens, the first (or sometimes later ones as well) TFTP
command hangs and does not complete correctly. This leads to the
assumption that the d-cache is not in a clean state once the ethernet
driver is called (d-cache is used here for the buffers). The old work-
around with the cache flush somehow does not work any more now with
the new code change.
Unfortunately adding CONFIG_SYS_MALLOC_CLEAR_ON_INIT also did not fix
this issue. With v2019.07-rc3 it shows again. The time of accessing
the data seems to be very important here. It needs to be "very late"
in the boot process.
Testing has shown, that copying a 64KiB area in DDR at a very late
bootup time, directly before calling into the prompt, fixes this issue.
Flushing of the complete d-cache does not seem to necessary, as this
copy alone seems to fix this problem.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This uclass is intended for devices that do not need any features from the
uclass, including binding children.
This will typically be used by devices that are used to bind child devices
but do not use dm_scan_fdt_dev() to do it. That is for example the case of
several USB wrappers that have 2 child devices (1 for device and 1 for
host) but bind only one at a any given time.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit b238e4b00c ("rockchip: Cleanup of make_fit_atf.py.") set
firmware = "atf_1";
loadables = "uboot","atf_1","atf_2";
Actually it should be:
firmware = "atf_1";
loadables = "uboot","atf_2","atf_3";
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for generating an unique MAC address using the SoC internal
serial number from the Secure Monitor interface.
The algorithm generates an unicast locally administered 6bytes minus 2bits
address using an crc16 of the serial for the top 16bits with the lower 2 bits
masked to setup the unicast locally administered property and a crc24 for
the lower 24bits.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Secure Monitor interface permits retrieving the SoC Serial Number,
add a function to retrieve it.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
After the transition to DM, only the mx6dl/solo wandboard
is supported.
Add FIT image support so that all the wandboard variants
can be supported, like it was prior to the DM conversion.
Successfully booted Linux on mx6q/solo/qp wandboards.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Place dtbs under SoC level rather than board level.
imx6q-novena.dtb and imx6dl-wandboard-revb1.dtb were
placed under the board config option, so move them
to SoC level.
This also aligns with the kernel dts Makefile format.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
rockchip pinctrl driver has update to use dts, so we need
to add the pinctrl config in SPL for sdmmc.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Migrate all the "u-boot,dm-pre-reloc" tag from rk3288-tinker.dts
into rk3288-tinker-u-boot.dtsi.
When both board level and soc level '-u-boot.dtsi' files exist,
we need to include the soc level 'rk3288-u-boot.dtsi' manually.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
TPL is at SRAM while other stage is at SDRAM, so it needs
separate STACK.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
More boards other than vyasa needs TPL, so enable the TPL configs
at chip level instead of board level.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Move the sg_set_pinsel macro to arch/arm/mach-uniphier/arm32/debug_ll.S
since it is not used anywhere else.
Move the C functions sg_set_{pinsel,iectrl} to debug-uart.c since they
are not used anywhere else.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
debug_uart_init() is called from spl_board_init(), which is only
compiled for SPL. For U-boot proper, _debug_uart_init() is unreachable,
so dropped by the dead code elimination.
Now that 64-bit SoCs of this SoC family no longer support SPL,
debug-uart-ld20.c is never compiled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This file calls readl(), so needs to include <linux/io.h>.
Currently, it relies on someone else including it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The MPU region dedicated for SDRAM for STM32F4 SoCs family
was set to 16MB, but STM32F429 Evaluation board have 32MB of SDRAM.
When kernel starts, only first 16MB of SDRAM are configured with XN
(eXecute Never) bit disabled, whereas kernel is using 32MB.
To avoid such situation in the future, extend this MPU region to 512MB
as for STM32F7/H7.
It fixes the following user land exception on STM32F429 Evaluation
board :
[ 1.713002] VFS: Mounted root (ext4 filesystem) readonly on device 179:2.
[ 1.722605] devtmpfs: mounted
[ 1.733057] Freeing unused kernel memory: 72K
[ 1.737622] This architecture does not have kernel memory protection.
[ 1.744070] Run /sbin/init as init process
[ 1.906850]
[ 1.906850] Unhandled exception: IPSR = 00000004 LR = fffffffd
[ 1.914282] CPU: 0 PID: 1 Comm: init Not tainted 5.1.0-00002-gcf9ca5719954 #6
[ 1.921433] Hardware name: STM32 (Device Tree Support)
[ 1.926601] PC is at 0x1a00b64
[ 1.929642] LR is at (null)
[ 1.932669] pc : [<01a00b64>] lr : [<00000000>] psr: 01000000
[ 1.938993] sp : 01a5cfb0 ip : 00000000 fp : 00000000
[ 1.944269] r10: 01a43b00 r9 : 00000000 r8 : 00000000
[ 1.949564] r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000
[ 1.956168] r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 00000000
[ 1.962701] xPSR: 01000000
[ 1.965506] CPU: 0 PID: 1 Comm: init Not tainted 5.1.0-00002-gcf9ca5719954 #6
[ 1.972658] Hardware name: STM32 (Device Tree Support)
[ 1.978132] [<0000c009>] (unwind_backtrace) from [<0000b24f>] (show_stack+0xb/0xc)
[ 1.986024] [<0000b24f>] (show_stack) from [<0000b947>] (__invalid_entry+0x4b/0x4c)
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
As in stm32f7-u-boot.dtsi these nodes already have "u-bootdm-pre-reloc"
property, no need to add them again in stm32f746-disco-u-boot.dtsi.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Import iMX53 M53Menlo device tree from Linux next-20190607 3f310e51ceb1 .
Enable DT control in full U-Boot . Add U-Boot extras into separate DTSi,
the GPIO controllers need to be inited early, otherwise m53_set_clock()
won't be able to detect the correct CPU clock frequency by reading the
GPIO.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Synchronize iMX53 device tree from Linux next-20190607 3f310e51ceb1 ,
this is needed to get NFC, UART, USBOTG DT nodes.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
According to hab.c code we have to notify the ROM code if the MMU is
enabled or not. This is achieved by setting the "pu_irom_mmu_enabled"
to 0x1.
The current address in hab.c code is wrong for i.MX6SL, according to ROM
map file the correct address is 0x00901c60.
As we are writing in the wrong address the ROM code is not flushing the
caches when needed, and the following HAB event is observed in certain
scenarios:
--------- HAB Event 1 -----------------
event data:
0xdb 0x00 0x14 0x41 0x33 0x18 0xc0 0x00
0xca 0x00 0x0c 0x00 0x01 0xc5 0x00 0x00
0x00 0x00 0x07 0xe4
STS = HAB_FAILURE (0x33)
RSN = HAB_INV_SIGNATURE (0x18)
CTX = HAB_CTX_COMMAND (0xC0)
ENG = HAB_ENG_ANY (0x00)
Update MX6SL_PU_IROM_MMU_EN_VAR to address this issue.
Reported-by: Frank Zhang <frank.zhang@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Enable TPL_BOARD_INIT, this would help us to show
TPL boot prints.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Now, we have spl_board_init which has TPL banner prints.
So mark the 'U-Boot TPL board init' print into debug.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add spl_board_init for TPL, that have TPL banner will help
to print tpl boot prints.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable SPL_BOARD_INIT globally to rk3399, this would
help to print the SPL banner during bootup.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
u-boot,dm-pre-reloc for uart0, uart2 indeed u-boot specific
properties. Move them into rk3399-u-boot.dtsi so the boards
which enabled these node will available during SPL.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Now, we have spl_board_init with preloader_console_init that
indeed show SPL banner.
So mark the 'U-Boot SPL board init' print into debug.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Support common spl_board_init by moving code from puma
board file into, common rk3399-board-spl.c.
Part of the code has sysreset-gpio, regulators_enable_boot_on
but right now only puma board is using this with relevant
config options rest remains common for all targets.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Right now rockchip platform need to copy bl31.elf into u-boot
source directory to make use of building u-boot.itb.
So, add environment variable BL31 like Allwinner SoC so-that the
bl31.elf would available via BL31.
If the builds are not exporting BL31 env, the make_fit_atf.py
explicitly create dummy bl31.elf in u-boot root directory to
satisfy travis builds and it will show the warning on console as
WARNING: BL31 file bl31.elf NOT found, resulting binary is non-functional
WARNING: Please read Building section in doc/README.rockchip
Note, that the dummy bl31 files were created during not exporting
BL31 case would be removed via clean target in Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
rk3328-rock64.dts has been taken from Linux kernel commit
cff6d1d6f88b ("arm64: dts: rockchip: enable HS200 for eMMC on rock64")
with minor modifications (drop nodes not known by rk3328.dtsi).
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable SPL support and some related option in Kconfig.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from 430b01462b with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
rk3328 SPL is locate at dram, so do not have strict size limit,
suppose to enable storage media controller driver, load ATF and
U-Boot, then boot into ATF.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from 4ebe3968b6 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Converted to use fsl_esdhc_imx for i.MX platforms.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
This breaks Intel Edison to work. It gets laggish and unable to boot kernel.
Reverts commit 665cb18ea6 for now
till better solution will be proposed.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
T2080 integrated 4 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 3.0, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Compile the routines of mpc85xx/pci.c when both FSL_PCI_INIT
and DM_PCI are not enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Use the Kconfig option to select the PCIe reset errata.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Use the Kconfig option to select the PCIe ASPM errata.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
- LS1046AFRWY support
- USB errata fix and secure boot defconfig support for LS1028A
- Enabled SDHC and SATA for LX2160
- LS1046A serdes fixes
- other minor fixes
Remove the override for usbotg_hs on g-tx-fifo-size as the correct
binding, used in the kernel device tree, is now supported in dwc2
device driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
LS1028A includes an integrated PCI bus with 11 PCI functions residing on
bus 0. ECAM plus the device register space takes up 256MB of address
space.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Layerscape began to use two eSDHC controllers, for example,
LS1012A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on
lane D and lane C respectively for 0x3363 protocol.
So fix serdes1 settings for ls1046a.
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Fixes a link error on layerscape platform, linking fails with CONFIG_PCI
set and CONFIG_PCI_LAYERSCAPE unset.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Change bootcmd update logic when CONFIG_ENV_ADDR is not defined
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Update qspi clock configuration in TFABOOT in case
of all boot sources except qspi boot source.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This patch is to fixed the reg read to "0" for armv7
architecture.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Flushing L3 cache may need variable time depending upon cache line
allocation.
Coming up with a proper timeout value would be best handled by
simulations under multiple scenarios in your actual system.
>From the purely HN-F point of view, the flush would take ~15 cycles for
a clean line, and ~22 cycles for a dirty line. For the dirty line case,
there are many variables outside the HN-F that will increase the
duration per line. For example, a *DBIDResp from the SN-F/SBSX,
memory controller latency, SN-F/SBSX RetryAck responses, CCN ring
congestion, CCN ring hops, etc, etc. The worst-case timeout would
have to factor in all of these variables plus the HN-F cycles for
every line in the L3, and assuming all lines are dirty
In case if L3 is not flushed properly, system behaviour will be
erratic, so remove timeout and add loop to check status of L3 cache.
System will stuck in while loop if there is some issue in L3 cache
flushing.
Signed-off-by: Udit Kumar <udit.kumar@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This patch is to enable esdhc controllers for lx2160aqds
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Layerscape began to use two eSDHC controllers, for example,
LS1028A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Rx Compliance tests may fail intermittently at high jitter
frequencies using default register values.
So program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL
registers has been moved to DSCR as compared to other Layerscape SoCs
where it was in SCFG.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This provides an SPL_SIZE_LIMIT that makes the build check that the SPL
binary loaded from flash fits into the SRAM (64 KiB) and leaves enough
room for global data, heap and stack (512 bytes assumed stack usage).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
In order to use CMD_SF / CMD_SPI / ENV_IS_IN_SPI_FLASH we need to have
the SPI (or SPI_FLASH/DM_SPI_FLASH, for CMD_SF) enabled. Express this
in the Kconfigs.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Per discussion on the list, drop this board again.
Cc: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Updating the bcm283x device tree sources adds the device trees for
- Raspberry Pi 3 Model A+
- Raspberry Pi 3 Model B+
- Raspberry Pi Compute Module IO board rev1
- Raspberry Pi Compute Module 3 IO board V3.0
- Raspberry Pi Zero
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
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Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-boot
- Add Ethernet support for STM32MP1
- Add saveenv support for STM32MP1
- Add STM32MP1 Avenger96 board support
- Add SPI driver suport for STM32MP1
- Add watchdog support for STM32MP1
- Update power supply check via USB TYPE-C for STM32MP1 discovery board
All i.mx6 boards seems to have moved to DM_USB, however gadget support
for mx6 is still pre-DM as CI_UDC isn't converted yet. To make this work
the usb otg controller used for gadgets needs to be usb number 0.
Add an alias for this directly in the main u-boot mx6qdl dtsi so it
doesn't need to be done for each board separately.
This fixes regressions wrt. usb gadget functionality in several boards
that have gadget functions enabled in their config, but no usb0 alias in
their device-tree.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Without this definition, fsl_esdhc will access reserved registers
on i.MX chips, so define ARCH_MXC to fix it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Enable DM block and DM MMC support on iMX6SX VINING|2000 .
Convert board code to match the DM support. This disables
USB mass storage support due to missing DM USB, however
that will be re-enabled in subsequent patch.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
Import iMX6SX VINING|2000 device tree from Linux 5.1.1 b724e9356404 .
Enable DT control in full U-Boot .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
The company Samtec was merged into Softing, migrate the board over to
the new name and update copyright headers.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
The DM iMX PCI driver has DM_FLAG_OS_PREPARE set and will call
imx_pcie_remove() from the .remove callback. Do not call it from
the architecture code again.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit adds initial support for the Toradex Apalis iMX8QM 4GB WB IT
V1.0B module. Unlike the V1.0A early access samples exclusively booting
from SD card, they are now strapped to boot from eFuses which are
factory fused to properly boot from their on-module eMMC. U-Boot
supports either booting from the on-module eMMC or may be used for
recovery purpose using the universal update utility (uuu) aka mfgtools
3.0.
Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Gigabit Ethernet
- GPIOs
- I2C
Unfortunately, there is no USB functionality for the i.MX 8QM as of yet.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
CPU frequency reporting failed with the following error message being
printed:
sc_pm_get_clock_rate: resource:507 clk:2: res:3
Could not read CPU frequency: -22
CPU: NXP i.MX8QM RevB A53 at 0 MHz
Fix this by differentiating between the A35 as found on the i.MX 8QXP
and the A53 as found on the i.MX 8QM SoCs.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
Add support for i2c0, i2c1, i2c2, i2c3 and i2c4.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
Add support for lpuart1, lpuart2, lpuart3 and lpuart4.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
Enable DM block, DM MMC and DM SATA support on iMX6Q Novena
convert board code to match the DM support.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Vagrant Cascadian <vagrant@debian.org>
Import iMX6Q Novena device tree from Linux 5.1-rc7 37624b58542f .
Enable DT control in full U-Boot .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Vagrant Cascadian <vagrant@debian.org>
Correct uart clock root ID. Incorrect ID may result the
clock is gated because rate value 0 is returned in
imx_get_uartclk()
The ID can be ignored if CONFIG_SKIP_LOWLEVEL_INIT is not enabled
because init_clk_uart() will enable all uart clocks in that case.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Skip secure related initialization in arch_cpu_init if low level
init is skipped. Because these should be done in early stage
firmware, such as ARM trusted firmware.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
in case CONFIG_MULTI_DTB_FIT is set and u-boot-dtb.imx
image is build, currently u-boot-dtb.bin is used for
generating the u-boot-dtb.imx binary, which is wrong, as
it contains only a dtb blob not the fit.blob
Use instead the u-boot-fit-dtb.bin for generating
u-boot-dtb.imx which contains the fit.blob.
Signed-off-by: Heiko Schocher <hs@denx.de>
The SPI nCS signal is active low, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Ludwig Zenz <lzenz@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
Import DHCOM iMX6 PDK2 device tree from Linux 5.1.1 b724e9356404 .
Enable DT control in full U-Boot .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Ludwig Zenz <lzenz@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
This fixes an issue with USB host mode.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Migrate USB to Driver Model (CONFIG_DM_USB=y).
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Add device tree to Makefile to avoid newly introduced error:
Device Tree Source is not correctly specified.
Please define 'CONFIG_DEFAULT_DEVICE_TREE'
or build with 'DEVICE_TREE=<device_tree>' argument
make[1]: *** [dts/Makefile:28: arch/arm/dts/imx6-apalis.dtb] Error 1
make: *** [Makefile:1009: dts/dt.dtb] Error 2
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2
header.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB
IT V1.0B module. Unlike the V1.0A early access samples exclusively
booting from SD card, they are now strapped to boot from eFuses which
are factory fused to properly boot from their on-module eMMC. U-Boot
supports either booting from the on-module eMMC or may be used for
recovery purpose using the universal update utility (uuu) aka mfgtools
3.0.
Functionality wise the following is known to be working:
- eMMC and MMC/SD card
- Ethernet
- GPIOs
- I2C
Unfortunately, there is no USB functionality for the i.MX 8QXP as of
yet.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Building with Travis CI complained and stopped with the following error:
+cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No such
file or directory
+compilation terminated.
This fixes commit caceb739ea ("imx: build flash.bin for i.MX8") which
took SPL being enabled on i.MX8 for granted.
Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Merge tag 'u-boot-atmel-fixes-2019.07-a' of git://git.denx.de/u-boot-atmel
First set of u-boot-atmel fixes for 2019.07 cycle
The bulk of these changes are an effort to unify Tegra186 builds with
builds of prior 64-bit Tegra generations. On top of that there are
various improvements that allow data (such as the MAC address and boot
arguments) to be passed through from early firmware to the kernel on
boot.
We currently have duplicate definitions for BOARD_SIZE_CHECK in Makefile
and arch/arm/mach-imx/Makefile.
Move the board size check from arch/arm/mach-imx/Makefile to Makefile.
Depending on the value of CONFIG_BOARD_SIZE_LIMIT an error like an error
like the following is thrown:
u-boot-dtb.imx exceeds file size limit:
limit: 503696 bytes
actual: 509720 bytes
excess: 6024 bytes
make: *** [Makefile:1051: u-boot-dtb.imx] Error 1
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This patch adds independent watchdog support for stm32mp157c
in SPL.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the necessary configuration to have NAND and NOR support on ev1 board
for BASIC boot (with SPL) or for TRUSTED boot (with TF-A).
STM32MP> nand info
Device 0: nand0, sector size 256 KiB
Page size 4096 b
OOB size 224 b
Erase size 262144 b
subpagesize 4096 b
options 0x00184200
bbt options 0x00060000
STM32MP> sf probe
SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, total 64 MiB
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Without newline, the error message appears for non prgrammed OTP boards
looks messsy. Hence add it to look more clean.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add support for Avenger96 board from Arrow Electronics based on STM32MP157
MPU. This board is one of the Consumer Edition (CE) boards of the 96Boards
family and has the following features:
SoC: STM32MP157AAC
PMIC: STPMIC1A
RAM: 1024 Mbyte @ 533MHz
Storage: eMMC v4.51: 8 Gbyte
microSD Socket: UHS-1 v3.01
Ethernet Port: 10/100/1000 Mbit/s, IEEE 802.3 Compliant
Wireless: WiFi 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac
Bluetooth®v4.2 (BR/EDR/BLE)
USB: 2x Type A (USB 2.0) Host and 1x Micro B (USB 2.0) OTG
Display: HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4
LED: 4x User LED, 1x WiFi LED, 1x BT LED
More information about this board can be found in 96Boards website:
https://www.96boards.org/product/avenger96/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
By default the configuration of the PMC is to have an external crystal
connected that requires driving on both XIN and XOUT pins.
The bypass configuration means that only XIN will be used, the SoC will not
do any driving, and the XIN needs to be provided with a proper signal.
This is the MOSCXTBY bit in the PMC main clock generator register.
The SPL needs to properly initialize the PMC registers before switching
to external clock signal and raising the clock to the cruise speed.
Also created Kconfig for this specific configuration.
By default this is disabled.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Support for managing the non-volatile attribute of UEFI variables
is added though we do not have a backend for persistence yet.
Error messages for changes of UEFI variables are provided.
UEFI boottime service implementations are corrected.
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Merge tag 'efi-2019-07-rc4-2' of git://git.denx.de/u-boot-efi
Pull request for UEFI sub-system for v2019.07-rc4-2
Support for managing the non-volatile attribute of UEFI variables
is added though we do not have a backend for persistence yet.
Error messages for changes of UEFI variables are provided.
UEFI boottime service implementations are corrected.
Add an "ethernet" alias that points to the default network interface,
which is the built-in EQoS on Jetson TX2.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Recent versions of DTC have checks for PCI host bridge device tree nodes
that are named something other than "pci" or "pcie". Fix all occurrences
of such nodes for Tegra boards to avoid potential warnings from DTC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Note that U-Boot is always chainloaded from cboot starting with L4T
release 28. cboot always loads U-Boot to a fixed address, so making
the builds position independent isn't strictly necessary. However,
position independent builds can be convenient because if U-Boot is
ever loaded to an address different from its link address, it will
still be able to boot.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Read the boot arguments passed by cboot via the /chosen/bootargs
property and store it in the cbootargs environment variable.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This function will attempt to look up an Ethernet address in the DTB
that was passed in from cboot. It does so by first trying to locate the
default Ethernet device for the board (identified by the "ethernet"
alias) and if found, reads the "local-mac-address" property. If the
"ethernet" alias does not exist, or if it points to a device tree node
that doesn't exist, or if the device tree node that it points to does
not have a "local-mac-address" property or if the value is invalid, it
will fall back to the legacy mechanism of looking for the MAC address
stored in the "nvidia,ethernet-mac" or "nvidia,ether-mac" properties of
the "/chosen" node.
The MAC address is then written to the default Ethernet device for the
board (again identified by the "ethernet" alias) in U-Boot's control
DTB. This allows the device driver for that device to read the MAC
address from the standard location in device tree.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is easier to deal with and works just as well for this simple
function.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra186 build are currently dealt with in very special ways, which is
because Tegra186 is fundamentally different in many respects. It is no
longer necessary to do many of the low-level programming because early
boot firmware will already have taken care of it.
Unfortunately, separating Tegra186 builds from the rest in this way
makes it difficult to share code with prior generations of Tegra. With
all of the low-level programming code behind Kconfig guards, the build
for Tegra186 can again be unified.
As a side-effect, and partial reason for this change, other Tegra SoC
generations can now make use of the code that deals with taking over a
boot from earlier bootloaders. This used to be nvtboot, but has been
replaced by cboot nowadays. Rename the files and functions related to
this to avoid confusion. The implemented protocols are unchanged.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Resetting the USB device controller on boot is only necessary if the SoC
actually has a UDC controller and U-Boot enables support for it. All the
Tegra boards support UDC via the ChipIdea UDC driver, so make the UDC on
boot workaround depend on the ChipIdea UDC driver.
This prevents a crash on Tegra186 which does not have the ChipIdea UDC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some devices may restrict access to the PMC to TrustZone software only.
Non-TZ software can detect this and use SMC calls to the firmware that
runs in the TrustZone to perform accesses to PMC registers.
Note that this also fixes reset_cpu() and the enterrcm command on
Tegra186 where they were previously trying to access the PMC at a wrong
physical address.
Based on work by Kalyani Chidambaram <kalyanic@nvidia.com> and Tom
Warren <twarren@nvidia.com>.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The save_boot_params() function takes as its first four arguments the
first four registers. On 32-bit ARM these are r0, r1, r2 and r3, all of
which are 32 bits wide. However, on 64-bit ARM thene registers are x0,
x1, x2 and x3, all of which are 64 bits wide. In order to allow reusing
the save_boot_params() implementation on 64-bit ARM, change it to take
unsigned long parameters rather than the fixed size 32-bit integers.
This ensures that the correct values are passed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Powergate code is not relevant on all Tegra SoC generations, so guard it
with a Kconfig symbol that can be selected by the generations that need
it.
This is in preparation for unifying Tegra186 code with the code used on
older generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Pin controller code is not relevant on all Tegra SoC generations, so
guard it with a Kconfig symbol that can be selected by the generations
that need it.
This is in preparation for unifying Tegra186 code with the code used on
older generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Memory controller code is not relevant on all Tegra SoC generations, so
guard it with a Kconfig symbol that can be selected by the generations
that need it.
This is in preparation for unifying Tegra186 code with the code used on
older generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The GP pad control code is not relevant on all Tegra SoC generations, so
guard it with a Kconfig symbol that can be selected by the generations
that need it.
This is in preparation for unifying Tegra186 code with the code used on
older generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Clock code is not relevant on all Tegra SoC generations, so guard it
with a Kconfig symbol that can be selected by the generations that need
it.
This is in preparation for unifying Tegra186 code with the code used on
older generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There's no need to replicate the pmu.h header file for every Tegra SoC
generation. Use a single header that is shared across generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
pll_c is not a valid parent for the disp1 clock, so trying to set it
will fail. Given that display is not used in U-Boot, remove the init
table entry so that disp1 will keep its default parent (clk_m).
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
On Tegra210 the parents for the disp1 and disp2 clocks are slightly
different from earlier chips. Only pll_p, pll_d_out0, pll_d2_out0 and
clk_m are valid parents (technically pll_d_out is as well, but U-Boot
doesn't know anything about it). Fix up the type name and the mux
definition.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There are no more users of lowlevel_init.S. Remove the file.
Suggested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The commong initialization code manually initializes the GPIO
even when OF_CONTROL does it, so we can reduce the code size a
bit by not doing it manually when we have device tree support.
Using the omap3_logic board (dm3730), the sizes shrunk:
Before:
text data bss dec hex filename
561066 28596 116880 706542 ac7ee u-boot
55245 1605 1888 58738 e572 spl/u-boot-spl
After
text data bss dec hex filename
560898 28548 116872 706318 ac70e u-boot
55121 1557 1888 58566 e4c6 spl/u-boot-spl
Signed-off-by: Adam Ford <aford173@gmail.com>
With ipam390 support removed in we can remove the reference to the
linker script since that case will never be true.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
U-Boot README recommends initializing SDRAM in board_init_f(). DA850
was doing it as part of board_init_r() (through call to spl_board_init()
which calls arch_cpu_init() which calls da850_ddr_setup())
This worked fine till commit 15b8c75058 ("davinci:
da850evm/omapl138-lcdk: Move BSS to SDRAM because SRAM is full") moved
BSS to SDRAM.
Functions like mmc_initialize() called in board_init_r() assume BSS is
available. Since SDRAM was not initialized when arch/arm/lib/crt0.S tried
to initialize BSS to 0, BSS is not initialized correctly.
Fix this by simply calling arch_cpu_init() from board_init_f(). Also move
preloader_console_init() there to help debug issues with board_init_r().
With this spl_board_init() is no longer needed, we remove it.
Tested using MMC/SD boot on OMAP-L138 LCDK board.
Tested-by: Adam Ford <aford173@gmail.com> #da850evm
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Peter Howard <phoward@gme.net.au> #omapl138_lcdk
- Support Microchip MPFS Icicle board.
- Enable e1000 and nvme support for qemu.
- Enable PCI host ECAM generic driver for qemu.
- Increase the environment size to 128kB for qemu.
This patch adds Microchip MPFS Icicle board support.
For now, NS16550 serial driver is only enabled.
The Microchip MPFS Icicle defconfig by default builds
U-Boot for M-Mode with SMP support.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Extend the driver to build with DM_VIDEO enabled. DTS files
must additionally include 'u-boot,dm-pre-reloc' property in
soc and child nodes to enable driver binding to mxsfb device.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
In the UEFI Stall() boottime service we need access to usec_to_tick().
Export the function.
Remove redundant implementation in arch/arm/mach-rockchip/rk_timer.c.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This allows SPL to load the main U-Boot image from MMC once DM_MMC is
enabled.
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
- some fix for rk3399-puma;
- rockchip script make_fit_atf.py cleanup
- Enable TPL for rk3399 orangepi and nanopi4;
- add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
When using External PHY, reset the mux to use the external PHY in case U-Boot
was chainloaded from a misconfigured bootloader.
Fixes: 33e3378091 ("ARM: meson: rework soc arch file to prepare for new SoC")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The following DT nodes in the process on review for Linux 5.3,
until Linux 5.3 is tagged, add the missing DT nodes in u-boot specific
DTSI files that will be dropped when the v5.3-rc1 DT is synced again.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add initial support for Rock PI 4 board.
Specification
- Rockchip RK3399
- LPDDR4
- eMMC
- SD card slot
- RTL8211E 1Gbps
- HDMI In/Out, DP, MIPI DSI/CSI
- PCIe M.2
- USB 2.0, USB-3.0
- USB C Type
Commit details of rk3399-rock-pi-4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: add ROCK Pi 4 DTS support"
(sha1: 1b5715c602fda7b812af0e190eddcce2812e5417)
Signed-off-by: Akash Gajjar <akash@openedev.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add initial support for Rockpro64 board.
Specification
- Rockchip RK3399
- 2/4GB Dual-Channel LPDDR3
- SD card slot
- eMMC socket
- 128Mb SPI Flash
- Gigabit ethernet
- PCIe 4X slot
- WiFI/BT module socket
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-rockpro64.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: rockpro64 dts add usb regulator"
(sha1: 6db644c79c8d45d73b56bc389aebd85fc3679beb)
'Akash' has sent an initial patch before, so I keep him as board
maintainer and I'm co-maintainer based on our conversation.
Signed-off-by: Akash Gajjar <akash@openedev.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This patch cleans up make_fit_atf.py in the following way:
* Fix all issues reported by pylint
* Move copyright notice from file-to-generate to script
* Fix of-by-one bugs in loadables property
* Remove commented-out (dead) code.
Besides the bugfix no intended changes.
Tested on RK3399-Q7 with TF-A v2.1 as BL31.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The RK3399 SPL does not use a pinctrl driver to setup the UART pins.
Instead it works based on config macros, which set the base address
of the actual UART block.
Currently the RK3399 SPL support UART0 and UART2.
This patch adds UART3 in the same way as UART0.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This patch adds the missing GRF bit definitions for UART3 on the RK3399.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Heiko Schocher <hs@denx.de>
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
- Gen3 PCIe driver + enablement on Salvator-X platforms.
- Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon.
- SDHI HS400 fixes ported from latest BSP and datasheet.
Add a driver which supports transmitting digital sound to an audio codec.
This uses fixed parameters as a device-tree binding is not currently
defined.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a driver for the audio hub. This is modelled as a misc device which
supports writing audio data from I2S.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This function enables a peripheral clock and then immediately sets its
divider. Add a delay to allow the clock to settle first. This matches the
delay in other places which do a similar thing.
Without this, the I2S device on Nyan does not init properly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The first clock type appears to have and incorrect setting for out of the
mux outputs. It should be CLK_M, not OSC. Fix it and its only user.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
With commit 06985289d4 ("watchdog: Implement generic watchdog_reset()
version") the init sequence has changed in arch_misc_init(), resulting
in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena).
When this happens, the first (or sometimes later ones as well) TFTP
command hangs and does not complete correctly. This leads to the
assumption that the d-cache is not in a clean state once the ethernet
driver is called (d-cache is used here for the buffers). The old work-
around with the cache flush somehow does not work any more now with
the new code change.
To fix this issue, this patch now removes the old workaround and selects
CONFIG_SYS_MALLOC_CLEAR_ON_INIT for ARCH_MTMIPS. With this option the
complete malloc area is initialized with zeros (cache lines are touched).
Testing has shown that this also fixes the issue on the MT7688 boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Finding bitstream from cff-file is no longer valid after bitstream is built
into FIT image and loaded by generic firmware loader. Remove cff-file
as this is legacy implementation from A10 downstream.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
- Add STM32MP1 DDR driver update:
These update introduce the DDR interactive mode described in:
https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode
This mode is used by the CubeMX: DDR tuning tool.
https://wiki.st.com/stm32mpu/index.php/STM32CubeMX
The DDR interactive mode is NOT activated by default because
it increase the SPL size and slow down the boot time
(200ms wait added).
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Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-boot
- Add various STM32MP1 fixes for serial, env, clk, board, i2c ...
- Add STM32MP1 DDR driver update:
These update introduce the DDR interactive mode described in:
https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode
This mode is used by the CubeMX: DDR tuning tool.
https://wiki.st.com/stm32mpu/index.php/STM32CubeMX
The DDR interactive mode is NOT activated by default because
it increase the SPL size and slow down the boot time
(200ms wait added).
This patches move dspi bus-related operations into more
proper location, to avoid the driver to declares them as externs.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
This patch adds basic dts files for all the m68k boards.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
[trini: Add CONFIG_TARGET_M5329EVB dtbs and update M5329EVB defconfigs]
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds a basic group of devicetrees, one for each
cpu family, including actually just uart and dspi devices,
since these are the drivers supporting devicetree (support
added in this patch-set).
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
On SoCFPGA A10 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices using DMA, like e.g. the
DWMMC controller. This can in turn cause e.g. SPL to fail reading data
from SD/MMC.
The obvious solution here would be to fully reset the L2 cache controller
via the reset manager MPUMODRST L2 bit, however this causes bus hang even
if executed entirely from L1 I-cache to avoid generating any bus traffic
through the L2 cache controller.
This patch thus configures and enables the L2 cache controller very early
in the SPL boot process, clears the L2 cache and disables the L2 cache
controller again.
The reason for doing it in SPL is because we need to avoid accessing any
of the potentially stale data in the L2 cache, and we are certain any of
the stale data will be below the OCRAM address range. To further reduce
bus traffic during the L2 cache invalidation, we enable L1 I-cache and
run the invalidation code entirely out of the L1 I-cache.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Pull the PL310 clearing code into common code, so it can be reused
by Arria10.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Manage power supply configuration for board using stpmic1
with LPDDR2 or with LPDDR3:
+ VDD_DDR1 = 1.8V with BUCK3 (bypass if possible)
+ VDD_DDR2 = 1.2V with BUCK2
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Update DDR configuration with the latest update:
- PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte
lane 2/3 in 16bit
- fix LPDDR2/3 timing_calc to step RL/WL in relaxed
timings mode
- remove LPDDR3 RL3 (optional) support vs MR0[7]
because MR0[7] can't be read instead always apply
worse RL/WL for LPDDR3 when freq < 166MHz)
- change MR3 to 48ohm drive for LPDDR2/3
- change default ZPROG[7:4] = 0x1 for LPDDR2/3 ,
'0' is not allowed even when ODT not used
- use DQSTRN for LPDDR2/3 (it was not set in PIR)
- LPDDR3: set dqsge/dwsgx gate extension to 2,2
like LPDDR2
-DDRCTRL.dfitmg0:
+ for LPDDR3 tphy_wrlat = WL (as LPDDR2)
+ improvement for relaxed mode vs RL/Wl at corner case.
For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3
and correction to MR2 accordingly
- DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40,
for LTDC.
- DDR_PCFGWQOS0_0: change vpr level from
11 to 12 in order to include the CPU on
the variable priority queue.
- DDR_SCHED: fix to consider 13 levels (13 levels - 1 = 0xC)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add the needed configurations for bootstage and
activate bootstage command.
BOOTSTAGE_REPORT is not activated by default.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
In initf_bootstage() we call bootstage_mark_name() which ends up calling
timer_get_us() before timer_init(); that cause crash for stm32mp1.
This patch solve the issue without changing the initialization sequence.
See also commit 97d20f69f5 ("Enable CONFIG_TIMER_EARLY with bootstage")
for other solution when DM is activated for TIMER.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Use SGI0 interruption and TAMP_BACKUP_MAGIC_NUMBER
to synchronize the core1 boot sequence requested by
core0 in psci_cpu_on():
- a initial interruption is needed in ROM code after
RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off)
- the ROM code set to 0 the 2 registers
+ TAMP_BACKUP_BRANCH_ADDRESS
+ TAMP_BACKUP_MAGIC_NUMBER
when magic is not egual to
BOOT_API_A7_CORE0_MAGIC_NUMBER
This patch solve issue for cpu1 restart in kernel.
echo 0 > /sys/devices/system/cpu/cpu1/online
echo 1 > /sys/devices/system/cpu/cpu1/online
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch moves the the config SYS_MALLOC_LEN to
Kconfig as it is already done for zynq arch in
commit 01aa5b8f05 ("Kconfig: Move config
SYS_MALLOC_LEN to Kconfig for zynq")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on
CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE
is enabled
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead
of PCIE_LAYERSCAPE.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The LS2080A has 8GB region for each PCIe controller, while the
other platforms have 32GB.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Change to use PCIe address macro to determine if precompile the PCIe
MMU table entry.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
when loading the splash image from a FIT
- updates for loading internal and external splash data from FIT
- DM_GPIO/DM_VIDEO migration for mx53 cx9020 board
- fix boot issue on mx6sabresd board after DM_VIDEO migration
- increase the max preallocated framebuffer BPP to 32 in ipuv3
driver to prepare for configurations with higher color depth
- allow to use vidconsole_put_string() in board code for text
output on LCD displays
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Merge tag 'video-for-2019.07-rc3' of git://git.denx.de/u-boot-video
- update for using splashfile instead of location->name
when loading the splash image from a FIT
- updates for loading internal and external splash data from FIT
- DM_GPIO/DM_VIDEO migration for mx53 cx9020 board
- fix boot issue on mx6sabresd board after DM_VIDEO migration
- increase the max preallocated framebuffer BPP to 32 in ipuv3
driver to prepare for configurations with higher color depth
- allow to use vidconsole_put_string() in board code for text
output on LCD displays
The gdsys gazerbeam board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.
On board peripherals include:
- 2x 10/100 Mbit/s Ethernet (optional)
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Add a U-Boot specific dts file, which encapsulates the needed
modifications to the Gazerbeam Linux device tree.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
To support OF_EMBED, the MPC83xx architecture has to define the "_end"
symbol to correctly access the appended DT.
Fortunately, MPC8xx already defines the symbol, and the linker script is
quite similar to that of MPC83xx, so copy this approach for MPC83xx.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Lots of stuff in processor.h was taken verbatim from the Linux kernel.
It was never synced, so most of it was removed or changed in the kernel
since it was imported.
Remove all the stuff that is unused in the current U-Boot sources;
should anybody feel the need to re-sync with the kernel, they can do it
later on.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
For a lot of inline assembly calls in the mpc8xxx and mpc83xx
directories, we already have convenient pre-defined helper functions,
but they're not used, resulting in hard-to-read code.
Use these helper functions where ever possible and useful.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
ppcDWstore/ppcDWload are hardly used by any board, but since they're
implemented in start.S, they're always present in every U-Boot image,
even if they're not needed.
Re-implement these fuctions in C with inline assembly, so that the
compiler can decide when to actually include them.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The fsl-esdhc driver can be used for the SDHC functionality on MPC83xx,
but it needs some additional definitions.
Add a clock.h file, so we can use the driver for MPC83xx.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The MPC85xx GPIO driver was converted to handle a broader range of SoCs.
Prepare the MPC83xx code for usage of this driver.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Replace the hard-coded CONFIG_SYS_NS16550_CLK value for the FDT fixup
with the previously introduced get_serial_clock function
This will make it possible to activate DM for serial devices on MPC83xx
later on.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
DM serial drivers on PowerPC determine their clock frequency via the
get_serial_clock function. This function is not Implemented yet for
MPC83xx.
This patch Implements the function so that DM serial drivers work on
MPC83xx.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Migrate the BR/OR settings to Kconfig. These must be known at compile
time, so cannot be configured via DT.
Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The LBLAW_* values determine the window configuration of the memory
controller. Hence, they must be known at compile time, and cannot be
implemented in the DT mechanism.
Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The BATs (block address translation registers) determine the initial
memory window mappings. Hence, they must be known at compile time and
cannot be implemented in the DT mechanism.
Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The MPC83xx DM timer driver disables arch.pciexp*_clk, and uses
clk_get_rate instead. But the legacy MPC83xx PCIe driver still uses
arch.pciexp*_clk for the clock.
Hence, read the PCIe clock from the registers in the legacy MPC83xx PCIe
driver.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The HRCW (hardware reset configuration word) is a constant that must be
hard-coded into the boot loader image. So, it must be available at
compile time, and cannot be migrated to the DT mechanism, but has to be
kept in Kconfig.
Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
MPC83xx uses CONFIG_83XX_CLKIN instead of CONFIG_SYS_CLK_FREQ to set the
system clock. To migrate the architecture, we can replace
CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ.
To do this
* replace all occurrences of CONFIG_83XX_CLKIN with CONFIG_SYS_CLK_FREQ
* set CONFIG_SYS_CLK_FREQ to the old value of CONFIG_83XX_CLKIN in all
MPC83xx config files
Signed-off-by: Mario Six <mario.six@gdsys.cc>
CONFIG_SYS_CLK_FREQ is the standard way to set the system clock
frequency. On MPC83xx, CONFIG_83XX_CLKIN is used for this purpose.
Hence, the obvious way is to replace CONFIG_83XX_CLKIN with
CONFIG_SYS_CLK_FREQ.
A few MPC83xx boards use the CONFIG_83XX_CLKIN variable for computing
CONFIG_SYS_NS16550_CLK. This makes it harder to replace
CONFIG_83XX_CLKIN.
But the value of the multiplicator can be read from the SPMR register.
Hence, replace the static calculations with a call to a new get_bus_freq
function, as other architectures do.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The MPC83xx include files contain some settings of the PCI subsystem.
Migrate these to Kconfig until a proper DM PCI driver exists.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The MPC8349EMDS config file contains config options to enable SDRAM
support. To keep this ability after the Kconfig migration, create a new
MPC8349EMDS_SDRAM board that enables the SDRAM support and remove the
SDRAM support from the original board.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Some H6 boards have a watchdog which didn't make the SoC
reboot properly.
Reason is still unknown but several people have test it.
Chen-Yu Tsai :
Pine H64 = H6 V200-AWIN H6448BA 7782 => OK
OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO
Martin Ayotte :
Pine H64 = H8069BA 6892 => OK
OrangePi 3 = HA047BA 69W2 => KO
OrangePi One Plus = H7310BA 6842 => KO
OrangePi Lite2 = H6448BA 6662 => KO
Clément Péron:
Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO
After the series of result, Icenowy try to reach Allwinner about this
issue but they seems not interested to investigate it.
As we don't have the ARIS coproc to do power management and watchdogis
the only solution to reset the board.
So, Change from watchdog to R_watchdog to allow a reboot on all H6
boards.
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The LSDMR_* macros are used to configure the system bus on MPC83xx.
A few of the possible LSDMR_* macros were never defined in the
respective include files. This renders the SDRAM support on the
MPC8349EMDS unusable, because it uses these undefined macros.
To make the SDRAM option work, introduce these macros into the proper
config file.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
vme8349.h contains two separate boards: The vme8349 itself, and the
caddy2 board. The caddy2 board is chosen by setting certain config
variables. Create a proper config file for the caddy2 board to make
Kconfig migration easier.
Furthermore, simplify the vme8349 and caddy2 configs by keeping only the
options necessary for each board.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
MPC8313ERDB has the option of either enabling NOR or NAND boot in its
config file (by commenting out certain #ifdefs). To keep this ability
after migrating options to Kconfig, we introduce two MPC8313ERDB
configs: one for NOR, and one for NAND.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The kmeter1, and kmcoge5ne boards also build from the same config
file with #ifdef logic.
Create a separate include config for each board with the #ifdef logic
resolved as needed.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The kmsupx5, tuge1, kmopti2, and kmtepr2 boards all build from the same
include config file with lots of #ifdef logic.
To ease Kconfig migration, create new config include files for these
boards, and resolve the #ifdef logic as needed.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
The kmtegr1, kmvect1, and suvd3 boards all use the same config include
file with lots of #ifdefs in it.
The Kconfig migation will become easier if we get rid of these #ifdefs
first.
Hence, create distinct config include files for these boards, and unwind
the #ifdef logic in these config files to only include the options
necessary for each board.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Meet the following boot hang.
"
U-Boot SPL 2019.04-00661-gdc80a012e4 (Apr 25 2019 - 10:31:57 +0800)
Trying to boot from MMC1
U-Boot 2019.04-00661-gdc80a012e4 (Apr 25 2019 - 10:31:57 +0800)
CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C)Reset cause: POR
Model: Freescale i.MX6 Quad SABRE Smart Device Board
Board: MX6-SabreSD
I2C: ready
DRAM: 1 GiB
Video device 'ipu@2400000' cannot allocate frame buffer memory -ensure the device is set up before relocation
Error binding driver 'ipuv3_video': -28
Video device 'ipu@2800000' cannot allocate frame buffer memory -ensure the device is set up before relocation
Error binding driver 'ipuv3_video': -28
Some drivers failed to bind
Error binding driver 'generic_simple_bus': -28
Some drivers failed to bind
initcall sequence 4ffe4500 failed at call 1780dfb7 (err=-28)
"
1. fdtdec_get_alias_seq will use "video" as base, however in alias node,
we use ipux, so add new alias for U-Boot dts.
2. DM_VIDEO is enabled, however reserve_video is called before
relocation, so to make DM_VIDEO work before relocation, need to
set SYS_MALLOC_F_LEN
3. defconfig is updated with savedefconfig
Note: I do not have a video panel to test, but with this patch, U-Boot
boots up again, below log.
"
U-Boot SPL 2019.04-00662-g0b62453bff (Apr 25 2019 - 10:36:31 +0800)
Trying to boot from MMC1
U-Boot 2019.04-00662-g0b62453bff (Apr 25 2019 - 10:36:31 +0800)
CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Model: Freescale i.MX6 Quad SABRE Smart Device Board
Board: MX6-SabreSD
I2C: ready
DRAM: 1 GiB
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 3
Loading Environment from MMC... *** Warning - bad CRC, using default environment
PCI: pcie phy link never came up
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
The ipu node in imx53 is needed for DM_VIDEO. We also need to set
u-boot,dm-pre-reloc to initialize before relocation.
Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Without this U-Boot specific property, booting on Armada XP theadorable
fails in SPL. All nodes in the "internal-regs" (simple-bus) DT node are
not scanned, so the UART node is missing (and others).
I'm not adding this property in an *u-boot.dtsi file, since there is
none matching the generic rules for all files including this dtsi
file. So to not miss any of the boards using this dtsi file, I'm
adding it to this file directly, which makes the Linux merge a less
easy unforunately.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
coreboot makes it possible to add own entries into coreboot's
table at a per mainboard basis. As there might be some custom
ones it makes sense to provide a way to process them.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The watchdog should use a clock at 50 Mhz, so
instead of using the clock osc (200 Mhz), we
define a reference clock at 50Mhz and use it
for both watchdog.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The watchdog should use a clock at 50 Mhz, so
instead of using the clock osc (200 Mhz), we
define a reference clock at 50Mhz and use it
for both watchdog.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Stefan Roese <sr@denx.de>
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
CONFIG_SYS_[DI]CACHE_OFF had been partially converted to Kconfig
parameters; only for the ARC architecture. This patch turns these two
parameters into Kconfig items everywhere else they are found.
All of the include/configs/* and defconfig changes in this patch are
for arm machines only. The Kconfig changes for arc, nds32, riscv,
and xtensa have been included since these symbols are found in code
under arch/{arc,nds32,riscv,xtensa}, however, no currently-defined
include/configs/* or defconfigs for these architectures exist which
include these symbols.
These results have been confirmed with tools/moveconfig.py.
Acked-by: Alexey Brodkin <abrodkin@snopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Re-migrate for a few more boards]
Signed-off-by: Tom Rini <trini@konsulko.com>
According to De Morgan's Law[1]:
!(A && B) = !A || !B
!(A || B) = !A && !B
There are 5 places in the code where we find:
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
and 4 places in the code where we find:
#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
In words, the construct:
!defined(CONFIG_SYS_[DI]CACHE_OFF)
means:
"is the [DI]CACHE on?"
and the construct:
defined(CONFIG_SYS_[DI]CACHE_OFF)
means:
"is the [DI]CACHE off?"
Therefore
!(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
means:
"the opposite of 'are they both off?'"
in other words:
"are either or both on?"
and:
(!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
means:
"are either or both on?"
As a result, I've converted the 4 instances of '(!A || !B)' to '!(A && B)' for
consistency.
[1] https://en.wikipedia.org/wiki/De_Morgan%27s_laws
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
Keep the FPGA bridge entries in SPL DT to let do_bridge_reset() toggle
the bridges on/off as needed according to the handoff file.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi
into separate dtsi header file to make it easier to patch in custom handoff
dtsi files, without having to manually add the U-Boot bits. Shuffle the include
clauses in the A10 DT files to make it obvious what gets included where without
having to follow confusing long chain of includes, i.e. board DT file includes
everything it needs.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK and MCVEVP baseboard. The board can boot
from eMMC. Ethernet and USB is supported.
The Aries Embedded boards have been removed with commit 03b54997d5
("board/aries: Remove"). I will now take care of them.
The device-tree files are from mainline Linux commit e93c9c99a629
("Linux v5.1)".
Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
CC: Marek Vasut <marex@denx.de>
CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The stratix 10 reset manager ad-hoc code in arch/arm contains an unused
function 'reset_deassert_peripherals_handoff' that has been added from
the beginning. As this is probably a result of copying the gen5 reset
manager and this function has never been used, remove it.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
commit c5de2b7eae ("arm: socfpga: implement proper peripheral reset")
has removed the call to 'reset_deassert_peripherals_handoff()' from
socfpga gen5 SPL since the reset driver now handles resets. However,
commit c1d4b464c8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA")
has re-added this ad-hoc reset code, so that all peripherals were now
again enabled instead of letting the drivers enable them by request.
While at it, remove this function for gen5 as it should not be used.
Fixes: commit c1d4b464c8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Mark Jonas <mark.jonas@de.bosch.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
For chainboot configurations or test environments, this patch allows
booting barebox images by using command bootz.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
- Add USB Complex Glue driver for Amlogic G12A
- Add USB Gadget support for Amlogic G12A
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Merge tag 'u-boot-amlogic-20190509' of git://git.denx.de/u-boot-amlogic
- Add USB PHY drivers for Amlogic G12A
- Add USB Complex Glue driver for Amlogic G12A
- Add USB Gadget support for Amlogic G12A
Add initial support for Nanopc T4 board.
Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- 16GB eMMC
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A
Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: Add NanoPC-T4 IR receiver"
(sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3)
Tested-by: Daniel Gröber <dxld@darkboxed.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Attaching GPIO functionality to SDMMC0_DET pin (which
does in Linux base dts) make dwmmc driver "fail to detect
the card".
Card did not respond to voltage select!
It may be because the existing driver can't support gpio
card detection. So, change the pinctrl functionality from
RK_FUNC_GPIO to RK_FUNC_1 like other rk3399 dts does via
sdmmc_cd pin.
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.
It depends on the following kernel patch which adds the header to the
flat Image. Gzip compressed Image (Image.gz) support is not enabled with
this patch.
https://patchwork.kernel.org/patch/10925543/
Tested on HiFive Unleashed and QEMU.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Karsten Merker <merker@debian.org>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.
When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adds support for Amlogic G12A USB Device mode.
The DWC2 Controller behind the Glue can be connected to an OTG
capable PHY. The Glue setups the PHY mode.
This patch implements Device mode support by adding a board_usb_init/cleanup
setting up the DWC2 controller and switch the OTG capable port to Device
before starting the DWC2 controller in Device mode.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This allows SPL to load the main U-Boot image from MMC once DM_MMC is
enabled.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and
like some of the other similar boards requires bin_hdr.
bin_hdr (DDR3 init stage) is currently retrieved from the stock
bootloader and compiled into the kwb image.
Adds support for U-Boot, enable UART, SPI, Winbond SPI flash chip
support and writing env to SPI flash.
Signed-off-by: Luka Kovacic <me@lukakovacic.xyz>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Commit ff7bd212cb ("net: phy: micrel: fix divisor value for KSZ9031
phy skew") fixed the skew value divisor for the KSZ9031, but left the
code using the same divisor for the KSZ9021, which is incorrect.
The preceding commit c16e69f702 ("net: phy: micrel: add documentation
for Micrel KSZ90x1 binding") added the DTS documentation for the
KSZ90x1, changing it from the equivalent file in the Linux kernel to
correctly state that for this part the skew value is set in 120ps steps,
whereas the Linux documentation and driver continue to this day to use
the incorrect value of 200 that came from the original KSZ9021 datasheet
before it was corrected in revision 1.2 (Feb 2014).
This commit sorts out the resulting confusion in a consistent way by
making the following changes:
- Update the documentation to be clear about what the skew values mean,
in the same was as for the KSZ9031.
- Update the Micrel PHY driver to select the appropriate divisor for
both parts.
- Adjust all the device trees that state skew values for KSZ9021 PHYs to
use values based on 120ps steps instead of 200ps steps. This will result
in the same values being programmed into the skew registers as the
equivalent device trees in the Linux kernel do, where it incorrectly
uses 200ps steps (since that's where all these device trees were copied
from).
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Olimex A64-Teres-I board is a mainboard (the only one so far)
for Olimex Teres-I DIY laptop kit.
Key features:
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 2GB DDR3 RAM
- MicroSD Slot
- 16GB eMMC Flash
- eDP LCD display
- HDMI
- USB Host
- Battery management
- 5V DC power supply
- Certified Open Source Hardware (OSHW)
Works:
- i2C
- MMC/SD
- PWM backlight
Known broken:
- Internal keyboard (seems to be because the keyboard firmware loads a
bootloader first, and then disconnects bootloader and connect real
keyboard). External ones connected to the USB port work fine.
This patch enables support for the A64-Teres-I board to u-boot,
including enabling screen backlight (lacking from Linux device-tree).
Linux commit details about the sun50i-a64-teres-i.dts sync:
"arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins"
(sha1: d91ebb95b96c8840932dc3a10c9f243712555467)
Cosmetic warnings regarding whitespace and placement of SPDX notice for
dts file was ignored.
config and .dtsi file are adapted from pinebook files.
Tested-by: Jonas Smedegaard <dr@jones.dk>
Signed-off-by: Jonas Smedegaard <dr@jones.dk>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: move board entry in MAINTAINERS file at proper position]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.
Linux commit details about the rk3399-nanopi4.dtsi sync:
"arm64: dts: rockchip: Add nanopi4 bluetooth"
(sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Few SPL and U-Boot proper configs are common to all rk3399 target
defconfigs, move them and select it from platform kconfig.
Moved configs:
- SPL_ATF
- SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
- SPL_LOAD_FIT
- SPL_CLK if SPL
- SPL_PINCTRL if SPL
- SPL_RAM if SPL
- SPL_REGMAP if SPL
- SPL_SYSCON if SPL
- CLK
- FIT
- PINCTRL
- RAM
- REGMAP
- SYSCON
- DM_PMIC
- DM_REGULATOR_FIXED
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
To make successful build with dts(i) files syncing from Linux 5.1-rc2
the rk3399.dtsi would require pwm2_pin_pull_down.
So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this
node is strictly not part of any commit alone, I have mentioned
Linux 5.1-rc2 tag for future reference of where would this sync
coming from.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Now we have
- board specific -u-boot.dtsi files for board specific u-boot
dts changes.
- soc specific rk3399-u-boot.dtsi for soc specific u-boot
dts changes.
So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi
and drop the properties which are globally available in rk3399-u-boot.dtsi
Right now rk3399-u-boot.dtsi has sdmmc, spi1 u-boot,dm-pre-reloc
property and more properties and nodes can be move further based
on the requirements.
This would fix, the -u-boot.dtsi inclusion for evb, firefly, puma
boards that was accidentally merged on below commit.
"rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi"
(sha1: e05b4a4fa8)
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add u-boot,dm-pre-reloc property for spi1, so-that the
subsequent rk3399 boards which boot from SPI.
This help to separate the u-boot specific properties away
from base dts files so-that the Linux sync become easy and
meaningful.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Devicetree files in RK3399 platform is synced from Linux, like other
platforms does. Apart from these u-boot in rk3399 would also require
some u-boot specific node like dmc.
dmc node has big chunk of DDR timing parameters which are specific
to specific board, and maintained with rk3399-sdram*.dtsi.
So, create board specific -u-boot.dtsi files and move these sdram dtsi
files accordingly. This would help of maintain u-boot specific changes
separately without touching Linux dts(i) files which indeed easy for
syncing from Linux between releases.
These board specific -u-boot.dtsi can be extendible to add more u-boot
specific nodes or properties in future.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
- Sometimes u-boot specific dtsi files are included
automatically which would build for entire rockchip SoC,
even-though the respective dtsi should used it for specific
family of rockchip SoC.
- Sometimes u-boot specific dts nodes or properties can use
config macros from respective rockchip family include/configs
files, example CONFIG_SPL_PAD_TO.
So, it's better to compile the dtbs based on the respective
rockchip family types rather than rockchip itself to avoid
compilation issues.
This patch organize the existing dtb's based on the rockchip
family types.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable sound for this board, which has the same codec as jerry.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip platform suppose to use TPL(run in SRAM) as dram init and
SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be
limited by SRAM size.
This patch add rk3399-board-tpl.c and its common configs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We don't have both sram and sdram in TPL, so update from:
arch/arm/cpu/armv8/u-boot-spl.lds
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The iomux should have been set in board_debug_uart_init(),
do not set in board_init_f(), remove it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
TPL need dmc to init ddr sdram, and emmc, boot-order.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
evb-rk3368 is using UART2 and PX5 evb is using UART4
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Move original spl to tpl, and add spl to load next stage firmware,
adapt all the address and option for them.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
TPL stack may different from SPL and sys stack, add support for
separate one when the board defines it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY
and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This is fix to:
e2a12f590d rockchip: use 'arch-rockchip' as header file path
The V2 of origin patch set has fix this, but we merge V1 by
mistake, so lets correct it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
boot0.h and gpio.h will be used by system and include by
'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When TPL finishes it needs to jump to SPL with the stack set up correctly.
Add a function to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With the move to Kconfig this option should be set in Kconfig, not in the
config header file. Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With the use of a phandle we can outdent the device tree nodes a little.
Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This report is normally generated by U-Boot proper. Correct the condition
here so that it respects the Kconfig options for bootstage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The MTRRs are normally set up in U-Boot proper, so avoid setting them up
in SPL as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update the Makefie rules to ensure that the correct files are built when
TPL is being used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When the MRC cache fails to save it is useful to have some debugging info
to indicate what when wrong. Add some more debug() calls.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds
and identifies the CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allow broadwell to build for SPL and include the reference code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present broadwell only supports booting straight into U-Boot proper.
Add a separate init file to boot from SPL into U-Boot proper, and select
it when SPL is in use.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When a previous phase of U-Boot has run we need to adjust the init of
subsequent states to avoid messing up the CPU state.
Add a new version of the start logic for SPL, when it boots from TPL
(start_from tpl.c) and a new version for U-Boot when it boots from SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Split the CPU init into two parts - the 'full' init which happens in the
first U-Boot phase, and the rest of the init that happens on subsequent
stages.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.
Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add debugging during SDRAM init so that problems are easier to
diagnose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add an arch-specific handoff header so that we can use the HANDOFF feature
on x86 devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some boards want to use TPL as the first phase of U-Boot. This allows
selection of A or B SPL phases, thus allowing the memory init to be
upgraded in the field.
Add a new Kconfig option for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present only chromebook_link64 supports SPL. It is useful to eb able to
support both TPL and SPL to implement verified boot on x86.
Enable the options for both along with some suitable default options
needed to boot through these phases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add labels for these nodes so that board DT files can reference them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We cannot init the CPU fully both than once during a boot. Add a new
function which can be called to figure out the CPU identity, but which
does not change anything. For x86_64, this is empty for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present many of the functions in this file return -1 as an error
number. which is -EPERM. Update the code to use real error numbers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We use binman to build the x86 image now. Update a comment which still
refers to ifdtool.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .
Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC.
Distinguishing feature of this SoC is that it has up to
10 MiB of on-SoC static RAM (SRAM).
The DTs are imported from Linux 5.0.11, commit d5a2675b207d .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Send CONFIG_STATUS and RECONFIG_STATUS mailbox commands to Secure
Device Manager (SDM) to get the status of FPGA and make sure the
FPGA is in user mode before enable the bridge.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Software must never reset FPGA2SOC bridge. This bridge must only be
reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software
can cause the SoC to lock-up if there are traffics being drived into
FPGA2SOC bridge.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Convert Stratix 10 SDRAM driver to device model.
Get rid of call to socfpga_per_reset() and use reset
framework.
SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.
Move sdram_s10.h from arch to driver/ddr/altera directory.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
As mx66l512 qspi flash supports quad input fast program and
quad input fast read, set spi-tx_bus-width and spi-rx_bus-width
to 4.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
As n25q128 qspi flash supports quad input fast program and
quad input fast read, set spi-tx_bus-width and spi-rx_bus-width
to 4.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
As n25q512a qspi flash supports quad input fast program and
quad input fast read, set spi-tx_bus-width and spi-rx_bus-width
to 4.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The Quad-SPI interface is able to manage up to 256Mbytes Flash
memory starting from 0x90000000 to 0x9FFFFFFF in the memory
mapped mode.
Add a dedicated MPU region into stm32_region_config.
See application note AN4760 available at www.st.com
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
for suspend/resume robustness
update value for ext_phy_ctrl_36 for suspend/resume robustness
with hardware leveling enabled.
Match recommended values from EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
In case of RTC+DDR resume, need to restore EMIF context
before initiating hardware leveling.
Signed-off-by: Brad Griffis <bgriffis@ti.com>
[j-keerthy@ti.com Fixed the am335x build issues]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Enable HW leveling in RTC+DDR path. The mandate is to enable
HW leveling bit and then wait for 1 ms before accessing any
register.
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Adjust DQS skew in case where invert_clkout=1 is used.
Match recommended values from EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
This fixes SPL linker script size checks for 3 lds files where the size
checks were implemented as "x < YYY_MAX_SIZE".
Fix the size checks to be "x <= YYY_MAX_SIZE" instead.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Select the PL310 UCLASS_CACHE driver for SoCFPGA.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Add the PL310 macros for latency control setup, read and write bits.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
maintenance operations being done to support non-coherent platforms
causes issues.
For example, here is how U-Boot prepares/handles a buffer to receive
data from a device (DMA Write). This may vary slightly depending on the
driver framework:
Start DMA to write to destination buffer
Wait for DMA to be done (dma_receive()/dma_memcpy())
Invalidate destination buffer (invalidate_dcache_range())
Read from destination buffer
The invalidate after the DMA is needed in order to read latest data from
memory that’s updated by DMA write. Also, in case random prefetch has
pulled in buffer data during the “wait for DMA” before the DMA has
written to it. This works well for non-coherent architectures.
In case of coherent architecture with L3 cache, DMA write would directly
update L3 cache contents (assuming cacheline is present in L3) without
updating the DDR memory. So invalidate after “wait for DMA” in above
sequence would discard latest data and read will cause stale data to be
fetched from DDR. Therefore invalidate after “wait for DMA” is not
always correct on coherent architecture.
Therefore, provide a Kconfig option to disable cache maintenance ops on
coherent architectures. This has added benefit of improving the
performance of DMA transfers as we no longer need to invalidate/flush
individual cache lines(especially for buffer thats several KBs in size).
In order to facilitate use of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
flush_dcache_all() and invalidate_dcache_all() are exclusively used
during enabling/disabling dcache and hence are not disabled.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Ocelot
- mt7620: rename arch to more generic name mtmips
- mips: pass initrd addresses via DT as physical addresses
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Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mips
- mscc: small fixes, enhance network support for Serval, Luton and Ocelot
- mt7620: rename arch to more generic name mtmips
- mips: pass initrd addresses via DT as physical addresses
To assure the pins on R-Car Gen3 SoCs are configured correctly, always
select pin control drivers on Gen3 SoCs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
>From way back in 2015:
commit dffb86e468
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed Aug 12 07:31:54 2015 +0900
of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL
As we discussed a couple of times, negative CONFIG options make our
life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
and here is another one.
Now, there are three boards enabling OF_CONTROL on SPL:
- socfpga_arria5_defconfig
- socfpga_cyclone5_defconfig
- socfpga_socrates_defconfig
This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
the logic.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The support for DaVinci DM* SoCs has been dropped a while ago. There's
still a lot of leftover code in mach-davinci though. Entirely remove
certain files and modify the common code to no longer reference
unsupported chips.
Note: all DaVinci platforms supported in u-boot now define SOC_DA8XX
but not all define SOC_DA850 (e.g. omapl138). We can safely remove
all ifdefs for the former, but let's leave the ones for the latter.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The support for DaVinci DM* boards has been dropped a while ago. The
code for all those PHYs is no longer used and they have their own
proper PHY drivers in drivers/net/phy anyway. Remove all dead code.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
There are a few functions defined in the header file, but they are
not referenced by any Davinci code. In order to make a general
function in the future with static function declarations, this
patch will remove the references all together.
Signed-off-by: Adam Ford <aford173@gmail.com>
Update device tree for luton to add support for luton pcb90.
This pcb has 24 ports from which 12 ports are connected to
SerDes6G.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Currently mach-mt7620 contains only support for mt7628. To avoid confusion,
rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms.
MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628
because they do not share the same lowlevel codes.
Dependencies of four drivers are changed to SOC_MT7628 as these drivers
are only used by MT7628.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Microsemi SoC defines CONFIG_SYS_SDRAM_BASE to be 0x80000000, which
represents the start of kseg0 and represents a virtual address. Meaning
that the initrd_start and initrd_end point somewhere kseg0.
When these parameters are passed to linux kernel through DT
they are pointing somewhere in kseg0 which is a virtual address but linux
kernel expects the addresses to be physical addresses(in kuseg) because
it is converting the physical address to a virtual one.
Therefore update the uboot to pass the physical address of initrd_start
and initrd_end by converting them using the function virt_to_phys before
setting up the DT.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Remove "select MSCC_BITBANG_SPI_GPIO" since Kbuild option was deleted
back in commit ace9c103df:
commit ace9c103df
Author: Lars Povlsen <lars.povlsen@microchip.com>
Date: Tue Jan 8 10:38:35 2019 +0100
mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
Add ethernet nodes for Serval SoCs family. There are 2 pcb in this
family: pcb105 and pcb106.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
The card detect pin was incorrectly using IRQ_TYPE_LEVEL_LOW
instead of GPIO_ACTIVE_LOW when reading the state of the CD pin.
Without this patch, MMC1 won't be detected.
This is the same patch submitted to linux-omap, but I was hoping
to get it applied to U-Boot without having to wait for the
linux adoption and then backporting.
Fixes: 5448ff33f2 ("ARM: DTS: Resync Logic PD SOM-LV 37xx
devkit with Linux 4.18-RC4")
Signed-off-by: Adam Ford <aford173@gmail.com>
Add device-tree files from linux 5.1-rc7 needed to complete support
for PocketBeagle.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Transition to the IOPAD macros as used in Linux in which the pin mux
mode is specified using a dedicated parameter while also dropping the
related MUX_MODEx macros that are no longer needed. This transition
will allow us to keep both Linux and U-Boot DTS in sync more easily.
While at it also align the file name of the include file itself and
update any references accordingly.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
- at91sam9g20-taurus.dts: use labels
- cleanup taurus port to compile clean with
current mainline again. SPL has no serial
output anymore, so it fits into SRAM.
Signed-off-by: Heiko Schocher <hs@denx.de>
Switch from using the high priority DMSC transmit message queue used
by the secure R5 MCU island boot context to the low priority message
queue. While the change in priority is irrelevant for the current boot
architecture it however gives us access to a deeper message queue that
will allow us to buffer more messages. This is an important aspect when
sending several messages without requesting and waiting for a response
in a row which is a communication scheme used during core shutdown for
example. See AM654 TISCI User Guide for additional details.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
There is a Factory RESET button on the back side of the Turris Omnia
router. When user presses this button before powering the device up and
keeps it pressed, the microcontroller prevents the main CPU from booting
and counts how long the RESET button is being pressed (and indicates
this by lighting up front LEDs).
The idea behind this is that the user can boot the device into several
Factory RESET modes.
This patch adds support for U-Boot to read into which Factory RESET mode
the user booted the device. The value is an integer stored into the
omnia_reset environment variable. It is 0 if the button was not pressed
at all during power up, otherwise it is the number identifying the
Factory RESET mode.
This patch also changes bootcmd to a special hardcoded value if Factory
RESET button was pressed during device powerup. This special bootcmd
value sets the colors of all the LEDs on the front panel to green and
then tries to load the rescue image from the SPI flash memory and boot
it.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This driver is required for Turris Omnia to read ethernet addresses.
Move the dependency from turris_omnia_defconfig to Kconfig.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The I2C dependencies are defined in include/configs/turris_omnia.h,
because Turris Omnia won't boot correctly without I2C support.
Move these dependencies to Kconfig, so that they are selected if Turris
Omnia is selected as target.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
------------------------
- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
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Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx
Porting to DM and i.MX8
------------------------
- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
To avoid a warning, we need to include the header defining
back_to_bootrom for us.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
After applying the series for debug_uart_init(), Travis-CI reports:
arch/arm/mach-rockchip/rk3399/rk3399.c:90:2: error: implicit declaration of function 'spl_gpio_set_pull' [-Werror=implicit-function-declaration]
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
^~~~~~~~~~~~~~~~~
This is caused by a missing header-file include. Fix it.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file for all rockchip SoCs later.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Prefer to use structure to access register if we could.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file later for all rockchip SoCs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file for all rockchip SoCs later.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Prefer to use structure to access register if we can.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file later for all rockchip SoCs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up header-list to not break FASTBOOT:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Use board_debug_uart_init() for UART iomux init instead of
do it in board_init_f, and move the function to soc file so
that we can find all the soc/board setting in soc file and
use a common board file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed whitespace error:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
All Rockchip SoCs use DEBUG_UART_BOARD_INIT to init per board
UART IOMUX, enable it by default.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The ARCH_SOC name default as 'rockchip' and we put all the
header file in 'arch/arm/include/asm/arch-rockchip/', but
the 'rockchip' is not the SOC name, let's correct it after
we update all the source file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsiich <philipp.tomsich@theobroma-systems.com>
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
rockchip platform header file is in 'arch-rockchip'
instead of arch-$(SOC) for all SoCs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
TIMER7_BASE is no used by source code now, remove it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This failed and caused a boot failure on c201, and afaik
the pins should be setup by the new pinctrl driver.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
u-boot,dm-pre-reloc is required for SDMMC booted rk3399 boards and
which is U-Boot specific devicetrees binding.
Move it on global rk3399-u-boot.dtsi file and rest of the U-Boot
bindings will move it future based on the requirement.
This would help to sync the devicetrees from Linux whenever required
instead of adding specific nodes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sync rk3399-opp.dtsi from Linux.
Linux commit details about the rk3399-opp.dtsi sync:
"arm64: dts: rockchip: use SPDX-License-Identifier"
(sha1: 4ee99cebd486238ac433da823b95cc5f8d8a6905)
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Booting this board failed as the initial console isn't found since
commit c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")
The uart0 devicetree entry was missing "clock-frequency = <100000000>:"
since that commit
Fixes: c402e81702 ("dts: arm: socfpga: merge gen5 devicetrees from linux")
Reported-by: rafael mello <rafaelmello_3@hotmail.com>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and
is confirmed to lead to a rare system hang when enabling bridges. This
patch removes the socfpga_sdram_apply_static_cfg() altogether, because
it's use seems unjustified and problematic.
The socfpga_sdram_apply_static_cfg() triggers write to SDRAM staticcfg
register to set the applycfg bit, which according to old vendor U-Boot
sources can only be written when there is no traffic between the SDRAM
controller and the rest of the system. Empirical measurements confirm
this, setting the applycfg bit when there is traffic between the SDRAM
controller and CPU leads to the SDRAM controller accesses being blocked
shortly after.
Altera originally solved this by moving the entire code which sets the
staticcfg register to OCRAM [1]. The commit message claims that the
applycfg bit needs to be set after write to fpgaportrst register. This
is however inverted by Altera shortly after in [2], where the order
becomes the exact opposite of what commit message [1] claims to be the
required order. The explanation points to a possible problem in AMP
use-case, where the FPGA might be sending transactions through the F2S
bridge.
However, the AMP is only the tip of the iceberg here. Any of the other
L2, L3 or L4 masters can trigger transactions to the SDRAM. It becomes
rather non-trivial to guarantee there are no transactions to the SDRAM
controller.
The SoCFPGA SDRAM driver always writes the applycfg bit in SPL. Thus,
writing the applycfg again in bridge enable code seems redundant and
can presumably be dropped.
[1] 75905816ec
[2] 8ba6986b04
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Add optional "mask" argument to the SoCFPGA bridge command, to select
which bridges should be enabled/disabled. This allows the user to avoid
enabling bridges which are not connected into the FPGA fabric. Default
behavior is to enable/disable all bridges.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Instead of just putting the bridges into reset, fully remove the bridges
from the L3 main bridge space when disabling them by clearing bits in
NIC-301 remap register. Moreover, only touch the 3 LSbits in brgmodrst
register as the rest of the bits are undefined.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Disable bridges between L3 Main switch and FPGA unless booting
from FPGA and keep them disabled to prevent glitches and possible
hangs of the L3 Main switch.
The current version of the code could have enabled the bridges
between the L3 Main switch and FPGA for a short period of time
in board_init_f() in case the FPGA was programmed and then again
disable them at the end of board_init_f(). Replace this with a
code which only sets up the handoff registers and let the user
enable the bridges later on.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Factor out the code for programming preloader handoff register values,
the ISWGRP Handoff 0 and 1. These registers later control which bridges
are enabled by the "bridge" command on Gen5 devices.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Add the device trees for
* vexpress_ca5x2_defconfig
* vexpress_ca9x4_defconfig
* vexpress_ca15_tc2_defconfig
as available in Linux 5.1 rc5.
We are using the vexpress_ca15_tc2_defconfig and vexpress_ca9x4_defconfig
for Travis testing via QEMU.
The UEFI base Embedded Base Boot Requirements Specification (EBBR) requires
that an embedded board either provides a device tree or an ACPI table.
All block devices are meant to be moved to the driver model. On ARM this
requires a device tree.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The match controller register is not cleared during
initialization. However, some bits of this register may reset the TC if
tnMRx match it.
As we can't make any assumption about how U-Boot is launched by the first
stage bootloader (such as S1L) clearing this register ensure that the
timers work as expected.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
K3 HS devices require signed binaries for boot, use the SECDEV tools
to sign the boot artifacts during build.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
K3 devices have High Security (HS) variants along with the non-HS already
supported. Like the previous generation devices (OMAP/Keystone2) K3
supports boot chain-of-trust by authenticating and optionally decrypting
images as they are unpacked from FIT images. Add support for this here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
On HS devices the 512b region of reset isolated memory called
MCU_PSRAM0 is firewalled by default. Until SYSFW is loaded we
cannot use this memory. It is only used to store a single value
left at the end of SRAM by ROM that will be needed later. Save
that value to a global variable stored in the .data section.
This section is used as .bss will be cleared between saving
this value and using it.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
- Add DM based generic watchdog start and reset implementation
and remove all ad-hoc implementations (Stefan)
- Move mv_sdhci to DM (Pierre)
- Misc turris_omnia updates (Pierre)
- Change openrd targets to correctly build again (size changes
and fixes to the dts targets) and bring it back into Travis
builds (Stefan)
- Add Kirkwood db-88f6281-bp board (Chris)
With the new generic function, the scattered other functions are now
removed to be replaced by the generic one. The new version also enables
the configuration of the watchdog timeout via the DT "timeout-sec"
property (if enabled via CONFIG_OF_CONTROL).
The watchdog servicing is enabled via CONFIG_WATCHDOG.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
With the generic watchdog driver now implemented, this patch removes
some legacy stuff from the MPC8xx watchdog driver and its Kconfig
integration. CONFIG_MPC8xx_WATCHDOG is completely removed and
hw_watchdog_reset() is made static, as the watchdog will now get
serviced via the DM infrastructure if enabled via CONFIG_WATCHDOG.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
This patch tries to implement a generic watchdog_reset() function that
can be used by all boards that want to service the watchdog device in
U-Boot. This watchdog servicing is enabled via CONFIG_WATCHDOG.
Without this approach, new boards or platforms needed to implement a
board specific version of this functionality, mostly copy'ing the same
code over and over again into their board or platforms code base.
With this new generic function, the scattered other functions are now
removed to be replaced by the generic one. The new version also enables
the configuration of the watchdog timeout via the DT "timeout-sec"
property (if enabled via CONFIG_OF_CONTROL).
This patch also adds a new flag to the GD flags, to flag that the
watchdog is ready to use and adds the pointer to the watchdog device
to the GD. This enables us to remove the global "watchdog_dev"
variable, which was prone to cause problems because of its potentially
very early use in watchdog_reset(), even before the BSS is cleared.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Maxim Sloyko <maxims@google.com>
Cc: Erik van Luijk <evanluijk@interact.nl>
Cc: Ryder Lee <ryder.lee@mediatek.com>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: "Álvaro Fernández Rojas" <noltari@gmail.com>
Cc: Philippe Reynes <philippe.reynes@softathome.com>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
This is Marvell's Kirkwood development board. It has the following
features
- 512M DDR2
- 2 PCI connectors
- 1 x1 PCI-e interface
- 1 Gigabit Ethernet Port
- 2 SATA Ports
- USB 2.0 Interface
- SDIO
- 128M NAND Flash
- 16M SPI Flash
It can be strapped to boot from SPI or NAND so there are two defconfigs
(one per boot media).
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The following Kirkwood dtb build targets are currently missing:
kirkwood-openrd-base.dtb
kirkwood-openrd-client.dtb
kirkwood-openrd-ultimate.dtb
This patch adds them to the Makefile to fix the build error.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The new DM implementation currently does not support the Sheeva
88SV331xV5 specific quirk present in the legacy implementation. The
legacy code is thus kept for this SoC and others not yet migrated to
DM_MMC.
Signed-off-by: Pierre Bourdon <delroth@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit switches to DM USB for warp7 and warp7_bl33 defconfigs.
Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This commit switches to DM SERIAL for warp7 and warp7_bl33 defconfigs.
Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
