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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Browse source 
- PCIe driver change to support DM model
- T2080QDS migrated to use PCIe DM model
This commit is contained in:
Tom Rini 2019-06-20 09:14:35 -04:00
commit f643fb9f4c
36 changed files with 842 additions and 43 deletions
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29
arch/powerpc/cpu/mpc85xx/Kconfig
View file

@ -533,6 +533,7 @@ config ARCH_BSC9132
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_I2C_A004447
select SYS_FSL_ERRATUM_IFC_A002769
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -551,6 +552,7 @@ config ARCH_C29X
select SYS_FSL_DDR_VER_46
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -566,6 +568,7 @@ config ARCH_MPC8536
select FSL_LAW
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@ -594,6 +597,7 @@ config ARCH_MPC8544
bool
select FSL_LAW
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -609,6 +613,7 @@ config ARCH_MPC8548
select SYS_FSL_ERRATUM_NMG_LBC103
select SYS_FSL_ERRATUM_NMG_ETSEC129
select SYS_FSL_ERRATUM_I2C_A004447
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR1
select SYS_FSL_HAS_SEC
@ -633,6 +638,7 @@ config ARCH_MPC8560
config ARCH_MPC8568
bool
select FSL_LAW
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -643,6 +649,7 @@ config ARCH_MPC8569
select FSL_LAW
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -657,6 +664,7 @@ config ARCH_MPC8572
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_DDR_115
select SYS_FSL_ERRATUM_DDR111_DDR134
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
@ -681,6 +689,7 @@ config ARCH_P1010
select SYS_FSL_ERRATUM_P1010_A003549
select SYS_FSL_ERRATUM_SEC_A003571
select SYS_FSL_ERRATUM_IFC_A003399
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -702,6 +711,7 @@ config ARCH_P1011
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -716,6 +726,8 @@ config ARCH_P1020
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -735,6 +747,8 @@ config ARCH_P1021
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -756,6 +770,7 @@ config ARCH_P1022
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_SATA_A001
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -769,6 +784,7 @@ config ARCH_P1023
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_I2C_A004447
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -782,6 +798,8 @@ config ARCH_P1024
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -802,6 +820,8 @@ config ARCH_P1025
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_DISABLE_ASPM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -819,6 +839,7 @@ config ARCH_P2020
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_ERRATUM_ESDHC_A001
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@ -1074,6 +1095,7 @@ config ARCH_T2080
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
@ -1096,6 +1118,7 @@ config ARCH_T2081
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
@ -1429,6 +1452,12 @@ config SYS_P4080_ERRATUM_SERDES_A001
config SYS_P4080_ERRATUM_SERDES_A005
bool
config FSL_PCIE_DISABLE_ASPM
bool
config FSL_PCIE_RESET
bool
config SYS_FSL_QORIQ_CHASSIS1
bool

2
arch/powerpc/cpu/mpc85xx/pci.c
View file

@ -12,7 +12,7 @@
#include <asm/cpm_85xx.h>
#include <pci.h>
#if !defined(CONFIG_FSL_PCI_INIT)
#if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI)
#ifndef CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE

48
arch/powerpc/dts/t2080.dtsi
View file

@ -104,4 +104,52 @@
sata-fpdma = <0x0>;
};
};
pcie@ffe240000 {
compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe250000 {
compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe260000 {
compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe270000 {
compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
law_trgt_if = <3>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */
};
};

5
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -61,19 +61,16 @@
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#elif defined(CONFIG_ARCH_P1020)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#elif defined(CONFIG_ARCH_P1021)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
@ -95,14 +92,12 @@
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28

2
board/freescale/t208xqds/pci.c
View file

@ -11,6 +11,7 @@
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#if !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
#endif

3
configs/T2080QDS_NAND_defconfig
View file

@ -66,6 +66,9 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

3
configs/T2080QDS_SDCARD_defconfig
View file

@ -63,6 +63,9 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

3
configs/T2080QDS_SECURE_BOOT_defconfig
View file

@ -50,6 +50,9 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

3
configs/T2080QDS_SPIFLASH_defconfig
View file

@ -64,6 +64,9 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

3
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
View file

@ -43,6 +43,9 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

3
configs/T2080QDS_defconfig
View file

@ -50,6 +50,9 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

8
drivers/pci/Kconfig
View file

@ -60,6 +60,14 @@ config PCIE_DW_MVEBU
Armada-8K SoCs. The PCIe controller on Armada-8K is based on
DesignWare hardware.
config PCIE_FSL
bool "FSL PowerPC PCIe support"
depends on DM_PCI
help
Say Y here if you want to enable PCIe controller support on FSL
PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
This driver does not support SRIO_PCIE_BOOT feature.
config PCI_RCAR_GEN2
bool "Renesas RCar Gen2 PCIe driver"
depends on DM_PCI

1
drivers/pci/Makefile
View file

@ -31,6 +31,7 @@ obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \

610
drivers/pci/pcie_fsl.c Normal file
View file

@ -0,0 +1,610 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2019 NXP
*
* PCIe DM U-Boot driver for Freescale PowerPC SoCs
* Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
*/
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <mapmem.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include "pcie_fsl.h"
LIST_HEAD(fsl_pcie_list);
static int fsl_pcie_link_up(struct fsl_pcie *pcie);
static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
{
struct udevice *bus = pcie->bus;
if (!pcie->enabled)
return -ENXIO;
if (PCI_BUS(bdf) < bus->seq)
return -EINVAL;
if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
return -EINVAL;
if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
return -EINVAL;
if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
return -EINVAL;
return 0;
}
static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,
enum pci_size_t size)
{
struct fsl_pcie *pcie = dev_get_priv(bus);
ccsr_fsl_pci_t *regs = pcie->regs;
u32 val;
if (fsl_pcie_addr_valid(pcie, bdf)) {
*valuep = pci_get_ff(size);
return 0;
}
bdf = bdf - PCI_BDF(bus->seq, 0, 0);
val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
out_be32(&regs->cfg_addr, val);
sync();
switch (size) {
case PCI_SIZE_8:
*valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
break;
case PCI_SIZE_16:
*valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
(offset & 2)));
break;
case PCI_SIZE_32:
*valuep = in_le32(&regs->cfg_data);
break;
}
return 0;
}
static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
uint offset, ulong value,
enum pci_size_t size)
{
struct fsl_pcie *pcie = dev_get_priv(bus);
ccsr_fsl_pci_t *regs = pcie->regs;
u32 val;
u8 val_8;
u16 val_16;
u32 val_32;
if (fsl_pcie_addr_valid(pcie, bdf))
return 0;
bdf = bdf - PCI_BDF(bus->seq, 0, 0);
val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
out_be32(&regs->cfg_addr, val);
sync();
switch (size) {
case PCI_SIZE_8:
val_8 = value;
out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
break;
case PCI_SIZE_16:
val_16 = value;
out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
break;
case PCI_SIZE_32:
val_32 = value;
out_le32(&regs->cfg_data, val_32);
break;
}
return 0;
}
static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
ulong *valuep, enum pci_size_t size)
{
int ret;
struct udevice *bus = pcie->bus;
ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
offset, valuep, size);
return ret;
}
static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
ulong value, enum pci_size_t size)
{
struct udevice *bus = pcie->bus;
return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
offset, value, size);
}
static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
u8 *valuep)
{
ulong val;
int ret;
ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
*valuep = val;
return ret;
}
static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
u16 *valuep)
{
ulong val;
int ret;
ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
*valuep = val;
return ret;
}
static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
u32 *valuep)
{
ulong val;
int ret;
ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
*valuep = val;
return ret;
}
static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
u8 value)
{
return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
}
static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
u16 value)
{
return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
}
static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
u32 value)
{
return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
}
static int fsl_pcie_link_up(struct fsl_pcie *pcie)
{
ccsr_fsl_pci_t *regs = pcie->regs;
u16 ltssm;
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
ltssm = (in_be32(&regs->pex_csr0)
& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
return ltssm == LTSSM_L0_REV3;
}
fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
return ltssm == LTSSM_L0;
}
static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
{
u8 header_type;
fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
}
static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
{
struct pci_region *io, *mem, *pref;
pci_get_regions(pcie->bus, &io, &mem, &pref);
if (mem)
set_next_law(mem->phys_start,
law_size_bits(mem->size),
pcie->law_trgt_if);
if (io)
set_next_law(io->phys_start,
law_size_bits(io->size),
pcie->law_trgt_if);
return 0;
}
static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
{
ccsr_fsl_pci_t *regs = pcie->regs;
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
return;
}
fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
}
static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
int type, u64 phys, u64 bus_addr,
pci_size_t size)
{
ccsr_fsl_pci_t *regs = pcie->regs;
pot_t *po = &regs->pot[idx];
u32 war, sz;
if (idx < 0)
return -EINVAL;
out_be32(&po->powbar, phys >> 12);
out_be32(&po->potar, bus_addr >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
out_be32(&po->potear, bus_addr >> 44);
#else
out_be32(&po->potear, 0);
#endif
sz = (__ilog2_u64((u64)size) - 1);
war = POWAR_EN | sz;
if (type == PCI_REGION_IO)
war |= POWAR_IO_READ | POWAR_IO_WRITE;
else
war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
out_be32(&po->powar, war);
return 0;
}
static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
bool pf, u64 phys, u64 bus_addr,
pci_size_t size)
{
ccsr_fsl_pci_t *regs = pcie->regs;
pit_t *pi = &regs->pit[idx];
u32 sz = (__ilog2_u64(size) - 1);
u32 flag = PIWAR_LOCAL;
if (idx < 0)
return -EINVAL;
out_be32(&pi->pitar, phys >> 12);
out_be32(&pi->piwbar, bus_addr >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
out_be32(&pi->piwbear, bus_addr >> 44);
#else
out_be32(&pi->piwbear, 0);
#endif
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434))
flag = 0;
flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
if (pf)
flag |= PIWAR_PF;
out_be32(&pi->piwar, flag | sz);
return 0;
}
static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
{
struct pci_region *io, *mem, *pref;
int idx = 1; /* skip 0 */
pci_get_regions(pcie->bus, &io, &mem, &pref);
if (io)
/* ATU : OUTBOUND : IO */
fsl_pcie_setup_outbound_win(pcie, idx++,
PCI_REGION_IO,
io->phys_start,
io->bus_start,
io->size);
if (mem)
/* ATU : OUTBOUND : MEM */
fsl_pcie_setup_outbound_win(pcie, idx++,
PCI_REGION_MEM,
mem->phys_start,
mem->bus_start,
mem->size);
return 0;
}
static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
{
phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
u64 sz = min((u64)gd->ram_size, (1ull << 32));
pci_size_t pci_sz;
int idx;
if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
idx = 2;
else
idx = 3;
pci_sz = 1ull << __ilog2_u64(sz);
dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)sz);
/* if we aren't an exact power of two match, pci_sz is smaller
* round it up to the next power of two. We report the actual
* size to pci region tracking.
*/
if (pci_sz != sz)
sz = 2ull << __ilog2_u64(sz);
fsl_pcie_setup_inbound_win(pcie, idx--, true,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_BUS, sz);
#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
/*
* On 64-bit capable systems, set up a mapping for all of DRAM
* in high pci address space.
*/
pci_sz = 1ull << __ilog2_u64(gd->ram_size);
/* round up to the next largest power of two */
if (gd->ram_size > pci_sz)
pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
fsl_pcie_setup_inbound_win(pcie, idx--, true,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
#endif
return 0;
}
static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
{
fsl_pcie_setup_outbound_wins(pcie);
fsl_pcie_setup_inbound_wins(pcie);
return 0;
}
static int fsl_pcie_init_port(struct fsl_pcie *pcie)
{
ccsr_fsl_pci_t *regs = pcie->regs;
u32 val_32;
u16 val_16;
fsl_pcie_init_atmu(pcie);
if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) {
val_32 = 0;
fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
val_32 &= ~0x03;
fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
udelay(1);
}
if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) {
u16 ltssm;
int i;
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
/* assert PCIe reset */
setbits_be32(&regs->pdb_stat, 0x08000000);
(void)in_be32(&regs->pdb_stat);
udelay(1000);
/* clear PCIe reset */
clrbits_be32(&regs->pdb_stat, 0x08000000);
asm("sync;isync");
for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
udelay(1000);
} else {
fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
if (ltssm == 1) {
/* assert PCIe reset */
setbits_be32(&regs->pdb_stat, 0x08000000);
(void)in_be32(&regs->pdb_stat);
udelay(100);
/* clear PCIe reset */
clrbits_be32(&regs->pdb_stat, 0x08000000);
asm("sync;isync");
for (i = 0; i < 100 &&
!fsl_pcie_link_up(pcie); i++)
udelay(1000);
}
}
}
if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) &&
!fsl_pcie_link_up(pcie)) {
serdes_corenet_t *srds_regs;
srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
val_32 = in_be32(&srds_regs->srdspccr0);
if ((val_32 >> 28) == 3) {
int i;
out_be32(&srds_regs->srdspccr0, 2 << 28);
setbits_be32(&regs->pdb_stat, 0x08000000);
in_be32(&regs->pdb_stat);
udelay(100);
clrbits_be32(&regs->pdb_stat, 0x08000000);
asm("sync;isync");
for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
udelay(1000);
}
}
/*
* The Read-Only Write Enable bit defaults to 1 instead of 0.
* Set to 0 to protect the read-only registers.
*/
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815))
clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
/*
* Enable All Error Interrupts except
* - Master abort (pci)
* - Master PERR (pci)
* - ICCA (PCIe)
*/
out_be32(&regs->peer, ~0x20140);
/* set URR, FER, NFER (but not CER) */
fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
val_32 |= 0xf000e;
fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
/* Clear all error indications */
out_be32(&regs->pme_msg_det, 0xffffffff);
out_be32(&regs->pme_msg_int_en, 0xffffffff);
out_be32(&regs->pedr, 0xffffffff);
fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
if (val_16)
fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
if (val_16)
fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
return 0;
}
static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
{
ccsr_fsl_pci_t *regs = pcie->regs;
u32 val;
setbits_be32(&regs->dbi_ro_wr_en, 0x01);
fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);
val &= 0xff;
val |= PCI_CLASS_BRIDGE_PCI << 16;
fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);
clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
return 0;
}
static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
{
return fsl_pcie_fixup_classcode(pcie);
}
static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
{
fsl_pcie_config_ready(pcie);
return 0;
}
static int fsl_pcie_probe(struct udevice *dev)
{
struct fsl_pcie *pcie = dev_get_priv(dev);
ccsr_fsl_pci_t *regs = pcie->regs;
u16 val_16;
pcie->bus = dev;
pcie->block_rev = in_be32(&regs->block_rev1);
list_add(&pcie->list, &fsl_pcie_list);
pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
if (!pcie->enabled) {
printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
return 0;
}
fsl_pcie_setup_law(pcie);
pcie->mode = fsl_pcie_is_agent(pcie);
fsl_pcie_init_port(pcie);
printf("PCIe%d: %s ", pcie->idx, dev->name);
if (pcie->mode) {
printf("Endpoint");
fsl_pcie_init_ep(pcie);
} else {
printf("Root Complex");
fsl_pcie_init_rc(pcie);
}
if (!fsl_pcie_link_up(pcie)) {
printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
return 0;
}
fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
return 0;
}
static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
{
struct fsl_pcie *pcie = dev_get_priv(dev);
int ret;
pcie->regs = dev_remap_addr(dev);
if (!pcie->regs) {
pr_err("\"reg\" resource not found\n");
return -EINVAL;
}
ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
if (ret < 0) {
pr_err("\"law_trgt_if\" not found\n");
return ret;
}
pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000;
return 0;
}
static const struct dm_pci_ops fsl_pcie_ops = {
.read_config = fsl_pcie_read_config,
.write_config = fsl_pcie_write_config,
};
static const struct udevice_id fsl_pcie_ids[] = {
{ .compatible = "fsl,pcie-t2080" },
{ }
};
U_BOOT_DRIVER(fsl_pcie) = {
.name = "fsl_pcie",
.id = UCLASS_PCI,
.of_match = fsl_pcie_ids,
.ops = &fsl_pcie_ops,
.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
.probe = fsl_pcie_probe,
.priv_auto_alloc_size = sizeof(struct fsl_pcie),
};

56
drivers/pci/pcie_fsl.h Normal file
View file

@ -0,0 +1,56 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*
* PCIe DM U-Boot driver for Freescale PowerPC SoCs
* Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
*/
#ifndef _PCIE_FSL_H_
#define _PCIE_FSL_H_
#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
#define FSL_PCIE_CAP_ID 0x70
#else
#define FSL_PCIE_CAP_ID 0x4c
#endif
/* PCIe Device Control Register */
#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08)
/* PCIe Device Status Register */
#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a)
/* PCIe Link Control Register */
#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10)
/* PCIe Link Status Register */
#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12)
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS 0
#endif
#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
#define CONFIG_SYS_PCI_MEMORY_PHYS 0
#endif
#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024)
#endif
#define PEX_CSR0_LTSSM_MASK 0xFC
#define PEX_CSR0_LTSSM_SHIFT 2
#define LTSSM_L0_REV3 0x11
#define LTSSM_L0 0x16
struct fsl_pcie {
int idx;
struct udevice *bus;
void __iomem *regs;
u32 law_trgt_if; /* LAW target ID */
u32 block_rev; /* IP block revision */
bool mode; /* RC&EP mode flag */
bool enabled; /* Enable status */
struct list_head list;
};
extern struct list_head fsl_pcie_list;
#endif /* _PCIE_FSL_H_ */

50
drivers/pci/pcie_fsl_fixup.c Normal file
View file

@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2019 NXP
*
* PCIe Kernel DT fixup of DM U-Boot driver for Freescale PowerPC SoCs
* Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
*/
#include <common.h>
#ifdef CONFIG_OF_BOARD_SETUP
#include <dm.h>
#include <fdt_support.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include "pcie_fsl.h"
static void ft_fsl_pcie_setup(void *blob, struct fsl_pcie *pcie)
{
struct pci_controller *hose = dev_get_uclass_priv(pcie->bus);
fdt_addr_t regs_addr;
int off;
regs_addr = dev_read_addr(pcie->bus);
off = fdt_node_offset_by_compat_reg(blob, FSL_PCIE_COMPAT, regs_addr);
if (off < 0) {
printf("%s: Fail to find PCIe node@0x%pa\n",
FSL_PCIE_COMPAT, &regs_addr);
return;
}
if (!hose || !pcie->enabled)
fdt_del_node(blob, off);
else
fdt_pci_dma_ranges(blob, off, hose);
}
/* Fixup Kernel DT for PCIe */
void pci_of_setup(void *blob, bd_t *bd)
{
struct fsl_pcie *pcie;
list_for_each_entry(pcie, &fsl_pcie_list, list)
ft_fsl_pcie_setup(blob, pcie);
}
#else
void pci_of_setup(void *blob, bd_t *bd)
{
}
#endif

1
include/configs/BSC9132QDS.h
View file

@ -57,7 +57,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*

1
include/configs/C29XPCIE.h
View file

@ -66,7 +66,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*

1
include/configs/MPC8536DS.h
View file

@ -36,7 +36,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */

1
include/configs/MPC8544DS.h
View file

@ -16,7 +16,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8548CDS.h
View file

@ -20,7 +20,6 @@
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8568MDS.h
View file

@ -16,7 +16,6 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8569MDS.h
View file

@ -15,7 +15,6 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8572DS.h
View file

@ -27,7 +27,6 @@
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/P1010RDB.h
View file

@ -115,7 +115,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*

1
include/configs/P1022DS.h
View file

@ -81,7 +81,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENABLE_36BIT_PHYS

1
include/configs/P1023RDB.h
View file

@ -24,7 +24,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#ifndef __ASSEMBLY__

37
include/configs/T208xQDS.h
View file

@ -491,50 +491,51 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PCI
#if !defined(CONFIG_DM_PCI)
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#define CONFIG_PCI_INDIRECT_BRIDGE
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif

1
include/configs/T208xRDB.h
View file

@ -476,7 +476,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif

1
include/configs/UCP1020.h
View file

@ -17,7 +17,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#if defined(CONFIG_TARTGET_UCP1020T1)

1
include/configs/controlcenterd.h
View file

@ -204,7 +204,6 @@
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT

1
include/configs/p1_p2_rdb_pc.h
View file

@ -209,7 +209,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/p1_twr.h
View file

@ -34,7 +34,6 @@
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

1
include/configs/sbc8548.h
View file

@ -49,7 +49,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#endif
#ifdef CONFIG_PCIE1
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#endif
#define CONFIG_ENV_OVERWRITE

1
include/configs/xpedite537x.h
View file

@ -22,7 +22,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
/*
* Multicore config

1
include/configs/xpedite550x.h
View file

@ -22,7 +22,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
/*
* Multicore config