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imx: define ARCH_MXC for i.MX8/8M/7ULP

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Without this definition, fsl_esdhc will access reserved registers
on i.MX chips, so define ARCH_MXC to fix it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
This commit is contained in:
Peng Fan 2019-05-09 08:33:55 +00:00 committed by Stefano Babic
parent 75eba18321
commit 16529ff255
3 changed files with 6 additions and 0 deletions
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2
arch/arm/include/asm/arch-imx8/imx-regs.h
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@ -6,6 +6,8 @@
#ifndef __ASM_ARCH_IMX8_REGS_H__
#define __ASM_ARCH_IMX8_REGS_H__
#define ARCH_MXC
#define LPUART_BASE 0x5A060000
#define GPT1_BASE_ADDR 0x5D140000

2
arch/arm/include/asm/arch-imx8m/imx-regs.h
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@ -6,6 +6,8 @@
#ifndef __ASM_ARCH_IMX8M_REGS_H__
#define __ASM_ARCH_IMX8M_REGS_H__
#define ARCH_MXC
#include <asm/mach-imx/regs-lcdif.h>
#define ROM_VERSION_A0 0x800

2
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
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@ -8,6 +8,8 @@
#include <linux/sizes.h>
#define ARCH_MXC
#define CAAM_SEC_SRAM_BASE (0x26000000)
#define CAAM_SEC_SRAM_SIZE (SZ_32K)
#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)