Brad Griffis 6fe3e5ba66 arm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr path ... Enable HW leveling in RTC+DDR path. The mandate is to enable HW leveling bit and then wait for 1 ms before accessing any register. Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>		2019-05-05 08:48:50 -04:00
..
arc	ARC: [plat-axs10x]: migrate to DM_MMC	2019-04-18 09:12:38 +03:00
arm	arm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr path	2019-05-05 08:48:50 -04:00
m68k	m68k: ColdFire mcf5441x, add eSDHC support	2018-09-16 00:01:13 +02:00
microblaze	spl: fix linker size check off-by-one errors	2019-05-05 08:48:50 -04:00
mips	net: mscc: ocelot: Update DTS for Luton pcb90	2019-05-03 16:46:36 +02:00
nds32	dts: switch spi-flash to jedec, spi-nor compatible	2019-04-12 10:54:27 +05:30
nios2	.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore	2018-06-18 14:43:12 -04:00
powerpc	watchdog: mpc8xx_wdt: Watchdog driver and macros cleanup	2019-04-26 09:16:32 +02:00
riscv	dts: switch spi-flash to jedec, spi-nor compatible	2019-04-12 10:54:27 +05:30
sandbox	Various minor sandbox iumprovements	2019-04-24 12:27:29 -04:00
sh	sh: bitops: add hweight*() macros	2019-02-07 15:33:21 +05:30
x86	x86: dts: switch spi-flash to jedec, spi-nor compatible	2019-04-12 10:54:27 +05:30
xtensa	xtensa: use asm-generic/atomic.h	2018-09-25 21:49:18 -04:00
.gitignore
Kconfig	arch: armv8: Provide a way to disable cache maintenance ops	2019-05-05 08:48:50 -04:00