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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
mpc83xx: Introduce ARCH_MPC837X
Replace CONFIG_MPC837x with a proper CONFIG_ARCH_MPC837X Kconfig option. Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
parent
61abced70f
commit
8439e99ddb
11 changed files with 42 additions and 40 deletions
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@ -64,12 +64,14 @@ config TARGET_MPC8349ITX
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config TARGET_MPC837XEMDS
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bool "Support MPC837XEMDS"
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select ARCH_MPC837X
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select BOARD_EARLY_INIT_F
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imply CMD_SATA
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imply FSL_SATA
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config TARGET_MPC837XERDB
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bool "Support MPC837XERDB"
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select ARCH_MPC837X
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select BOARD_EARLY_INIT_F
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config TARGET_IDS8313
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@ -151,6 +153,9 @@ config ARCH_MPC8349
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config ARCH_MPC8360
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bool
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config ARCH_MPC837X
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bool
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source "board/esd/vme8349/Kconfig"
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source "board/freescale/mpc8308rdb/Kconfig"
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source "board/freescale/mpc8313erdb/Kconfig"
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@ -86,7 +86,7 @@ int get_clocks(void)
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u32 csb_clk;
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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u32 tsec1_clk;
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u32 tsec2_clk;
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u32 usbdr_clk;
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@ -123,11 +123,11 @@ int get_clocks(void)
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u32 brg_clk;
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC837X)
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u32 pciexp1_clk;
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u32 pciexp2_clk;
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#endif
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#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
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#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
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u32 sata_clk;
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#endif
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@ -156,7 +156,7 @@ int get_clocks(void)
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sccr = im->clk.sccr;
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
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case 0:
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tsec1_clk = 0;
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@ -177,7 +177,7 @@ int get_clocks(void)
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#endif
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#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
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case 0:
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usbdr_clk = 0;
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@ -198,7 +198,7 @@ int get_clocks(void)
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
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case 0:
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tsec2_clk = 0;
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@ -321,7 +321,7 @@ int get_clocks(void)
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i2c1_clk = enc_clk;
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#elif defined(CONFIG_FSL_ESDHC)
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i2c1_clk = sdhc_clk;
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#elif defined(CONFIG_MPC837x)
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#elif defined(CONFIG_ARCH_MPC837X)
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i2c1_clk = enc_clk;
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#elif defined(CONFIG_ARCH_MPC8309)
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i2c1_clk = csb_clk;
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@ -331,7 +331,7 @@ int get_clocks(void)
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC837X)
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switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
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case 0:
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pciexp1_clk = 0;
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@ -369,7 +369,7 @@ int get_clocks(void)
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}
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#endif
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#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
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#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
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switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
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case 0:
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sata_clk = 0;
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@ -449,7 +449,7 @@ int get_clocks(void)
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gd->arch.csb_clk = csb_clk;
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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gd->arch.tsec1_clk = tsec1_clk;
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gd->arch.tsec2_clk = tsec2_clk;
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gd->arch.usbdr_clk = usbdr_clk;
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@ -484,11 +484,11 @@ int get_clocks(void)
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gd->arch.brg_clk = brg_clk;
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC837X)
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gd->arch.pciexp1_clk = pciexp1_clk;
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gd->arch.pciexp2_clk = pciexp2_clk;
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#endif
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#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
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#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
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gd->arch.sata_clk = sata_clk;
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#endif
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gd->pci_clk = pci_sync_in;
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@ -559,7 +559,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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strmhz(buf, gd->arch.sdhc_clk));
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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printf(" TSEC1: %-4s MHz\n",
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strmhz(buf, gd->arch.tsec1_clk));
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printf(" TSEC2: %-4s MHz\n",
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@ -575,13 +575,13 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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strmhz(buf, gd->arch.usbmph_clk));
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC837X)
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printf(" PCIEXP1: %-4s MHz\n",
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strmhz(buf, gd->arch.pciexp1_clk));
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printf(" PCIEXP2: %-4s MHz\n",
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strmhz(buf, gd->arch.pciexp2_clk));
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#endif
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#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
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#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
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printf(" SATA: %-4s MHz\n",
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strmhz(buf, gd->arch.sata_clk));
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#endif
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@ -9,7 +9,7 @@
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#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
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defined(CONFIG_ARCH_MPC8315)
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#define MPC83XX_GPIO_CTRLRS 1
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#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
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#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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#define MPC83XX_GPIO_CTRLRS 2
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#else
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#define MPC83XX_GPIO_CTRLRS 0
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@ -36,7 +36,7 @@ struct arch_global_data {
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/* There are other clocks in the MPC83XX */
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u32 csb_clk;
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# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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u32 tsec1_clk;
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u32 tsec2_clk;
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u32 usbdr_clk;
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@ -54,11 +54,11 @@ struct arch_global_data {
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u32 lbiu_clk;
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u32 lclk_clk;
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# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC837X)
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u32 pciexp1_clk;
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u32 pciexp2_clk;
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# endif
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# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
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# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
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u32 sata_clk;
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# endif
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# if defined(CONFIG_ARCH_MPC8360)
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@ -759,7 +759,7 @@ typedef struct immap {
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u8 res12[0x1CF00];
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} immap_t;
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#elif defined(CONFIG_MPC837x)
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#elif defined(CONFIG_ARCH_MPC837X)
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typedef struct immap {
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sysconf83xx_t sysconf; /* System configuration */
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wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
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@ -14,7 +14,7 @@
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defined(CONFIG_ARCH_MPC8313) || \
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defined(CONFIG_ARCH_MPC8315) || \
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defined(CONFIG_ARCH_MPC834X) || \
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defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC837X)
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typedef struct spi8xxx {
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u8 res0[0x20]; /* 0x0-0x01f reserved */
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@ -170,7 +170,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
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switch (odt_rd_cfg) {
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case ODT_RD_ONLY_OTHER_DIMM:
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if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
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!IS_ENABLED(CONFIG_MPC837x)) {
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!IS_ENABLED(CONFIG_ARCH_MPC837X)) {
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debug("%s: odt_rd_cfg value %d invalid.\n",
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ofnode_get_name(node), odt_rd_cfg);
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return -EINVAL;
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@ -182,7 +182,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
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if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
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!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
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!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
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!IS_ENABLED(CONFIG_MPC837x)) {
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!IS_ENABLED(CONFIG_ARCH_MPC837X)) {
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debug("%s: odt_rd_cfg value %d invalid.\n",
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ofnode_get_name(node), odt_rd_cfg);
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return -EINVAL;
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@ -201,7 +201,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
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switch (odt_wr_cfg) {
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case ODT_WR_ONLY_OTHER_DIMM:
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if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
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!IS_ENABLED(CONFIG_MPC837x)) {
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!IS_ENABLED(CONFIG_ARCH_MPC837X)) {
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debug("%s: odt_wr_cfg value %d invalid.\n",
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ofnode_get_name(node), odt_wr_cfg);
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return -EINVAL;
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@ -213,7 +213,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
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if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
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!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
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!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
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!IS_ENABLED(CONFIG_MPC837x)) {
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!IS_ENABLED(CONFIG_ARCH_MPC837X)) {
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debug("%s: odt_wr_cfg value %d invalid.\n",
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ofnode_get_name(node), odt_wr_cfg);
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return -EINVAL;
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@ -11,7 +11,6 @@
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
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#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
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/*
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@ -12,7 +12,6 @@
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
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#define CONFIG_MPC837XERDB 1
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#define CONFIG_HWCONFIG
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@ -130,8 +130,8 @@
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#define SPCR_TSEC2EP_SHIFT (31-31)
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#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_MPC837x)
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/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
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defined(CONFIG_ARCH_MPC837X)
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/* SPCR bits - MPC8308, MPC831x and MPC837X specific */
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/* TSEC data priority */
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#define SPCR_TSECDP 0x00003000
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#define SPCR_TSECDP_SHIFT (31-19)
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#define SICRH_TSOBI1 0x00000002
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#define SICRH_TSOBI2 0x00000001
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#elif defined(CONFIG_MPC837x)
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/* SICRL bits - MPC837x specific */
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#elif defined(CONFIG_ARCH_MPC837X)
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/* SICRL bits - MPC837X specific */
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#define SICRL_USB_A 0xC0000000
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#define SICRL_USB_B 0x30000000
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#define SICRL_USB_B_SD 0x20000000
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#define SICRL_LDP_A 0x00000002
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#define SICRL_LDP_B 0x00000001
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/* SICRH bits - MPC837x specific */
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/* SICRH bits - MPC837X specific */
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#define SICRH_DDR 0x80000000
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#define SICRH_TSEC1_A 0x10000000
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#define SICRH_TSEC1_B 0x08000000
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#define HRCWL_SVCOD_DIV_8 0x20000000
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#define HRCWL_SVCOD_DIV_1 0x30000000
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#elif defined(CONFIG_MPC837x)
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#elif defined(CONFIG_ARCH_MPC837X)
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#define HRCWL_SVCOD 0x30000000
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#define HRCWL_SVCOD_SHIFT 28
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#define HRCWL_SVCOD_DIV_4 0x00000000
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#if defined(CONFIG_ARCH_MPC834X)
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#define HRCWH_ROM_LOC_PCI2 0x00200000
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#endif
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#if defined(CONFIG_MPC837x)
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#if defined(CONFIG_ARCH_MPC837X)
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#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
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#endif
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#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
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#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC837X)
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#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
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#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
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#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
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* RSR - Reset Status Register
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*/
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_MPC837x)
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defined(CONFIG_ARCH_MPC837X)
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#define RSR_RSTSRC 0xF0000000 /* Reset source */
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#define RSR_RSTSRC_SHIFT 28
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#else
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#define SCCR_TDMCM_2 0x00000020
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#define SCCR_TDMCM_3 0x00000030
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#elif defined(CONFIG_MPC837x)
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/* SCCR bits - MPC837x specific */
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#elif defined(CONFIG_ARCH_MPC837X)
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/* SCCR bits - MPC837X specific */
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#define SCCR_TSEC1CM 0xc0000000
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#define SCCR_TSEC1CM_SHIFT 30
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#define SCCR_TSEC1CM_0 0x00000000
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#elif defined(CONFIG_ARCH_MPC832X)
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#define CSCONFIG_ODT_RD_CFG 0x00400000
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#define CSCONFIG_ODT_WR_CFG 0x00040000
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#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_MPC837x)
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#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
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#define CSCONFIG_ODT_RD_NEVER 0x00000000
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#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
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#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
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@ -1226,7 +1226,6 @@ CONFIG_MPC832XEMDS
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CONFIG_MPC8349ITX
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CONFIG_MPC837XEMDS
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CONFIG_MPC837XERDB
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CONFIG_MPC837x
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CONFIG_MPC83XX_GPIO
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CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
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CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
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