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https://github.com/AsahiLinux/u-boot
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- mxsfb DM_VIDEO conversion
- splash fix for DM_VIDEO configurations - meson HDMI fix for boards without hdmi-supply regulator -----BEGIN PGP SIGNATURE----- iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCXP4oqg4cYWd1c3RAZGVu eC5kZQAKCRBM6ATMmsalXLDlAJ422AAeTYTWf0wrfWz11YUWggd7HQCfcsY+UjgL SM69apyCTV0ZGo5uVzE= =bQQc -----END PGP SIGNATURE----- Merge tag 'video-updates-for-2019.07-rc3' of git://git.denx.de/u-boot-video - mxsfb DM_VIDEO conversion - splash fix for DM_VIDEO configurations - meson HDMI fix for boards without hdmi-supply regulator
This commit is contained in:
commit
99e14d5249
14 changed files with 252 additions and 64 deletions
|
@ -11,8 +11,10 @@
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compatible = "toradex,imx7d-colibri-emmc", "fsl,imx7d";
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aliases {
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u-boot,dm-pre-reloc;
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mmc0 = &usdhc3;
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mmc1 = &usdhc1;
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display1 = &lcdif;
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};
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chosen {
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@ -111,3 +111,31 @@
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>;
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};
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};
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&lcdif {
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u-boot,dm-pre-reloc;
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status = "okay";
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display-timings {
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native-mode = <&timing_vga>;
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/* Standard VGA timing */
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timing_vga: 640x480 {
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u-boot,dm-pre-reloc;
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clock-frequency = <25175000>;
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hactive = <640>;
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vactive = <480>;
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hback-porch = <48>;
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hfront-porch = <16>;
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vback-porch = <33>;
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vfront-porch = <10>;
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hsync-len = <96>;
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vsync-len = <2>;
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de-active = <1>;
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hsync-active = <0>;
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vsync-active = <0>;
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pixelclk-active = <0>;
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};
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};
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};
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@ -298,7 +298,7 @@ void arch_preboot_os(void)
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/* disable video before launching O/S */
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ipuv3_fb_shutdown();
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#endif
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#if defined(CONFIG_VIDEO_MXS)
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#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
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lcdif_power_down();
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#endif
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}
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@ -369,7 +369,7 @@ void s_init(void)
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void reset_misc(void)
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{
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#ifndef CONFIG_SPL_BUILD
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#ifdef CONFIG_VIDEO_MXS
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#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
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lcdif_power_down();
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#endif
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#endif
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13
common/lcd.c
13
common/lcd.c
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@ -171,8 +171,7 @@ int drv_lcd_init(void)
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void lcd_clear(void)
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{
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int bg_color;
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char *s;
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ulong addr;
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__maybe_unused ulong addr;
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static int do_splash = 1;
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#if LCD_BPP == LCD_COLOR8
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/* Setting the palette */
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@ -222,14 +221,10 @@ void lcd_clear(void)
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/* Paint the logo and retrieve LCD base address */
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debug("[LCD] Drawing the logo...\n");
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if (do_splash) {
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s = env_get("splashimage");
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if (s) {
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if (splash_display() == 0) {
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do_splash = 0;
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addr = simple_strtoul(s, NULL, 16);
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if (lcd_splash(addr) == 0) {
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lcd_sync();
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return;
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}
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lcd_sync();
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return;
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}
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}
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@ -80,11 +80,23 @@ void splash_get_pos(int *x, int *y)
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}
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#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
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#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_LCD)
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int lcd_splash(ulong addr)
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/*
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* Common function to show a splash image if env("splashimage") is set.
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* Is used for both dm_video and lcd video stacks. For additional
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* details please refer to doc/README.splashprepare.
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*/
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#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
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int splash_display(void)
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{
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ulong addr;
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char *s;
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int x = 0, y = 0, ret;
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s = env_get("splashimage");
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if (!s)
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return -EINVAL;
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addr = simple_strtoul(s, NULL, 16);
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ret = splash_screen_prepare();
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if (ret)
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return ret;
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@ -16,6 +16,7 @@
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#include <malloc.h>
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#include <stdio_dev.h>
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#include <serial.h>
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#include <splash.h>
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#if defined(CONFIG_SYS_I2C)
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#include <i2c.h>
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@ -366,6 +367,9 @@ int stdio_add_devices(void)
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if (ret)
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printf("%s: Video device failed (ret=%d)\n", __func__, ret);
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#endif /* !CONFIG_SYS_CONSOLE_IS_IN_ENV */
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#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
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splash_display();
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#endif /* CONFIG_SPLASH_SCREEN && CONFIG_CMD_BMP */
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#else
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# if defined(CONFIG_LCD)
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drv_lcd_init ();
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@ -85,3 +85,4 @@ CONFIG_DM_VIDEO=y
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CONFIG_VIDEO_IPUV3=y
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CONFIG_FAT_WRITE=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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CONFIG_SYS_WHITE_ON_BLACK=y
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@ -63,6 +63,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
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CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
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CONFIG_CI_UDC=y
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CONFIG_USB_GADGET_DOWNLOAD=y
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CONFIG_VIDEO=y
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CONFIG_DM_VIDEO=y
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CONFIG_FAT_WRITE=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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@ -64,3 +64,4 @@ CONFIG_DM_VIDEO=y
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CONFIG_VIDEO_TEGRA20=y
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CONFIG_CONSOLE_SCROLL_LINES=10
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CONFIG_OF_LIBFDT_OVERLAY=y
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CONFIG_SYS_WHITE_ON_BLACK=y
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@ -361,13 +361,19 @@ static int meson_dw_hdmi_probe(struct udevice *dev)
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priv->hdmi.i2c_clk_high = 0x67;
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priv->hdmi.i2c_clk_low = 0x78;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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ret = device_get_supply_regulator(dev, "hdmi-supply", &supply);
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if (ret)
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if (ret && ret != -ENOENT) {
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pr_err("Failed to get HDMI regulator\n");
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return ret;
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}
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ret = regulator_set_enable(supply, true);
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if (ret)
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return ret;
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if (!ret) {
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ret = regulator_set_enable(supply, true);
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if (ret)
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return ret;
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}
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#endif
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ret = reset_get_bulk(dev, &resets);
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if (ret)
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@ -5,22 +5,26 @@
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* Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <linux/errno.h>
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#include <malloc.h>
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#include <video.h>
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#include <video_fb.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/mach-imx/dma.h>
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#include <asm/io.h>
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#include "videomodes.h"
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#define PS2KHZ(ps) (1000000000UL / (ps))
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#define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
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#define BITS_PP 18
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#define BYTES_PP 4
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static GraphicDevice panel;
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struct mxs_dma_desc desc;
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/**
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@ -46,8 +50,7 @@ __weak void mxsfb_system_setup(void)
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* le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
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*/
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static void mxs_lcd_init(GraphicDevice *panel,
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struct ctfb_res_modes *mode, int bpp)
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static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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uint32_t word_len = 0, bus_width = 0;
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@ -112,8 +115,8 @@ static void mxs_lcd_init(GraphicDevice *panel,
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writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
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®s->hw_lcdif_vdctrl4);
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writel(panel->frameAdrs, ®s->hw_lcdif_cur_buf);
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writel(panel->frameAdrs, ®s->hw_lcdif_next_buf);
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writel(fb_addr, ®s->hw_lcdif_cur_buf);
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writel(fb_addr, ®s->hw_lcdif_next_buf);
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/* Flush FIFO first */
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writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
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@ -130,16 +133,47 @@ static void mxs_lcd_init(GraphicDevice *panel,
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writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
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}
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void lcdif_power_down(void)
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static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, u32 fb)
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{
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/* Start framebuffer */
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mxs_lcd_init(fb, mode, bpp);
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#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
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/*
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* If the LCD runs in system mode, the LCD refresh has to be triggered
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* manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
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* having to set this bit manually after every single change in the
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* framebuffer memory, we set up specially crafted circular DMA, which
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* sets the RUN bit, then waits until it gets cleared and repeats this
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* infinitelly. This way, we get smooth continuous updates of the LCD.
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*/
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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memset(&desc, 0, sizeof(struct mxs_dma_desc));
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desc.address = (dma_addr_t)&desc;
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desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
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MXS_DMA_DESC_WAIT4END |
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(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
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desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
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desc.cmd.next = (uint32_t)&desc.cmd;
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/* Execute the DMA chain. */
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mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
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#endif
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return 0;
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}
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static int mxs_remove_common(u32 fb)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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int timeout = 1000000;
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if (!panel.frameAdrs)
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return;
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if (!fb)
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return -EINVAL;
|
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|
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writel(panel.frameAdrs, ®s->hw_lcdif_cur_buf_reg);
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writel(panel.frameAdrs, ®s->hw_lcdif_next_buf_reg);
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writel(fb, ®s->hw_lcdif_cur_buf_reg);
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writel(fb, ®s->hw_lcdif_next_buf_reg);
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writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
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while (--timeout) {
|
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if (readl(®s->hw_lcdif_ctrl1_reg) &
|
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|
@ -148,13 +182,25 @@ void lcdif_power_down(void)
|
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udelay(1);
|
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}
|
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mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
|
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|
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return 0;
|
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}
|
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|
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#ifndef CONFIG_DM_VIDEO
|
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|
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static GraphicDevice panel;
|
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|
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void lcdif_power_down(void)
|
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{
|
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mxs_remove_common(panel.frameAdrs);
|
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}
|
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|
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void *video_hw_init(void)
|
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{
|
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int bpp = -1;
|
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int ret = 0;
|
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char *penv;
|
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void *fb;
|
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void *fb = NULL;
|
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struct ctfb_res_modes mode;
|
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|
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puts("Video: ");
|
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|
@ -169,8 +215,7 @@ void *video_hw_init(void)
|
|||
bpp = video_get_params(&mode, penv);
|
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|
||||
/* fill in Graphic device struct */
|
||||
sprintf(panel.modeIdent, "%dx%dx%d",
|
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mode.xres, mode.yres, bpp);
|
||||
sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
|
||||
|
||||
panel.winSizeX = mode.xres;
|
||||
panel.winSizeY = mode.yres;
|
||||
|
@ -213,31 +258,125 @@ void *video_hw_init(void)
|
|||
|
||||
printf("%s\n", panel.modeIdent);
|
||||
|
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/* Start framebuffer */
|
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mxs_lcd_init(&panel, &mode, bpp);
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
|
||||
/*
|
||||
* If the LCD runs in system mode, the LCD refresh has to be triggered
|
||||
* manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
|
||||
* having to set this bit manually after every single change in the
|
||||
* framebuffer memory, we set up specially crafted circular DMA, which
|
||||
* sets the RUN bit, then waits until it gets cleared and repeats this
|
||||
* infinitelly. This way, we get smooth continuous updates of the LCD.
|
||||
*/
|
||||
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
|
||||
|
||||
memset(&desc, 0, sizeof(struct mxs_dma_desc));
|
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desc.address = (dma_addr_t)&desc;
|
||||
desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
|
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MXS_DMA_DESC_WAIT4END |
|
||||
(1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
|
||||
desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
|
||||
desc.cmd.next = (uint32_t)&desc.cmd;
|
||||
|
||||
/* Execute the DMA chain. */
|
||||
mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
|
||||
#endif
|
||||
ret = mxs_probe_common(&mode, bpp, (u32)fb);
|
||||
if (ret)
|
||||
goto dealloc_fb;
|
||||
|
||||
return (void *)&panel;
|
||||
|
||||
dealloc_fb:
|
||||
free(fb);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
#else /* ifndef CONFIG_DM_VIDEO */
|
||||
|
||||
static int mxs_video_probe(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
|
||||
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
|
||||
struct ctfb_res_modes mode;
|
||||
struct display_timing timings;
|
||||
int bpp = -1;
|
||||
u32 fb_start, fb_end;
|
||||
int ret;
|
||||
|
||||
debug("%s() plat: base 0x%lx, size 0x%x\n",
|
||||
__func__, plat->base, plat->size);
|
||||
|
||||
ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get any display timings\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mode.xres = timings.hactive.typ;
|
||||
mode.yres = timings.vactive.typ;
|
||||
mode.left_margin = timings.hback_porch.typ;
|
||||
mode.right_margin = timings.hfront_porch.typ;
|
||||
mode.upper_margin = timings.vback_porch.typ;
|
||||
mode.lower_margin = timings.vfront_porch.typ;
|
||||
mode.hsync_len = timings.hsync_len.typ;
|
||||
mode.vsync_len = timings.vsync_len.typ;
|
||||
mode.pixclock = HZ2PS(timings.pixelclock.typ);
|
||||
|
||||
bpp = BITS_PP;
|
||||
|
||||
ret = mxs_probe_common(&mode, bpp, plat->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
switch (bpp) {
|
||||
case 24:
|
||||
case 18:
|
||||
uc_priv->bpix = VIDEO_BPP32;
|
||||
break;
|
||||
case 16:
|
||||
uc_priv->bpix = VIDEO_BPP16;
|
||||
break;
|
||||
case 8:
|
||||
uc_priv->bpix = VIDEO_BPP8;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
uc_priv->xsize = mode.xres;
|
||||
uc_priv->ysize = mode.yres;
|
||||
|
||||
/* Enable dcache for the frame buffer */
|
||||
fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
|
||||
fb_end = plat->base + plat->size;
|
||||
fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
|
||||
mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
|
||||
DCACHE_WRITEBACK);
|
||||
video_set_flush_dcache(dev, true);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxs_video_bind(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
|
||||
struct display_timing timings;
|
||||
int ret;
|
||||
|
||||
ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get any display timings\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
plat->size = timings.hactive.typ * timings.vactive.typ * BYTES_PP;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxs_video_remove(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
|
||||
|
||||
mxs_remove_common(plat->base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id mxs_video_ids[] = {
|
||||
{ .compatible = "fsl,imx23-lcdif" },
|
||||
{ .compatible = "fsl,imx28-lcdif" },
|
||||
{ .compatible = "fsl,imx7ulp-lcdif" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mxs_video) = {
|
||||
.name = "mxs_video",
|
||||
.id = UCLASS_VIDEO,
|
||||
.of_match = mxs_video_ids,
|
||||
.bind = mxs_video_bind,
|
||||
.probe = mxs_video_probe,
|
||||
.remove = mxs_video_remove,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
#endif /* ifndef CONFIG_DM_VIDEO */
|
||||
|
|
|
@ -225,7 +225,7 @@
|
|||
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
|
||||
#define DFU_DEFAULT_POLL_TIMEOUT 300
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
|
||||
#define CONFIG_VIDEO_MXS
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
|
|
|
@ -66,10 +66,10 @@ void splash_get_pos(int *x, int *y);
|
|||
static inline void splash_get_pos(int *x, int *y) { }
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_LCD)
|
||||
int lcd_splash(ulong addr);
|
||||
#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
|
||||
int splash_display(void);
|
||||
#else
|
||||
static inline int lcd_splash(ulong addr)
|
||||
static inline int splash_display(void)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue