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rockchip: rk3288: move configure_l2ctlr back to rk3288
The configure_l2ctlr() is used only by rk3288, do not need to locate in sys_proto.h Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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ccab9e7ee3
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2 changed files with 22 additions and 22 deletions
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@ -6,28 +6,6 @@
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#ifndef _ASM_ARCH_SYS_PROTO_H
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#define _ASM_ARCH_SYS_PROTO_H
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#ifdef CONFIG_ROCKCHIP_RK3288
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#include <asm/armv7.h>
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static void configure_l2ctlr(void)
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{
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uint32_t l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#endif /* CONFIG_ROCKCHIP_RK3288 */
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/* provided to defeat compiler optimisation in board_init_f() */
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void gru_dummy_function(int i);
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@ -2,12 +2,34 @@
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*/
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#include <asm/armv7.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/grf_rk3288.h>
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#define GRF_BASE 0xff770000
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#ifdef CONFIG_SPL_BUILD
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static void configure_l2ctlr(void)
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{
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u32 l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#endif
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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