mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 07:31:15 +00:00
mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
parent
8a81bfd271
commit
133ec60284
44 changed files with 35 additions and 61 deletions
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@ -281,7 +281,7 @@ long int spd_sdram()
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/*
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* Set up LAWBAR for all of DDR.
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*/
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ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
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debug("DDR:bar=0x%08x\n", ecm->bar);
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debug("DDR:ar=0x%08x\n", ecm->ar);
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@ -33,7 +33,7 @@ static long fixed_sdram(void)
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
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CONFIG_SYS_SDRAM_BASE & 0xfffff000);
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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@ -61,7 +61,7 @@ static long fixed_sdram(void)
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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sync();
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return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
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return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
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}
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int dram_init(void)
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@ -47,7 +47,7 @@ static long fixed_sdram(void)
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volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
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@ -57,12 +57,12 @@ static long fixed_sdram(void)
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*/
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__udelay(50000);
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
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#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
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#warning Chip select bounds is only configurable in 16MB increments
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#endif
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im->ddr.csbnds[0].csbnds =
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
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((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
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CSBNDS_EA);
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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@ -44,7 +44,7 @@ static long fixed_sdram(void)
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
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@ -91,7 +91,7 @@ int fixed_sdram(void)
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u32 ddr_size = msize << 20; /* DDR size in bytes */
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u32 ddr_size_log2 = __ilog2(ddr_size);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CONFIG_SYS_DDR_SIZE != 256)
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@ -112,12 +112,12 @@ int fixed_sdram(void)
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
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#else
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
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#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
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#warning Chip select bounds is only configurable in 16MB increments
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#endif
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im->ddr.csbnds[2].csbnds =
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
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((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
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CSBNDS_EA_SHIFT) & CSBNDS_EA);
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im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
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@ -37,14 +37,14 @@ int fixed_sdram(void)
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
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#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
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#warning Chip select bounds is only configurable in 16MB increments
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#endif
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im->ddr.csbnds[0].csbnds =
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
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((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
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CSBNDS_EA_SHIFT) & CSBNDS_EA);
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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@ -252,7 +252,7 @@ int fixed_sdram(void)
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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#if (CONFIG_SYS_DDR_SIZE != 512)
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@ -95,7 +95,7 @@ int fixed_sdram(void)
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
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@ -34,7 +34,7 @@ static long fixed_sdram(void)
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
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CONFIG_SYS_SDRAM_BASE & 0xfffff000);
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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@ -62,7 +62,7 @@ static long fixed_sdram(void)
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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sync();
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return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
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return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
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}
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int dram_init(void)
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@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config)
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
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(CONFIG_SYS_SDRAM_BASE & 0xfffff000));
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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sync();
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@ -29,7 +29,7 @@ static long fixed_sdram(void)
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
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CONFIG_SYS_SDRAM_BASE & 0xfffff000);
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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@ -57,7 +57,7 @@ static long fixed_sdram(void)
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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sync();
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return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
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return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
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}
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int dram_init(void)
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@ -79,19 +79,19 @@ int fixed_sdram(void)
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u32 ddr_size = msize << 20; /* DDR size in bytes */
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u32 ddr_size_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CONFIG_SYS_DDR_SIZE != 256)
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#warning Currently any ddr size other than 256 is not supported
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#endif
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
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#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
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#warning Chip select bounds is only configurable in 16MB increments
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#endif
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im->ddr.csbnds[2].csbnds =
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
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((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
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CSBNDS_EA_SHIFT) & CSBNDS_EA);
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im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
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@ -38,7 +38,7 @@ static long fixed_sdram(void)
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
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(CONFIG_SYS_SDRAM_BASE & 0xfffff000));
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out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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@ -48,12 +48,12 @@ static long fixed_sdram(void)
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*/
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__udelay(50000);
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
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#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
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#warning Chip select bounds is only configurable in 16MB increments
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#endif
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out_be32(&im->ddr.csbnds[0].csbnds,
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
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((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
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CSBNDS_EA));
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out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
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@ -23,8 +23,12 @@
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* 0x80_8000_0000 ~ 0xff_ffff_ffff
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*/
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#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
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#ifdef CONFIG_MPC83xx
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
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#else
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
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#endif
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#endif
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#ifdef CONFIG_PPC
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#include <asm/fsl_law.h>
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@ -37,7 +37,6 @@
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
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| DDRCDR_PZ_LOZ \
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@ -87,7 +87,6 @@
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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/*
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* Manually set up DDR parameters, as this board does not
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@ -59,7 +59,6 @@
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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/*
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* Manually set up DDR parameters, as this board does not
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@ -35,7 +35,6 @@
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
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| DDRCDR_PZ_LOZ \
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@ -24,7 +24,6 @@
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#undef CONFIG_SPD_EEPROM
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#if defined(CONFIG_SPD_EEPROM)
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@ -21,7 +21,6 @@
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
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#undef CONFIG_SPD_EEPROM
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#undef CONFIG_DDR_32BIT
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
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| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#undef CONFIG_DDR_2T_TIMING
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@ -53,7 +53,6 @@
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#undef CONFIG_DDR_32BIT
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
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| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#undef CONFIG_DDR_2T_TIMING
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@ -143,7 +143,6 @@
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x2000
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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*/
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/* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
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#undef CONFIG_DDR_ECC /* only for ECC DDR module */
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#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
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@ -52,7 +52,6 @@
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#undef CONFIG_DDR_32BIT
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
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| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
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#define CONFIG_DDR_2T_TIMING
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|
|
|
@ -25,7 +25,6 @@
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* DDR Setup
|
||||
*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
|
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| DDRCDR_PZ_LOZ \
|
||||
|
|
|
@ -52,7 +52,6 @@
|
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* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
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||||
|
||||
/*
|
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* Manually set up DDR parameters,
|
||||
|
|
|
@ -46,7 +46,6 @@
|
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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||||
|
||||
|
|
|
@ -31,7 +31,6 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
|
|
|
@ -51,7 +51,6 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
|
|
|
@ -51,7 +51,6 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
|
|
|
@ -58,7 +58,6 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
|
|
|
@ -51,7 +51,6 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
|
|
|
@ -50,7 +50,6 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
|
|
|
@ -40,7 +40,6 @@
|
|||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
|
||||
| DDRCDR_PZ_LOZ \
|
||||
|
|
|
@ -47,7 +47,6 @@
|
|||
#undef CONFIG_DDR_32BIT
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
|
||||
#define CONFIG_DDR_2T_TIMING
|
||||
|
|
|
@ -25,7 +25,6 @@
|
|||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
|
||||
| DDRCDR_PZ_LOZ \
|
||||
|
|
|
@ -48,7 +48,6 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
|
|
|
@ -51,7 +51,6 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
|
|
|
@ -51,7 +51,6 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
|
|
|
@ -35,7 +35,6 @@
|
|||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
|
||||
/*
|
||||
* Manually set up DDR parameters, as this board does not
|
||||
|
|
|
@ -52,7 +52,6 @@
|
|||
#undef CONFIG_DDR_32BIT
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
|
||||
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
|
||||
#define CONFIG_DDR_2T_TIMING
|
||||
|
|
Loading…
Reference in a new issue