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rockchip: px5 update dts for spl/tpl

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TPL need dmc to init ddr sdram, and emmc, boot-order.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
Kever Yang 2019-03-29 22:48:25 +08:00
parent 579a168466
commit 4d9dd40d68
1 changed files with 29 additions and 0 deletions
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29
arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
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@ -2,6 +2,27 @@
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
/ {
chosen {
u-boot,spl-boot-order = &emmc;
};
};
&dmc {
u-boot,dm-pre-reloc;
/*
* PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
* See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
* details on the 'rockchip,memory-schedule' property and how it
* affects the physical-address to device-address mapping.
*/
rockchip,memory-schedule = <DMC_MSCH_CBRD>;
rockchip,ddr-frequency = <800000000>;
rockchip,ddr-speed-bin = <DDR3_1600K>;
status = "okay";
};
&pinctrl {
u-boot,dm-pre-reloc;
@ -20,6 +41,10 @@
u-boot,dm-pre-reloc;
};
&sgrf {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
@ -31,3 +56,7 @@
&uart4 {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};