mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
mcx: remove board
This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit is contained in:
Bartosz Golaszewski
Tom Rini
parent
2aa20c43e4
commit
d7cc0e4d79
9 changed files with 0 additions and 926 deletions
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@ -3596,7 +3596,6 @@
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#define MACH_TYPE_TAISHAN 3653
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#define MACH_TYPE_TOUCHLINK 3654
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#define MACH_TYPE_STM32F103ZE 3655
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#define MACH_TYPE_MCX 3656
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#define MACH_TYPE_STM_NMHDK_FLI7610 3657
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#define MACH_TYPE_TOP28X 3658
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#define MACH_TYPE_OKL4VP_MICROVISOR 3659
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@ -105,12 +105,6 @@ config TARGET_TRICORDER
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bool "Tricorder"
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select OMAP3_GPIO_2
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config TARGET_MCX
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bool "MCX"
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select BOARD_LATE_INIT
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select OMAP3_GPIO_2 if USB_EHCI_HCD
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select OMAP3_GPIO_5 if USB_EHCI_HCD
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config TARGET_OMAP3_LOGIC
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bool "OMAP3 Logic"
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select BOARD_LATE_INIT
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@ -189,7 +183,6 @@ source "board/logicpd/zoom1/Kconfig"
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source "board/ti/am3517crane/Kconfig"
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source "board/pandora/Kconfig"
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source "board/corscience/tricorder/Kconfig"
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source "board/htkw/mcx/Kconfig"
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source "board/logicpd/omap3som/Kconfig"
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source "board/nokia/rx51/Kconfig"
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source "board/technexion/tao3530/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_MCX
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config SYS_BOARD
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default "mcx"
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config SYS_VENDOR
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default "htkw"
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config SYS_CONFIG_NAME
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default "mcx"
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endif
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@ -1,6 +0,0 @@
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MCX BOARD
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M: Anatolij Gustschin <agust@denx.de>
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S: Maintained
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F: board/htkw/mcx/
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F: include/configs/mcx.h
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F: configs/mcx_defconfig
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@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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#
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# Based on ti/evm/Makefile
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obj-y := mcx.o
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@ -1,141 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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*
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* Based on ti/evm/evm.c
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include <asm/gpio.h>
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#include <asm/omap_gpio.h>
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#include <asm/arch/dss.h>
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#include <asm/arch/clock.h>
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#include <errno.h>
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#include <i2c.h>
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#ifdef CONFIG_USB_EHCI_HCD
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#include <usb.h>
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#include <asm/ehci-omap.h>
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#endif
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#include "mcx.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define HOT_WATER_BUTTON 42
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#define LCD_OUTPUT 55
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/* Address of the framebuffer in RAM. */
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#define FB_START_ADDRESS 0x88000000
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#ifdef CONFIG_USB_EHCI_HCD
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
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}
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int ehci_hcd_stop(int index)
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{
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return omap_ehci_hcd_stop();
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}
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#endif
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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gpio_direction_output(LCD_OUTPUT, 0);
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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if (gpio_request(HOT_WATER_BUTTON, "hot-water-button") < 0) {
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puts("Failed to get hot-water-button pin\n");
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return -ENODEV;
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}
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gpio_direction_input(HOT_WATER_BUTTON);
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/*
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* if hot-water-button is pressed
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* change bootcmd
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*/
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if (gpio_get_value(HOT_WATER_BUTTON))
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return 0;
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env_set("bootcmd", "run swupdate");
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return 0;
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}
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#endif
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_MCX();
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}
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#if defined(CONFIG_MMC_OMAP_HS)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
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static struct panel_config lcd_cfg = {
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.timing_h = PANEL_TIMING_H(40, 40, 48),
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.timing_v = PANEL_TIMING_V(29, 13, 3),
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.pol_freq = 0x00003000, /* Pol Freq */
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.divisor = 0x0001000E,
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.panel_type = 0x01, /* TFT */
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.data_lines = 0x03, /* 24 Bit RGB */
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.load_mode = 0x02, /* Frame Mode */
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.panel_color = 0,
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.lcd_size = PANEL_LCD_SIZE(800, 480),
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.gfx_format = GFXFORMAT_RGB24_UNPACKED,
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};
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int board_video_init(void)
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{
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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void *fb;
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fb = (void *)FB_START_ADDRESS;
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lcd_cfg.frame_buffer = fb;
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setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
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setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
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omap3_dss_panel_config(&lcd_cfg);
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omap3_dss_enable();
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return 0;
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}
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#endif
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@ -1,400 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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*
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* Based on ti/evm/evm.h
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*/
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#ifndef _AM3517EVM_H_
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#define _AM3517EVM_H_
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"HTKW mcx Board",
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"NAND",
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};
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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#define MUX_MCX() \
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/* SDRC */\
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
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MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
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MUX_VAL(CP(SDRC_CKE0), (M0)) \
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MUX_VAL(CP(SDRC_CKE1), (M0)) \
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MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
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/*sdrc_strben_dly0*/\
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MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
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/*sdrc_strben_dly1*/\
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/* GPMC */\
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MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
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/* GPIO_43 LCD buffer enable */ \
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
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/* GPIO_57 TS_PenIRQn */\
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MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
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/* GPIO_58 ETHERNET RESET */\
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MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
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/* GPIO_61 SD-CARD CD */ \
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MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
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/* GPIO_62 Nand write protect, keep enabled */ \
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
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/* GPIO_65 SD-CARD WP */\
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/* DSS */\
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
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MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
|
||||
/* CAMERA */\
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
|
||||
/* MMC */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_131 LCD Enable */ \
|
||||
MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_132 USB host Enable */\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_133 HDMI PD */\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
|
||||
/* McBSP */\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
|
||||
\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_152 USB phy2 reset */\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO_153 */\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
|
||||
/* GPIO_154 USB phy1 reset */\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO_155 TS_BUSY */\
|
||||
/* UART */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
|
||||
\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
|
||||
/* I2C */\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) \
|
||||
/* GPIO_170 Touchscreen ISR */\
|
||||
/* McSPI */\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat7 */\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat4 */\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat5 */\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat6 */\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
|
||||
/* HSUSB2_dat3 */\
|
||||
/* CCDC */\
|
||||
MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
|
||||
/* CCDC_FIELD: gpio_95, uP-TXD4 */ \
|
||||
MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \
|
||||
/* CCDC_HD: gpio_96, uP-RTS4# */ \
|
||||
MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \
|
||||
/* CCDC_VD: gpio_97, uP-CTS4# */ \
|
||||
MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \
|
||||
/* CCDC_WEN: gpio_98, uP-RXD4 */ \
|
||||
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \
|
||||
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
|
||||
/* RMII */\
|
||||
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
|
||||
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
|
||||
MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
|
||||
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
|
||||
/* HECC */\
|
||||
MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M0)) \
|
||||
/* HSUSB */\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
|
||||
/* HDQ */\
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
|
||||
/* Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
|
||||
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
|
||||
\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
|
||||
/* JTAG */\
|
||||
MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
|
||||
/* ETK (ES2 onwards) */\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
|
||||
/* hsusb1_stp */ \
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
|
||||
/* hsusb1_clk */\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
|
||||
/* Die to Die */\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
|
||||
|
||||
#endif
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
# CONFIG_SYS_THUMB_BUILD is not set
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80008000
|
||||
# CONFIG_SPL_GPIO_SUPPORT is not set
|
||||
CONFIG_TARGET_MCX=y
|
||||
CONFIG_EMIF4=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SPL=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_SPL_TEXT_BASE=0x40200000
|
||||
# CONFIG_SPL_FS_EXT4 is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="mcx # "
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),6m(k_recovery),8m(fs_recovery),-(common_data)"
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||
CONFIG_SPL_NAND_SIMPLE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_DRIVER_TI_EMAC=y
|
||||
CONFIG_CONS_INDEX=3
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_ULPI_VIEWPORT_OMAP=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_VIDEO_OMAP3=y
|
||||
CONFIG_VIDEO=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,294 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
|
||||
*
|
||||
* Based on omap3_evm_config.h
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#include <asm/arch/omap.h>
|
||||
|
||||
/*
|
||||
* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
|
||||
* and older u-boot.bin with the new U-Boot SPL.
|
||||
*/
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 26000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK >> 1)
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
|
||||
/*
|
||||
* DDR related
|
||||
*/
|
||||
#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
|
||||
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
115200}
|
||||
|
||||
/* EHCI */
|
||||
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
|
||||
|
||||
/* commands to include */
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_RTC_DS1337
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
|
||||
/*
|
||||
* Board NAND Info.
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
|
||||
/* to access */
|
||||
/* nand at CS0 */
|
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
|
||||
/* NAND devices */
|
||||
#define CONFIG_JFFS2_NAND
|
||||
/* nand device jffs2 lives on */
|
||||
#define CONFIG_JFFS2_DEV "nand0"
|
||||
/* start of jffs2 partition */
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x680000
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
|
||||
|
||||
/* Environment information */
|
||||
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
|
||||
/* Setup MTD for NAND on the SOM */
|
||||
|
||||
#define CONFIG_HOSTNAME "mcx"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
|
||||
"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
|
||||
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
|
||||
"addfb=setenv bootargs ${bootargs} vram=6M " \
|
||||
"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
|
||||
"addip_sta=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
||||
"${netmask}:${hostname}:eth0:off\0" \
|
||||
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
|
||||
"addip=if test -n ${ipdyn};then run addip_dyn;" \
|
||||
"else run addip_sta;fi\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
|
||||
"addtty=setenv bootargs ${bootargs} " \
|
||||
"console=${consoledev},${baudrate}\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"baudrate=115200\0" \
|
||||
"consoledev=ttyO2\0" \
|
||||
"hostname=" CONFIG_HOSTNAME "\0" \
|
||||
"loadaddr=0x82000000\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"load_k=tftp ${loadaddr} ${bootfile}\0" \
|
||||
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
|
||||
"loadmlo=tftp ${loadaddr} ${mlo}\0" \
|
||||
"mlo=" CONFIG_HOSTNAME "/MLO\0" \
|
||||
"mmcargs=root=/dev/mmcblk0p2 rw " \
|
||||
"rootfstype=ext3 rootwait\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"run addip addtty addmtd addfb addeth addmisc;" \
|
||||
"run loaduimage; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"net_nfs=run load_k; " \
|
||||
"run nfsargs; " \
|
||||
"run addip addtty addmtd addfb addeth addmisc;" \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
|
||||
"uboot_addr=0x80000\0" \
|
||||
"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
|
||||
"nand write ${loadaddr} ${uboot_addr} 80000\0" \
|
||||
"updatemlo=nandecc hw;nand erase 0 20000;" \
|
||||
"nand write ${loadaddr} 0 20000\0" \
|
||||
"upd=if run load;then echo Updating u-boot;if run update;" \
|
||||
"then echo U-Boot updated;" \
|
||||
"else echo Error updating u-boot !;" \
|
||||
"echo Board without bootloader !!;" \
|
||||
"fi;" \
|
||||
"else echo U-Boot not downloaded..exiting;fi\0" \
|
||||
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"nandargs=setenv bootargs ubi.mtd=7 " \
|
||||
"root=ubi0:rootfs rootfstype=ubifs\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"ubi part nand0,4;" \
|
||||
"ubi readvol ${loadaddr} kernel;" \
|
||||
"run addtty addmtd addfb addeth addmisc;" \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"preboot=ubi part nand0,7;" \
|
||||
"ubi readvol ${loadaddr} splash;" \
|
||||
"bmp display ${loadaddr};" \
|
||||
"gpio set 55\0" \
|
||||
"swupdate_args=setenv bootargs root=/dev/ram " \
|
||||
"quiet loglevel=1 " \
|
||||
"consoleblank=0 ${swupdate_misc}\0" \
|
||||
"swupdate=echo Running Sw-Update...;" \
|
||||
"if printenv mtdparts;then echo Starting SwUpdate...; " \
|
||||
"else mtdparts default;fi; " \
|
||||
"ubi part nand0,5;" \
|
||||
"ubi readvol 0x82000000 kernel_recovery;" \
|
||||
"ubi part nand0,6;" \
|
||||
"ubi readvol 0x84000000 fs_recovery;" \
|
||||
"run swupdate_args; " \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"${mtdparts} " \
|
||||
"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
|
||||
"omapdss.def_disp=lcd;" \
|
||||
"bootm 0x82000000 0x84000000\0" \
|
||||
"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
|
||||
"then source 82000000;else run nandboot;fi\0"
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
|
||||
/* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
|
||||
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
|
||||
0x01F00000) /* 31MB */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
|
||||
/* address */
|
||||
#define CONFIG_PREBOOT
|
||||
|
||||
/*
|
||||
* AM3517 has 12 GP timers, they can be driven by the system clock
|
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
|
||||
* This rate is divided by a local divisor.
|
||||
*/
|
||||
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
|
||||
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
/* **** PISMO SUPPORT *** */
|
||||
|
||||
/* Redundant Environment */
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
||||
#define CONFIG_ENV_OFFSET 0x180000
|
||||
#define CONFIG_ENV_ADDR 0x180000
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
2 * CONFIG_SYS_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
/* Flash banks JFFS2 should use */
|
||||
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
|
||||
CONFIG_SYS_MAX_NAND_DEVICE)
|
||||
#define CONFIG_SYS_JFFS2_MEM_NAND
|
||||
/* use flash_info[2] */
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* Defines for SPL */
|
||||
|
||||
#define CONFIG_SPL_NAND_BASE
|
||||
#define CONFIG_SPL_NAND_DRIVERS
|
||||
#define CONFIG_SPL_NAND_ECC
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
|
||||
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
|
||||
|
||||
/* move malloc and bss high to prevent clashing with the main image */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
|
||||
/* NAND boot config */
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
|
||||
48, 49, 50, 51, 52, 53, 54, 55,\
|
||||
56, 57, 58, 59, 60, 61, 62, 63}
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
|
||||
#define CONFIG_SPL_NAND_SOFTECC
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
|
||||
/*
|
||||
* ethernet support
|
||||
*
|
||||
*/
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_NET_RETRY_COUNT 10
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue