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ARM: socfpga: stratix10: Disable FPGA2SOC reset
Software must never reset FPGA2SOC bridge. This bridge must only be reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software can cause the SoC to lock-up if there are traffics being drived into FPGA2SOC bridge. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
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parent
6bf238a461
commit
a03e9d9fe5
2 changed files with 6 additions and 3 deletions
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@ -48,6 +48,8 @@ struct socfpga_reset_manager {
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#define RSTMGR_MPUMODRST_CORE0 0
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#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
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#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
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#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
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/* Watchdogs and MPU warm reset mask */
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#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
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@ -61,7 +61,7 @@ void socfpga_bridges_reset(int enable)
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/* clear idle request to all bridges */
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setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
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/* Release bridges from reset state per handoff value */
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/* Release all bridges from reset state */
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clrbits_le32(&reset_manager_base->brgmodrst, ~0);
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/* Poll until all idleack to 0 */
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@ -84,9 +84,10 @@ void socfpga_bridges_reset(int enable)
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(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
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;
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/* Put all bridges (except NOR DDR scheduler) into reset */
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/* Reset all bridges (except NOR DDR scheduler & F2S) */
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setbits_le32(&reset_manager_base->brgmodrst,
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~RSTMGR_BRGMODRST_DDRSCH_MASK);
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~(RSTMGR_BRGMODRST_DDRSCH_MASK |
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RSTMGR_BRGMODRST_FPGA2SOC_MASK));
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/* Disable NOC timeout */
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writel(0, &system_manager_base->noc_timeout);
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