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tegra: sound: Add an I2S driver
Add a driver which supports transmitting digital sound to an audio codec. This uses fixed parameters as a device-tree binding is not currently defined. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass
Tom Warren
parent
112f2e1443
commit
c5a120b3f0
4 changed files with 359 additions and 1 deletions
206
arch/arm/include/asm/arch-tegra/tegra_i2s.h
Normal file
206
arch/arm/include/asm/arch-tegra/tegra_i2s.h
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@ -0,0 +1,206 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* tegra_i2s.h - Definitions for Tegra124 I2S driver.
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* Note, some structures (ex, CIF) are different in Tegra114.
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*
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* NVIDIA Tegra I2S controller
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* Modified from dc tegra_regs.h
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*
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* Copyright 2018 Google LLC
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*
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* Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _TEGRA_I2S_H_
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#define _TEGRA_I2S_H_
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struct i2s_ctlr {
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u32 ctrl; /* I2S_CTRL_0, 0x00 */
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u32 timing; /* I2S_TIMING_0, 0x04 */
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u32 offset; /* I2S_OFFSET_0, 0x08 */
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u32 ch_ctrl; /* I2S_CH_CTRL_0, 0x0C */
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u32 slot_ctrl; /* I2S_SLOT_CTRL_0, 0x10 */
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u32 cif_tx_ctrl; /* I2S_CIF_TX_CTRL_0, 0x14 */
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u32 cif_rx_ctrl; /* I2S_CIF_RX_CTRL_0, 0x18 */
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u32 flowctl; /* I2S_FLOWCTL_0, 0x1C */
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u32 tx_step; /* I2S_TX_STEP_0, 0x20 */
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u32 flow_status; /* I2S_FLOW_STATUS_0, 0x24 */
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u32 flow_total; /* I2S_FLOW_TOTAL_0, 0x28 */
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u32 flow_over; /* I2S_FLOW_OVER_0, 0x2C */
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u32 flow_under; /* I2S_FLOW_UNDER_0, 0x30 */
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u32 reserved[12]; /* RESERVED, 0x34 - 0x60 */
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u32 slot_ctrl2; /* I2S_SLOT_CTRL2_0, 0x64*/
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};
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enum {
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I2S_CTRL_XFER_EN_TX = 1 << 31,
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I2S_CTRL_XFER_EN_RX = 1 << 30,
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I2S_CTRL_CG_EN = 1 << 29,
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I2S_CTRL_SOFT_RESET = 1 << 28,
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I2S_CTRL_TX_FLOWCTL_EN = 1 << 27,
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I2S_CTRL_OBS_SEL_SHIFT = 24,
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I2S_CTRL_OBS_SEL_MASK = 7 << I2S_CTRL_OBS_SEL_SHIFT,
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I2S_FRAME_FORMAT_LRCK = 0,
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I2S_FRAME_FORMAT_FSYNC = 1,
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I2S_CTRL_FRAME_FORMAT_SHIFT = 12,
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I2S_CTRL_FRAME_FORMAT_MASK = 7 << I2S_CTRL_FRAME_FORMAT_SHIFT,
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I2S_CTRL_FRAME_FORMAT_LRCK = I2S_FRAME_FORMAT_LRCK <<
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I2S_CTRL_FRAME_FORMAT_SHIFT,
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I2S_CTRL_FRAME_FORMAT_FSYNC = I2S_FRAME_FORMAT_FSYNC <<
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I2S_CTRL_FRAME_FORMAT_SHIFT,
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I2S_CTRL_MASTER_ENABLE = 1 << 10,
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I2S_LRCK_LEFT_LOW = 0,
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I2S_LRCK_RIGHT_LOW = 1,
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I2S_CTRL_LRCK_SHIFT = 9,
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I2S_CTRL_LRCK_MASK = 1 << I2S_CTRL_LRCK_SHIFT,
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I2S_CTRL_LRCK_L_LOW = I2S_LRCK_LEFT_LOW << I2S_CTRL_LRCK_SHIFT,
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I2S_CTRL_LRCK_R_LOW = I2S_LRCK_RIGHT_LOW << I2S_CTRL_LRCK_SHIFT,
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I2S_CTRL_LPBK_ENABLE = 1 << 8,
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I2S_BIT_CODE_LINEAR = 0,
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I2S_BIT_CODE_ULAW = 1,
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I2S_BIT_CODE_ALAW = 2,
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I2S_CTRL_BIT_CODE_SHIFT = 4,
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I2S_CTRL_BIT_CODE_MASK = 3 << I2S_CTRL_BIT_CODE_SHIFT,
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I2S_CTRL_BIT_CODE_LINEAR = I2S_BIT_CODE_LINEAR <<
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I2S_CTRL_BIT_CODE_SHIFT,
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I2S_CTRL_BIT_CODE_ULAW = I2S_BIT_CODE_ULAW << I2S_CTRL_BIT_CODE_SHIFT,
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I2S_CTRL_BIT_CODE_ALAW = I2S_BIT_CODE_ALAW << I2S_CTRL_BIT_CODE_SHIFT,
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I2S_BITS_8 = 1,
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I2S_BITS_12 = 2,
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I2S_BITS_16 = 3,
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I2S_BITS_20 = 4,
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I2S_BITS_24 = 5,
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I2S_BITS_28 = 6,
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I2S_BITS_32 = 7,
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/* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
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I2S_CTRL_BIT_SIZE_SHIFT = 0,
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I2S_CTRL_BIT_SIZE_MASK = 7 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_8 = I2S_BITS_8 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_12 = I2S_BITS_12 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_16 = I2S_BITS_16 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_20 = I2S_BITS_20 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_24 = I2S_BITS_24 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_28 = I2S_BITS_28 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_32 = I2S_BITS_32 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_TIMING_NON_SYM_ENABLE = 1 << 12,
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I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT = 0,
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I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US = 0x7ff,
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I2S_TIMING_CHANNEL_BIT_COUNT_MASK =
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I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US <<
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I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT,
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I2S_OFFSET_RX_DATA_OFFSET_SHIFT = 16,
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I2S_OFFSET_RX_DATA_OFFSET_MASK_US = 0x7ff,
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I2S_OFFSET_RX_DATA_OFFSET_MASK = I2S_OFFSET_RX_DATA_OFFSET_MASK_US <<
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I2S_OFFSET_RX_DATA_OFFSET_SHIFT,
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I2S_OFFSET_TX_DATA_OFFSET_SHIFT = 0,
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I2S_OFFSET_TX_DATA_OFFSET_MASK_US = 0x7ff,
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I2S_OFFSET_TX_DATA_OFFSET_MASK = I2S_OFFSET_TX_DATA_OFFSET_MASK_US <<
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I2S_OFFSET_TX_DATA_OFFSET_SHIFT,
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/* FSYNC width - 1 in bit clocks */
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I2S_CH_CTRL_FSYNC_WIDTH_SHIFT = 24,
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I2S_CH_CTRL_FSYNC_WIDTH_MASK_US = 0xff,
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I2S_CH_CTRL_FSYNC_WIDTH_MASK = I2S_CH_CTRL_FSYNC_WIDTH_MASK_US <<
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I2S_CH_CTRL_FSYNC_WIDTH_SHIFT,
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I2S_HIGHZ_NO = 0,
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I2S_HIGHZ_YES = 1,
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I2S_HIGHZ_ON_HALF_BIT_CLK = 2,
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I2S_CH_CTRL_HIGHZ_CTRL_SHIFT = 12,
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I2S_CH_CTRL_HIGHZ_CTRL_MASK = 3 << I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
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I2S_CH_CTRL_HIGHZ_CTRL_NO = I2S_HIGHZ_NO <<
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I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
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I2S_CH_CTRL_HIGHZ_CTRL_YES = I2S_HIGHZ_YES <<
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I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
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I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK = I2S_HIGHZ_ON_HALF_BIT_CLK <<
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I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
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I2S_MSB_FIRST = 0,
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I2S_LSB_FIRST = 1,
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I2S_CH_CTRL_RX_BIT_ORDER_SHIFT = 10,
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I2S_CH_CTRL_RX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
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I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
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I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_TX_BIT_ORDER_SHIFT = 9,
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I2S_CH_CTRL_TX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
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I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
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I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
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I2S_POS_EDGE = 0,
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I2S_NEG_EDGE = 1,
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I2S_CH_CTRL_EGDE_CTRL_SHIFT = 8,
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I2S_CH_CTRL_EGDE_CTRL_MASK = 1 << I2S_CH_CTRL_EGDE_CTRL_SHIFT,
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I2S_CH_CTRL_EGDE_CTRL_POS_EDGE = I2S_POS_EDGE <<
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I2S_CH_CTRL_EGDE_CTRL_SHIFT,
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I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE = I2S_NEG_EDGE <<
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I2S_CH_CTRL_EGDE_CTRL_SHIFT,
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/* Sample size is # bits from BIT_SIZE minus this field */
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I2S_CH_CTRL_RX_MASK_BITS_SHIFT = 4,
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I2S_CH_CTRL_RX_MASK_BITS_MASK_US = 7,
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I2S_CH_CTRL_RX_MASK_BITS_MASK = I2S_CH_CTRL_RX_MASK_BITS_MASK_US <<
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I2S_CH_CTRL_RX_MASK_BITS_SHIFT,
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I2S_CH_CTRL_TX_MASK_BITS_SHIFT = 0,
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I2S_CH_CTRL_TX_MASK_BITS_MASK_US = 7,
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I2S_CH_CTRL_TX_MASK_BITS_MASK = I2S_CH_CTRL_TX_MASK_BITS_MASK_US <<
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I2S_CH_CTRL_TX_MASK_BITS_SHIFT,
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/* Number of slots in frame, minus 1 */
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I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT = 16,
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I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US = 7,
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I2S_SLOT_CTRL_TOTAL_SLOTS_MASK = I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US <<
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I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT,
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/* TDM mode slot enable bitmask */
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I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT = 8,
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I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK =
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0xff << I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT,
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I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT = 0,
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I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK = 0xff <<
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I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT,
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I2S_FILTER_LINEAR = 0,
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I2S_FILTER_QUAD = 1,
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I2S_FLOWCTL_FILTER_SHIFT = 31,
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I2S_FLOWCTL_FILTER_MASK = 1 << I2S_FLOWCTL_FILTER_SHIFT,
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I2S_FLOWCTL_FILTER_LINEAR = I2S_FILTER_LINEAR <<
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I2S_FLOWCTL_FILTER_SHIFT,
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I2S_FLOWCTL_FILTER_QUAD = I2S_FILTER_QUAD << I2S_FLOWCTL_FILTER_SHIFT,
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I2S_TX_STEP_SHIFT = 0,
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I2S_TX_STEP_MASK_US = 0xffff,
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I2S_TX_STEP_MASK = I2S_TX_STEP_MASK_US << I2S_TX_STEP_SHIFT,
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I2S_FLOW_STATUS_UNDERFLOW = 1 << 31,
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I2S_FLOW_STATUS_OVERFLOW = 1 << 30,
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I2S_FLOW_STATUS_MONITOR_INT_EN = 1 << 4,
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I2S_FLOW_STATUS_COUNTER_CLR = 1 << 3,
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I2S_FLOW_STATUS_MONITOR_CLR = 1 << 2,
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I2S_FLOW_STATUS_COUNTER_EN = 1 << 1,
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I2S_FLOW_STATUS_MONITOR_EN = 1 << 0,
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};
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#endif /* _TEGRA_I2C_H_ */
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@ -11,7 +11,7 @@ obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o
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obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o
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obj-$(CONFIG_I2S_ROCKCHIP) += rockchip_i2s.o rockchip_sound.o
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obj-$(CONFIG_I2S_SAMSUNG) += samsung_sound.o
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obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o
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obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o tegra_i2s.o
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obj-$(CONFIG_SOUND_WM8994) += wm8994.o
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obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o
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obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o
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123
drivers/sound/tegra_i2s.c
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123
drivers/sound/tegra_i2s.c
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#define LOG_CATEGORY UCLASS_I2S
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#define LOG_DEBUG
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#include <common.h>
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#include <dm.h>
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#include <i2s.h>
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#include <misc.h>
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#include <sound.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/tegra_i2s.h>
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#include "tegra_i2s_priv.h"
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int tegra_i2s_set_cif_tx_ctrl(struct udevice *dev, u32 value)
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{
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struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
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struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address;
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writel(value, ®s->cif_tx_ctrl);
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return 0;
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}
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static void tegra_i2s_transmit_enable(struct i2s_ctlr *regs, int on)
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{
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clrsetbits_le32(®s->ctrl, I2S_CTRL_XFER_EN_TX,
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on ? I2S_CTRL_XFER_EN_TX : 0);
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}
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static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx)
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{
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struct i2s_ctlr *regs = (struct i2s_ctlr *)pi2s_tx->base_address;
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u32 audio_bits = (pi2s_tx->bitspersample >> 2) - 1;
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u32 ctrl = readl(®s->ctrl);
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/* Set format to LRCK / Left Low */
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ctrl &= ~(I2S_CTRL_FRAME_FORMAT_MASK | I2S_CTRL_LRCK_MASK);
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ctrl |= I2S_CTRL_FRAME_FORMAT_LRCK;
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ctrl |= I2S_CTRL_LRCK_L_LOW;
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/* Disable all transmission until we are ready to transfer */
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ctrl &= ~(I2S_CTRL_XFER_EN_TX | I2S_CTRL_XFER_EN_RX);
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/* Serve as master */
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ctrl |= I2S_CTRL_MASTER_ENABLE;
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/* Configure audio bits size */
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ctrl &= ~I2S_CTRL_BIT_SIZE_MASK;
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ctrl |= audio_bits << I2S_CTRL_BIT_SIZE_SHIFT;
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writel(ctrl, ®s->ctrl);
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/* Timing in LRCK mode: */
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writel(pi2s_tx->bitspersample, ®s->timing);
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/* I2S mode has [TX/RX]_DATA_OFFSET both set to 1 */
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writel(((1 << I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
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(1 << I2S_OFFSET_TX_DATA_OFFSET_SHIFT)), ®s->offset);
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/* FSYNC_WIDTH = 2 clocks wide, TOTAL_SLOTS = 2 slots per fsync */
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writel((2 - 1) << I2S_CH_CTRL_FSYNC_WIDTH_SHIFT, ®s->ch_ctrl);
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return 0;
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}
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static int tegra_i2s_tx_data(struct udevice *dev, void *data, uint data_size)
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{
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struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
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struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address;
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int ret;
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tegra_i2s_transmit_enable(regs, 1);
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ret = misc_write(dev_get_parent(dev), 0, data, data_size);
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tegra_i2s_transmit_enable(regs, 0);
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if (ret < 0)
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return ret;
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else if (ret < data_size)
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return -EIO;
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return 0;
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}
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static int tegra_i2s_probe(struct udevice *dev)
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{
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struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
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ulong base;
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base = dev_read_addr(dev);
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if (base == FDT_ADDR_T_NONE) {
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debug("%s: Missing i2s base\n", __func__);
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return -EINVAL;
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}
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priv->base_address = base;
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priv->id = 1;
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priv->audio_pll_clk = 4800000;
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priv->samplingrate = 48000;
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priv->bitspersample = 16;
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priv->channels = 2;
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priv->rfs = 256;
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priv->bfs = 32;
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return i2s_tx_init(priv);
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}
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static const struct i2s_ops tegra_i2s_ops = {
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.tx_data = tegra_i2s_tx_data,
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};
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static const struct udevice_id tegra_i2s_ids[] = {
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{ .compatible = "nvidia,tegra124-i2s" },
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{ }
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};
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U_BOOT_DRIVER(tegra_i2s) = {
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.name = "tegra_i2s",
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.id = UCLASS_I2S,
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.of_match = tegra_i2s_ids,
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.probe = tegra_i2s_probe,
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.ops = &tegra_i2s_ops,
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};
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29
drivers/sound/tegra_i2s_priv.h
Normal file
29
drivers/sound/tegra_i2s_priv.h
Normal file
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@ -0,0 +1,29 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#ifndef __TEGRA_I2S_PRIV_H
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#define __TEGRA_I2S_PRIV_H
|
||||
|
||||
enum {
|
||||
/* Set i2s device (in buf) */
|
||||
AHUB_MISCOP_SET_I2S,
|
||||
};
|
||||
|
||||
/*
|
||||
* tegra_i2s_set_cif_tx_ctrl() - Set the I2C port to send to
|
||||
*
|
||||
* The CIF is not really part of I2S -- it's for Audio Hub to control
|
||||
* the interface between I2S and Audio Hub. However since it's put in
|
||||
* the I2S registers domain instead of the Audio Hub, we need to export
|
||||
* this as a function.
|
||||
*
|
||||
* @dev: I2S device
|
||||
* @value: Value to write to CIF_TX_CTRL register
|
||||
* @return 0
|
||||
*/
|
||||
int tegra_i2s_set_cif_tx_ctrl(struct udevice *dev, u32 value);
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue