Commit graph

15731 commits

Author SHA1 Message Date
Aditya Prayoga
5ca84c6dd2 arm: mvebu: helios4: Reset uSOM onboard phy during board init
Similar to Clearfog rev 2.1, GPIO 19 also used to reset onboard ethernet
PHY.

This patch depend on
net: mvneta: Add GPIO configuration support
[URL: https://patchwork.ozlabs.org/patch/1007736/]

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-12-08 16:19:41 +01:00
Aditya Prayoga
8d7d97e2d1 arm: mvebu: helios4: Enable SPI flash support
Enable SPI flash support under U-Boot and SPL. The ENV size and offset,
ported from U-Boot 2013.01 Marvell version: 2015_T1.0p16

To create U-Boot image for SPI flash, user would need to replace
* CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC with CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
* CONFIG_ENV_IS_IN_MMC with CONFIG_ENV_IS_IN_SPI_FLASH

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-12-08 16:19:41 +01:00
Aditya Prayoga
c209a65e9e arm: mvebu: helios4: Enable I2C and IO Expander
Enable Marvell I2C driver and I2C IO expander. Set default bus to
external I2C bus. Define I2C aliases in device tree so it can be
recognized by the driver.

Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-12-08 16:19:41 +01:00
Tom Rini
c49aff3e66 Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Various axp209 fixes
- Fixes for OLinuXino-A20-Lime2 / OLinuXino-A20-Lime2-eMMC
2018-12-07 19:02:01 -05:00
Olliver Schinagl
c970e8954f sunxi: pmic_bus: Decrease boot time by not writing duplicate data
When we clear a pmic_bus bit, we do a read-modify-write operation.
We waste some time however, by writing back the exact samea value
that was already set in the chip. Let us thus only do the write
in case data was changed.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-07 22:24:33 +05:30
Simon Goldschmidt
a9024dc18e arm: socfpga: imply SPL options instead of select
For a small SPL, it should be possible to build without SPI(-flash) drivers
or wihout MMC drivers.

For this to work, we have to change from 'select'ing options to 'imply'ing
them.

With this change, I can have SPL trimmed to my hard-wired starting method
(SPI-NOR or MMC) while still including all drivers in U-Boot.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-12-07 16:32:01 +01:00
Jean-Jacques Hiblot
d0af9eb501 dts: dra7x: make ocp2scp@4a080000 compatible with simple-bus
This is required when DM_USB is used, to bind the USB phys.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07 16:31:46 +01:00
Jean-Jacques Hiblot
6c3af1f24e syscon: dm: Add a new method to get a regmap from DTS
syscon_regmap_lookup_by_phandle() can be used to get the regmap of a syscon
device from a reference in the DTS. It operates similarly to the linux
version of the namesake function.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-07 16:31:45 +01:00
Jean-Jacques Hiblot
687ab54560 usb: introduce a separate config option for DM USB device
Using CONFIG_DM_USB for this purpose prevents using DM_USB for host and not
for device.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2018-12-07 16:31:45 +01:00
Takeshi Kihara
5055a4e900 ARM: rmobile: Fix to enable icache early in Gen3
This patch fixes the problem that u-boot will not start unless icache is
enabled early.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07 16:31:15 +01:00
Takeshi Kihara
10854bcc25 ARM: rcar_gen3: fix protection area access error
This patch fixes the problem that "main memory domain AXI secure access
protection error" occurs. Exclude the area (0x43f00000 to 0x47DFFFFF)
set by DBSC from the map area.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07 16:31:15 +01:00
Hiroyuki Yokoyama
23b9b36ae3 ARM: rcar_gen3: fix protection area access error at Cortex-A53
This patch fixes the problem that "main memory domain AXI secure
access protection error" occurs when booting Cortex-A53. Exclude
the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07 16:31:15 +01:00
Felix Brack
fdce9d35dc arm: dts: am33xx: Sync dts with Linux 4.20.0
This patch synchronizes the am33xx SoC specific files with those from
Linux 4.20.0. Hence all board maintainers of am33xx based boards are
on the cc list.
The main purpose of this patch is to prevent further diverging of the
dts files from U-Boot and those from Linux. It aims to set the stage
for the synchronization of board specific dts files. Example: I'm the
maintainer of the PDU001 board: once this patch is applied successfully
I will make changes to the board specific dts file in Linux only and
then post a patch with a copy of this exact dts file to U-Boot. This
will make U-Boot and Linux remain in sync.
The stumbling block of https://patchwork.ozlabs.org/patch/943627 was
removed by the patch https://patchwork.ozlabs.org/patch/962428 from
Lokesh Vutla (many thanks!). This omap-serial driver allows using the
Linux am33xx.dtsi file in U-Boot.
Other changes to dts and dtsi files made by this patch are mainly to
prevent _new_ warnings during the build process. Especially the warning
at pinmux@800 stating 'unnecessary #address-cells/#size-cells without
"ranges" or child "reg"' was not removed. This warning is a good example
showing the benefit of the synchronization: if it needs to be fixed it
will be fixed in Linux and ported back to U-Boot.
Buildman reports all 46 am33xx SoC based boards to build fine, with
warnings of course. Nevertheless this patch should be tested thoroughly
on as many boards as possible to prevent any collateral damage.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07 08:13:51 -05:00
Adam Ford
8a15bdb040 ARM: DTS: da850-evm: Re-sync da850-evm.dts from Linux 4.20
There has been some natural evolution of the device tree, so
resync with 4.20

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:50 -05:00
Adam Ford
ae67a9b330 ARM: dts: da850-lcdk: Sync from Linux 4.20
Re-synce the device tree files from Linux 4.20

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:50 -05:00
Adam Ford
031288abe9 ARM: DTS: da850: Sync from Linux 4.20
Re-sync with 4.20 due some some natural evolution.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:50 -05:00
Adam Ford
343b606261 ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit with Linux 4.20
Migrate some small device tree fixes from Linux 4.20.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:50 -05:00
Adam Ford
faef5b376e ARM: DTS: Resync LogicPD SOM-LV with Linux 4.20
There have been a few fixes to the device trees, so this
re-syncs the dts/dtsi files with Linux

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:49 -05:00
Adam Ford
5792f0d8be ARM: DTS: Resync am3517-evm.dts with Linux 4.20
The DTS file for the AM3517 had the incorrect CD polarity.  Resync with
the fixed DTS file from Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-12-07 08:13:48 -05:00
Patrice Chotard
b2f84e37e2 gpio: stm32f7: Move STM32_GPIOS_PER_BANK into gpio.h
To allow access to this define by other driver, move
it into gpio.h

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Patrice Chotard
dbf928dd26 gpio: stm32f7: Add gpio bank holes management
In some STM32 SoC packages, GPIO bank has not always 16 gpios.
Several cases can occur, gpio hole can be located at the beginning,
middle or end of the gpio bank or a combination of these 3
configurations.

For that, gpio bindings offer the gpio-ranges DT property which
described the gpio bank mapping.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Álvaro Fernández Rojas
e9e8d80d8c serial: bcm6858: remove driver and switch to bcm6345
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-07 08:13:46 -05:00
Álvaro Fernández Rojas
47b1cbaf02 arm: implement {in, out}_{16, 32} and {clr, set, clrset}bits_{16, 32}
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-07 08:13:46 -05:00
Felix Brack
2aadff0feb arm: am335x-pdu001: Enable CONFIG_BLK and CONFIG_DM_MMC
This patch enables CONFIG_BLK as well as CONFIG_DM_MMC for the PDU001
board. It depends on Patrice Chotard's patch 'power: regulator: denied
disable on always-on regulator' which prevents power cycling the vmmc
supply. Without this patch the board will not boot as vmmc is
unfortunately used by other board components, not just eMMC and micro SD
card. Furthermore my patch 'dts: am335x-pdu001: Fix polarity of card
detection input' is required to boot from external micro SD card. Without
this patch no SD card will be detected and hence booting will fail.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07 08:13:46 -05:00
Felix Brack
ae0a157b38 dts: am335x-pdu001: Fix polarity of card detection input
When a micro SD card is inserted in the PDU001 card cage, the card
detection switch is opened and the corresponding GPIO input is driven
by a pull-up. Hence change the active level of the card detection
input from low to high.

Signed-off-by: Felix Brack <fb@ltec.ch>
2018-12-07 08:13:45 -05:00
Grygorii Strashko
b330991874 test: dma: add dma-uclass test
Add a sandbox DMA driver implementation (provider) and corresponding DM
test.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-07 08:13:45 -05:00
Eugen.Hristev@microchip.com
bbaeb7ac22 ARM: at91: lds: add test for SPL binary size and bss size
Add test for the SPL binary size and the bss section size.
This will throw an error at build time if the SPL sections
do not fit in the designated RAM area, thus avoiding oversizing the SPL.

Based on original work by Wenyou Yang.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-12-07 08:13:44 -05:00
Benjamin Gaignard
075b0185b6 pinctrl: stm32: make pinctrl use hwspinlock
Protect configuration registers with a hardware spinlock.

If a hwspinlock is defined in the device-tree node used it
to be sure that none of the others processors on the SoC could
change the configuration at the same time.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06 23:26:33 -05:00
Benjamin Gaignard
9119f547d3 hwspinlock: add stm32 hardware spinlock support
Implement hardware spinlock support for STM32MP1.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06 23:26:33 -05:00
Benjamin Gaignard
7f84fc670b dm: Add Hardware Spinlock class
This is uclass for Hardware Spinlocks.
It implements two mandatory operations: lock and unlock
and one optional relax operation.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-06 23:26:32 -05:00
Priyanka Jain
4909b89ec7 armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Priyanka Jain
d6fdec211f armv8:fsl-layerscape: Add support for Chassis 3.2
NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.

Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Priyanka Jain
6252faa0da armv8: lsch3: Add support of serdes3 module
Some lsch3 based SoCs like lx2160a contains three
serdes modules.
Add support for third serdes protocol in lsch3

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Peng Ma
8ec42856f1 armv8: dts: fsl-ls2080a: add sata node support
One ls2080a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Peng Ma
3e586ee307 armv8: dts: fsl-ls1088a: add sata node support
One ls1088a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Peng Ma
539e0cb6dc armv8: dts: fsl-ls1046a: add sata node support
One ls1046a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
ade32bb473 armv8: fsl-layerscape: add support of MC framework for TFA
Add support of MC framework for TFA
Make MC framework independent of boot source.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
2e17cb8a42 armv8: sec_firmware: return job ring status as true in TFABOOT
Returns job ring status as true in TFABOOT, as one job ring is always
reserved.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
339fb297d4 armv8: sec_firmware: change el2_to_aarch32 SMC ID
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17,
it is applicable to both TFA and non-TFA boot.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
York Sun
56db948b85 armv8: fsl-layerscape: Update parsing boot source
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
5a73ec6169 armv8: layerscape: skip OCRAM init for TFABOOT
OCRAM initialization is performed by TFA, Hence
skipped from u-boot.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
681d489e62 armv8: layerscape: add SMC calls for DDR size and bank info
Adds SMC calls for getting DDR size and bank info for TFABOOT.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
2141d250f5 armv8: fsl-layerscape: bootcmd identification for TFABOOT
Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
[YS: remove unnecessary braces]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:36 -08:00
Rajesh Bhagat
b6c97f4d94 armv8: layerscape: remove EL3 specific erratas for TFABOOT
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.

ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511,
SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663,
SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942,
SYS_FSL_ERRATUM_A010165

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
4c41738462 armv8: fsl-layerscape: identify boot source from PORSR register
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.

Further, it can be used to select the environment location.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix multiple checkpatch issues]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:26 -08:00
Rajesh Bhagat
535d76a121 armv8: layerscape: Add TFABOOT support
Adds TFABOOT support config option and add generic code to enable
execution from DDR.

Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-12-06 14:37:19 -08:00
Pankit Garg
e350648046 armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3
Change tlb base address from OCRAM to DDR when exception level is
less than 3.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
York Sun
bb50569dc4 armv8: layerscape: Enable routing SError exception
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to
EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes
the exception to EL2. Otherwise this exception is not taken.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Manivannan Sadhasivam
467877341a rockchip: rk3399: Add Ficus EE board support
Add board support for Ficus EE board from Vamrs. This board utilizes
common Rock960 family support.

Following peripherals are tested and known to work:
* Gigabit Ethernet
* USB 2.0
* MMC

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
[Reworked based on common Rock960 family support]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-06 16:04:49 +01:00
Manivannan Sadhasivam
07f7687869 rockchip: rk3399: Add Rock960 CE board support
Add board support for Rock960 CE board from Vamrs. This board utilizes
common Rock960 family support.

Following peripherals are tested and known to work:
* USB 2.0
* MMC

This commit also adds DDR configuration for LPDDR3-2GiB-1600MHz which
is being used on the board.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-06 16:04:49 +01:00
Manivannan Sadhasivam
1bad5e1492 rockchip: rk3399: Add common Rock960 family from Vamrs
Rock960 is a family of boards based on Rockchip RK3399 SoC from Vamrs.
It consists of Rock960 (Consumer Edition) and Ficus (Enterprise Edition)
96Boards.

Below are some of the key differences between both Rock960 and Ficus
boards:

1. Different host enable GPIO for USB
2. Different power and reset GPIO for PCI-E
3. No Ethernet port on Rock960

The common board support will be utilized by both boards. The device
tree has been organized in such a way that only the properties which
differ between both boards are placed in the board specific dts and
the reset of the nodes are placed in common dtsi file.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[Added instructions for SD card boot]
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2018-12-06 16:04:49 +01:00
Randy Li
2c9050cd3d arm: dts: rockchip: add some common pin-settings to rk3399
Those pins would be used by many boards.

Commit grabbed from Linux:

commit b41023282d07b61a53e2c9b9508912b1e7ce7b4f
Author: Randy Li <ayaka@soulik.info>
Date:   Thu Jun 21 21:32:10 2018 +0800

    arm64: dts: rockchip: add some common pin-settings to rk3399

    Those pins would be used by many boards.

    Signed-off-by: Randy Li <ayaka@soulik.info>
    Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-06 16:04:49 +01:00
Tom Rini
2a055ea532 Minor sandbox enhancements / fixes
tpm improvements to clear up v1/v2 support
 buildman toolchain fixes
 New serial options to set/get config
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Merge tag 'dm-pull-5dec18' of git://git.denx.de/u-boot-dm

Minor sandbox enhancements  / fixes
tpm improvements to clear up v1/v2 support
buildman toolchain fixes
New serial options to set/get config
2018-12-05 20:32:25 -05:00
Tom Rini
9450ab2ba8 Merge branch 'master' of git://git.denx.de/u-boot-spi
- Various MTD fixes from Boris
- Zap various unused / legacy paths.
- pxa3xx NAND update from Miquel

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-05 15:06:24 -05:00
Andy Shevchenko
b288cd9600 x86: acpi: Generate SPCR table
Microsoft specifies a SPCR (Serial Port Console Redirection Table) [1].
Let's provide it in U-Boot.

[1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-05 07:23:16 -07:00
Andy Shevchenko
f3275aa4a1 x86: acpi: Add SPCR table description
Add SPCR table description as it provided in Linux kernel.

Port subtype for ACPI_DBG2_SERIAL_PORT is used as an interface type in SPCR.
Thus, provide a set of definitions to be utilized later.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-05 07:23:16 -07:00
Álvaro Fernández Rojas
7959882049 dm: core: add functions to get/remap I/O addresses by name
This functions allow us to get and remap I/O addresses by name, which is useful when there are multiple reg addresses indexed by reg-names property.
This is needed in bmips dma/eth patch series, but can also be used on many
other drivers.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-05 06:06:44 -07:00
Simon Glass
40e9ede1dc sandbox: Use 'extras' to specify 'head' files
At present sandbox has a start.o in the 'start' target but also includes
it in the normal target list. This is not how this is normally handled. It
is needed because sandbox does not include the u-boot-init variable in its
link rule.

Update the rule and move start.o from the normal target list to the
'extras' list.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-05 06:01:34 -07:00
Simon Glass
a65d1a06c9 sandbox: Zero the ram buffer on startup
At present the RAM buffer is not inited unless it is read from a file,
likely produced by an earlier phase of U-Boot. This causes valgrind
warnings whenever the RAM buffer is used. Correct this by initing it if
needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-05 06:01:34 -07:00
Simon Glass
12efc933b9 sandbox: Check the filename in jump_to_image_no_args()
If the filename is NULL this function currently crashes. Update it to fail
gracefully.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-05 06:01:34 -07:00
Simon Glass
6b5e420137 sandbox: Fix up the debug message for the image filename
This currently prints out the wrong filename. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-05 06:01:34 -07:00
Rick Chen
48cbf62460 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
ax25-ae350 use CONFIG_OF_BOARD via a2 and CONFIG_SYS_SDRAM_BASE
to boot from ram which allow the board to override the fdt
address originally.

But after this patch
riscv: save hart ID and device tree passed by prior boot stage
It provide prior_stage_fdt_address which offer a temporary
memory address to keep the dtb address passing from loader(gdb)
to u-boot with a1.

So passing via a2 and CONFIG_SYS_SDRAM_BASE is redundant and
can be removed. And it also somehow may corrupted BBL if it
was be arranged in CONFIG_SYS_SDRAM_BASE.

In board_fdt_blob_setup()
When boting from ram:
prior_stage_fdt_address will be use to reserved dtb temporarily.

When booting from ROM:
dtb will be pre-burned in CONFIG_SYS_FDT_BASE, if it is flash base.
Or CONFIG_SYS_FDT_BASE maybe a memory map space (NOT RAM or ROM)
which is provided by HW.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2018-12-05 14:14:16 +08:00
Anup Patel
d2db2a8fa4 riscv: Add kconfig option to run U-Boot in S-mode
This patch adds kconfig option RISCV_SMODE to run U-Boot in
S-mode. When this opition is enabled we use s<xyz> CSRs instead
of m<xyz> CSRs.

It is important to note that there is no equivalent S-mode CSR
for misa and mhartid CSRs so we expect M-mode runtime firmware
(BBL or equivalent) to emulate misa and mhartid CSR read.

In-future, we will have more patches to avoid accessing misa and
mhartid CSRs from S-mode.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-05 14:13:53 +08:00
York Sun
d171c70716 move data structure out of cpu.h
Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-04 08:30:23 -08:00
Marek Vasut
00e4b57e9e ARM: rmobile: Set environment variable containing CPU type
Set environment variable 'platform' containing the CPU type.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-04 09:21:07 +01:00
Marek Vasut
66582cf6da ARM: rmobile: Enable MMC extensions
Enable extended MMC commands and GPT partition table support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
cbff9f80ce ARM: dts: rmobile: Sync Gen3 DTs with Linux 4.19.6
Synchronize DTs with mainline Linux 4.19.6 ,
commit 96db90800c06d3fe3fa08eb6222fe201286bb778

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
3b255531b6 ARM: dts: rmobile: Sync Gen2 DTs with Linux 4.19.6
Synchronize DTs with mainline Linux 4.19.6 ,
commit 96db90800c06d3fe3fa08eb6222fe201286bb778

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
4e96b693ee ARM: dts: rmobile: Extract i2c6 on M2W Porter
The i2c6 node is missing in mainline Linux thus far, pull it
into U-Boot specific DT until it hits mainline Linux, to make
syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
47179e5737 ARM: dts: rmobile: Extract SCIF2 node on E3 Ebisu
The SCIF2 node is not in Linux 4.17 DTs on E3, pull it into U-Boot
specific DT extras until it hits mainline Linux, to make syncing of
DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
6bdb7a80cb ARM: dts: rmobile: Extract SDHI nodes on E3 Ebisu
The SDHI nodes are not in Linux 4.17 DTs in E3, pull them into U-Boot
specific DT extras until they hit mainline Linux, to make syncing of
DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
1bce3ec801 ARM: dts: rmobile: Extract SDHI extras on H3, M3W, M3N Salvator-X
The SDHI nodes are missing features supported in upstream U-Boot,
like mode support properties. Pull the extras into U-Boot specific
DT until it hits mainline Linux, to make syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
750a147b3c ARM: dts: rmobile: Extract SDHI extras on H3 and M3W ULCB
The SDHI nodes are missing features supported in upstream U-Boot,
like mode support properties. Pull the extras into U-Boot specific
DT until it hits mainline Linux, to make syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
d2038b26e7 ARM: dts: rmobile: Extract CPLD node on H3 and M3W ULCB
The CPLD node is missing in Linux 4.17 DTs on H3/M3W ULCB, pull the
node into U-Boot specific DT until it hits mainline Linux, to make
syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
1172ade967 ARM: dts: rmobile: Extract AVB node extras on V3M Eagle
The AVB node is not complete in Linux 4.17 DTs on V3M Eagle, pull the
AVB node extras into U-Boot specific DT until they hit mainline Linux,
to make syncing of DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
830b94f768 ARM: dts: rmobile: Extract SDHI nodes on M3N
The SDHI nodes are not in Linux 4.17 DTs in M3N, pull them into U-Boot
specific DT extras until they hit mainline Linux, to make syncing of
DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
f529bc551b ARM: dts: rmobile: Extract USB nodes on M3N
The USB nodes are not in Linux 4.17 DTs in M3N, pull them into U-Boot
specific DT extras until they hit mainline Linux, to make syncing of
DTs easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
8c7d9e1f62 ARM: dts: rmobile: Extract RPC node to u-boot specific DT
The RPC DT bindings are still work in progress. Extract the RPC DT node
from the DT to allow easier update and so it can be replaced once the DT
bindings are stable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Marek Vasut
a89929bbb3 ARM: dts: rmobile: Add soc label to Gen3
Add label to the /soc node, so it can be referenced from the U-Boot DTs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
V2: Rebase on u-boot/master
2018-12-04 09:21:07 +01:00
Tom Rini
0a3d59e010 Xilinx changes for v2019.01
microblaze:
 - Use default functions for memory decoding
 - Showing model from DT
 
 zynq:
 - Fix spi flash DTs
 - Fix zynq_help_text with CONFIG_SYS_LONGHELP
 - Tune cse/mini configurations
 - Enabling cse/mini testing with current targets
 
 zynqmp:
 - Enable gzip SPL support
 - Fix chip detection logic
 - Tune mini configurations
 - DT fixes(spi-flash, models, clocks, etc)
 - Add support for OF_SEPARATE configurations
 - Enabling mini testing with current targets
 - Add mini mtest configuration
 - Some minor config setting
 
 nand:
 - arasan: Add subpage configuration
 
 net:
 - gem: Add 64bit DMA support
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Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.01

microblaze:
- Use default functions for memory decoding
- Showing model from DT

zynq:
- Fix spi flash DTs
- Fix zynq_help_text with CONFIG_SYS_LONGHELP
- Tune cse/mini configurations
- Enabling cse/mini testing with current targets

zynqmp:
- Enable gzip SPL support
- Fix chip detection logic
- Tune mini configurations
- DT fixes(spi-flash, models, clocks, etc)
- Add support for OF_SEPARATE configurations
- Enabling mini testing with current targets
- Add mini mtest configuration
- Some minor config setting

nand:
- arasan: Add subpage configuration

net:
- gem: Add 64bit DMA support
2018-12-03 19:30:54 -05:00
Tom Rini
f388e3bed7 Patch queue for efi - 2018-12-03
This release is fully packed with lots of glorious improvements in UEFI
 land again!
 
   - Make PE images more standards compliant
   - Improve sandbox support
   - Improve correctness
   - Fix RISC-V execution on virt model
   - Honor board defined top of ram (fixes a few boards)
   - Imply DM USB access when distro boot is available
   - Code cleanups
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-12-03

This release is fully packed with lots of glorious improvements in UEFI
land again!

  - Make PE images more standards compliant
  - Improve sandbox support
  - Improve correctness
  - Fix RISC-V execution on virt model
  - Honor board defined top of ram (fixes a few boards)
  - Imply DM USB access when distro boot is available
  - Code cleanups
2018-12-03 17:52:40 -05:00
Tom Rini
ec0d0d8742 Merge branch 'master' of git://git.denx.de/u-boot-sh
- MMC fixes for R-Car Gen3
2018-12-03 17:51:45 -05:00
Christophe Leroy
a8b8645fa9 board: MCR3000: migrate to DM_SERIAL
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-12-03 10:44:10 -05:00
Christophe Leroy
4c4ca6cdd5 board: MCR3000: use new DM watchdog
This patch switches MCR3000 board to the new DM watchdog.

The change in u-boot.lds is because MCR3000.o grows a bit
with this patch and doesn't fit anymore below env_offset on
some versions of GCC.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-12-03 10:44:10 -05:00
Christophe Leroy
f55db0afa2 board: MCR3000: Activate CONFIG_DM and CONFIG_OF_CONTROL
Add mcr3000 device tree and activate CONFIG_DM and CONFIG_OF_CONTROL

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-12-03 10:44:10 -05:00
Christophe Leroy
71c743c5f7 powerpc, mpc8xx: clear top of stack
Reported-by: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
2018-12-03 10:44:10 -05:00
Yegor Yefremov
67c145a836 arm: baltos: move the board to CONFIG_BLK
Use DM for both MMC and USB subsystems and use dedicated DTS
for U-Boot configuration.

Disable SPL support for GPIO and remove EVMSK leftover for
DDR power control via GPIO.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-03 10:44:10 -05:00
Tom Rini
8f5bfb7615 ARM: meson: Add regmap support for clock driver and sync DT with 4.19
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Merge tag 'u-boot-amlogic-20181203' of git://git.denx.de/u-boot-amlogic

ARM: meson: Add regmap support for clock driver and sync DT with 4.19
2018-12-03 09:21:06 -05:00
Loic Devulder
8973d81658 ARM: meson: Add regmap support for clock driver
This patch modifies the meson clock driver to use syscon/regmap like
the Linux kernel does, as it is needed if we want to share the same
DTS files.

DTS files are synchronized from Linux 4.19.

Signed-off-by: Loic Devulder <ldevulder@suse.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2018-12-03 13:34:21 +01:00
Marek Vasut
0be621aebd ARM: dts: rmobile: Enable HS400 on Salvator-X, ULCB, Ebisu
Enable the HS400 support in DT on H3, M3W, M3N Salvator-X(S)
and ULCB boards as well as E3 Ebisu board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03 12:51:17 +01:00
Marek Vasut
d0e0bbe7d1 ARM: dts: rmobile: Enable SDR modes on E3 Ebisu
Add regulators and pinmuxes for SDHI0 and SDHI1 SD and microSD
slots on E3 Ebisu and mark them as capable of up to SDR104 mode
of operation. With the SDHI fixes in place, it is now possible
to use SDR104.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03 12:51:17 +01:00
Marek Vasut
286ded3394 ARM: dts: rmobile: Enable SDR104 on Salvator-X and ULCB
Enable SDR104 modes on M3W and H3 boards. With the SDHI fixes
in place, it is now possible to use SDR104.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03 12:51:17 +01:00
Marek Vasut
ca3163ddb7 ARM: dts: rmobile: Add eMMC DS pinmux
Add pinmux entry for the eMMC DS line, as it is connected on these boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03 12:51:17 +01:00
Alexey Brodkin
85e529fdfc ARC: Improve identification of ARC cores
1. Try to guess a ARC core template that was used
   i.e. not just name a core family but something more
   menaingful like "ARC HS38", "ARC EM11D" etc.

   We do it checking availability of the key differentiation
   features like:
    - Caches (we actually only check for L1 I$ fpr simplicity)
    - XY-memory
    - DSP extensions etc.

2. Identify ARC subsystems

3. Print core clock frequency

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-12-03 14:26:18 +03:00
Heinrich Schuchardt
81ea00838c efi_loader: PSCI reset and shutdown
When an operating system started via bootefi tries to reset or power off
this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system
the actual reset relies on PSCI. Depending on whether the PSCI firmware
resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC
or an SMC command has to be issued.

The current implementation always uses SMC. This results in crashes on
systems where the PSCI firmware is implemented in the hypervisor, e.g.
qemu-arm64_defconfig.

The logic to decide which call is needed based on the device tree is
already implemented in the PSCI firmware driver. During the EFI runtime
the device driver model is not available. But we can minimize code
duplication by merging the EFI runtime reset and poweroff code with
the PSCI firmware driver.

As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff
and reset_misc routines let's move them into the same code module.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02 21:59:37 +01:00
Bin Meng
a33a4efd27 riscv: efi: Generate Microsoft PE format compliant images
Per Microsoft PE Format documentation [1], PointerToSymbolTable and
NumberOfSymbols should be zero for an image in the COFF file header.
Currently the COFF file header is hardcoded on RISC-V and these two
members are not zero.

This updates the hardcoded structure to clear these two members, as
well as setting the flag IMAGE_FILE_LOCAL_SYMS_STRIPPED so that we
can generate compliant *.efi images.

[1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02 21:59:36 +01:00
Bin Meng
fb8ebf52a4 arm: efi: Generate Microsoft PE format compliant images
Per Microsoft PE Format documentation [1], PointerToSymbolTable and
NumberOfSymbols should be zero for an image in the COFF file header.
Currently the COFF file header is hardcoded on ARM and these two
members are not zero.

This updates the hardcoded structure to clear these two members, as
well as setting the flag IMAGE_FILE_LOCAL_SYMS_STRIPPED so that we
can generate compliant *.efi images.

[1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02 21:59:36 +01:00
Bin Meng
c54ed3ef5e x86: efi: app: Generate Microsoft PE format compliant image
Per Microsoft PE Format documentation [1], PointerToSymbolTable and
NumberOfSymbols should be zero for an image in the COFF file header.
Currently U-Boot is generating u-boot-app.efi in which these two
members are not zero.

This updates the build rules to tell linker to remove the symbol
table completely so that we can generate compliant *.efi images.

[1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02 21:59:36 +01:00
Bin Meng
972ffcd7b0 x86: efi: payload: Generate Microsoft PE format compliant image
Per Microsoft PE Format documentation [1], PointerToSymbolTable and
NumberOfSymbols should be zero for an image in the COFF file header.
Currently U-Boot is generating u-boot-payload.efi image in which
these two members are not zero.

This updates the build rules to tell linker to remove the symbol
table completely so that we can generate compliant *.efi images.

[1] https://docs.microsoft.com/zh-cn/windows/desktop/Debug/pe-format

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-12-02 21:59:36 +01:00
Tom Rini
c1d6e0bbfd Improvements:
- RK3188 USB-UART functionality
 - errors triggering a hard-stop in SPL on the RK3399 are reported
 - Rockchip RV1108 (SoC) support
 - MicroCrystal RV3029 (RTC) DM driver
 
 Fixes:
 - RK3188 early UART setup
 - limit SD-card frequency to 40MHz on the RK3399-Q7
 - MIPI fixes
 - RK3399 CPUB clock initialisation
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Merge tag 'for-master-20181130' of git://git.denx.de/u-boot-rockchip

Improvements:
- RK3188 USB-UART functionality
- errors triggering a hard-stop in SPL on the RK3399 are reported
- Rockchip RV1108 (SoC) support
- MicroCrystal RV3029 (RTC) DM driver

Fixes:
- RK3188 early UART setup
- limit SD-card frequency to 40MHz on the RK3399-Q7
- MIPI fixes
- RK3399 CPUB clock initialisation
2018-12-01 14:17:27 -05:00
Tom Rini
172e3c1190 Fix sound on sandbox
Convert TPM fully to DM
 Tidy up sandbox I2C emulation
 Add a 'make qcheck' target for faster testing
 A few other misc things
 (dropped the final patch which breaks clang for some reason)
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Merge tag 'pull-30nov18' of git://git.denx.de/u-boot-dm

Fix sound on sandbox
Convert TPM fully to DM
Tidy up sandbox I2C emulation
Add a 'make qcheck' target for faster testing
A few other misc things
(dropped the final patch which breaks clang for some reason)
2018-11-30 17:09:50 -05:00
Tom Rini
daec1fd482 - MIPS: MT76xx: minor fixes and updates to gardena-smart-gateway board
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Merge tag 'mips-pull-2018-11-30' of git://git.denx.de/u-boot-mips

- MIPS: MT76xx: minor fixes and updates to gardena-smart-gateway board
2018-11-30 17:09:33 -05:00
Kever Yang
17e5f3a426 rockchip: rk3188: use board_debug_uart_init() for UART io init
Sync with other rockchip SoCs, use board_debug_uart_init() to
init default UART iomux.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 22:00:11 +01:00
Christoph Muellner
af765a49ba rockchip: rk3399: Initialize CPU B clock.
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz.
This decreases the boot time of Linux 4.19 by about 8%.

The 600 MHz are inspired by the 600 MHz used for LPLL initialization
(came in with commit 9f636a249c).

Tested on RK3399-Q7 on Haikou base board.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:45 +01:00
Otavio Salvador
8177c5c452 ARM: dts: rockchip: Add rv1108 USB OTG pinctrl
This adds the definitions need to use the USB OTG in rv1108
board. This has been tested using USB Mass Storage to export and
program a eMMC device.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:45 +01:00
Otavio Salvador
303cbd2141 ARM: rockchip: rv1108: Add a board_usb_init for USB OTG
Like it is done for other Rockchip SoCs, introduce a board_usb_init()
function so that USB OTG can be functional on rv1108 too.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Otavio Salvador
a8819e9a9e ARM: dts: rockchip: Add rv1108 eMMC pinctrl
This adds the pinctrl handles to enable the use of eMMC on custom
boards (as minievk) and makes it easier for later addition.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Otavio Salvador
5d2cb15c77 ARM: rockchip: rv1108: Sync clock with vendor tree
Make adjustments to the rv1108 clock driver in order to align it
with the internal Rockchip version.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Philipp Tomsich
765246a18c rockchip: rk3399-puma: reduce sd card max-frequency to 40MHz
Some SanDisk Ultra cards trigger intermittent errors on detection
resulting in an -EOPNOTSUPP, when running at 50MHz.

Waveform analysis suggest that the level shifters that are used on the
RK3399-Q7 module (for voltage translation between the on-module
voltages and the 3.3V required on the card-edge) don't handle clock
rates at or above 48MHz properly. This change reduces the maximum
frequency on the external SD-interface to 40MHz (for a safety margin
of 20%).

Reported-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
2018-11-30 21:56:44 +01:00
Philipp Tomsich
adbca53a3a rockchip: rk3399: spl: always report errors triggering a hard stop
The RK3399 SPL has two cases that may end in a hard-stop: if either
the pinctrl can not be initialised or if the DRAM fails to initialise.
Both have previously not triggered an error message unless DEBUG was
defined (i.e. both used debug() to print the error).

This converts both error messages to be printed using pr_err() to
ensure that some output points to the cause of the hard-stop.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Heiko Stuebner
6c69ed19f9 rockchip: rk3188: fix early uart setup
Commit 7a6d7d3e12 ("rockchip: pinctrl: rk3188: Move the iomux definitions
into pinctrl-driver") moved the iomux settings out of the grf header
to prevent conflicts with the iomux definitions of other rockchip socs.

This also breaks the early uart setup, as the iomux for uart2 are needed.
To fix that just put the tiny amount of needed iomux definitions next to
the early uart code.

Fixes: 7a6d7d3e12 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Heiko Stuebner
5b5ca4c0d4 rockchip: rk3188: add support for usb-uart functionality
Rockchip socs can route the debug uart pins through the d+ and d- pins
of one specific usbphy per soc. Add a config option and implement the
setting on the rk3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up to mark grf as maybe unused:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30 19:03:16 +01:00
Stefan Roese
b7461e01b9 mips: mt7628: Change compatible property of the ethernet DT node
As the driver has been changed to be more specific, the DT compatible
property also needs to be adapted.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-30 17:21:44 +01:00
Tom Rini
d814ff34a1 Merge git://git.denx.de/u-boot-marvell
- Some Kirkwood boards converted to DM_SPI by Chris
- New Armada-385 SoC revision printed by Chris
- Ethernet enable on mcbin by Baruch
- Support 2 DRAM banks on Armada-8k boards by Baruch
2018-11-30 11:20:03 -05:00
Chris Packham
d997ad034b ARM: mvebu: add revision id for Armada-385 B0
Marvell have release a B0 revision of the Armada-385 SoC. This fixes a
hardware errata enabling RGMII to work when the Ethernet voltage is
configured to 3.3V.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-30 10:58:10 +01:00
Baruch Siach
eff26e4804 arm: mvebu: mcbin: dts: enable 1G network interface
Describe the 1Gb network interface with on-board 88E1512 PHY.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-30 10:58:10 +01:00
Michal Simek
ee97a9996a arm64: zynqmp: Add mini mtest configuration
This configuration is useful when you want to run small u-boot and
perform DDR memory test to make sure that DDR is properly configured.
It is use for board bringup because alternative u-boot memory tests is
quite good.
Configuration is running out of OCM.

As is done for others mini configurations 0x80 bytes for variables is
enough and only default variables are stored there.

Alternative memtest is enabled and also 2GB of DDR via DTS files.
Configuration is enabling ZYNQMP_PSU_INIT_ENABLED and include psu_init()
from zcu102 for testing purpose.
In case of size issue this can be moved to SPL configuration as is done
for mini_qspi configuration but it is not a problem now.

Log:
U-Boot 2018.11-00268-gbd58b8ba8915 (Nov 29 2018 - 15:33:35 +0100)

Model: ZynqMP MINI
Board: Xilinx ZynqMP
DRAM:  WARNING: Initializing TCM overwrites TCM content
2 GiB
EL Level:       EL3
In:    dcc
Out:   dcc
Err:   dcc
ZynqMP>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-30 10:45:26 +01:00
Tom Rini
6d4a3ff264 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-11-29 16:36:53 -05:00
Tom Rini
93e72ac472 Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
 - net: designware: add meson meson compatibles
 - Amlogic Meson cleanup for AXG SoC support
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Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
2018-11-29 15:16:58 -05:00
Simon Glass
b847c14243 sandbox: Use memmove() to move overlapping regions
The use of strcpy() to remove characters at the start of a string is safe
in U-Boot, since we know the implementation. But in os.c we are using the
C library's strcpy() function, where this behaviour is not permitted.

Update the code to use memmove() instead.

Reported-by: Coverity (CID: 173279)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-11-29 09:30:05 -07:00
Simon Glass
1180030d12 sandbox: Enable sound
Now that the buffer-overflow bug is fixed, we can enable sound on sandbox.
Drop the code which exits early.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-29 09:30:05 -07:00
Simon Glass
856b8f5629 sound: sandbox: Use the correct frequency
At present we request a particular frequency but we may not get the exact
same frequency in response. So use the actual frequency for generation of
the square wave. This ensures that the pitch remains accurate on all host
machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-29 09:30:05 -07:00
Simon Glass
7d92b06090 sound: Add sample rate as a parameter for square wave
At present this value is hard-coded in the function that generates a
square wave. Since sample rates vary between different hardware, it makes
more sense to have this as a parameter.

Update the function and its users.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-29 09:30:05 -07:00
Simon Glass
031a650e13 dm: sandbox: i2c: Use new emulator parent uclass
Update the device tree, sandbox i2c driver and tests to use the new
emulation parent to hold emulators.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-29 09:30:05 -07:00
Simon Goldschmidt
30bade20a6 arm: socfpga: fix SPL booting from fpga OnChip RAM
This patch prevents disabling the FPGA bridges when
SPL or U-Boot is executed from FPGA onchip RAM.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
e8dd60d489 arm: socfpga: make socfpga_socrates_defconfig boot from QSPI
This fixes the board's dts to supply SPL with QSPI info.

The EBV Socrates board has DIP switches to boot from SD card or
QSPI, so let's fix its defconfig to work for both cases.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
c402e81702 dts: arm: socfpga: merge gen5 devicetrees from linux
Add -u-boot.dtsi files to keep the current U-Boot behaviour:
- add u-boot,dm-pre-reloc where required
- disable watchdog
- set uart clock frequency
- add gpio bank-name properties
where appropriate:
- make qspi work (add alias for spi0, fix compatible for flash)
- enable usb (status okay, add alias for udc0)

Adapt board dts files that are not in Linux to keep their old
behaviour.

Change licenses to SPDX.

(Patman warnings/errors are in 1:1 copied files from Linux)

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
2a3a99932b spi: cadence_qspi: use "cdns,qspi-nor" as compatible
Linux uses "cdns,qspi-nor" as compatible string for the cadence
qspi driver, so change driver, docs and all device trees.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Simon Goldschmidt
dd8ee8ea2a arm: socfpga: make config structs const
There are two config structs left in wrap_sdram_config.c that can
be made const.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Michal Simek
6bd13ee94e arm64: zynqmp: Setup clock-output-names for si570 chips
If there are more instances of si570 clock-output-names property
should be used for differentiation of clock output.
The patch is adding this optional properties for all zynqmp boards with
si570 chip.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:30:02 +01:00
Michal Simek
8418d2deb8 arm64: zynqmp: Disable ltc2952 poweroff chip
This chip is on the board but handling should be done via firmware not
via Linux driver. Changing status property to keep it in the tree to
describe it instead of removing this node completely.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:30:02 +01:00
Michal Simek
d1fb3d024e arm64: zynqmp: Fix sdhci clock in emmc0 mini configuration
Add missing clocks property.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:30:02 +01:00
Michal Simek
0ed45f0025 arm64: zynqmp: Wire spi-flash compatible string with flashes
Enable reading tx and rx buswidth from DT via spi-uclass.
To get these from uclass spi-flash compatible string has to be added
to flash node.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:30:02 +01:00
Siva Durga Prasad Paladugu
9cd26aaf39 arm64: zynqmp: Define and enable qspi node for DC4 board
DC4 board has qspi on it hence define and enable
qspi node for it.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:29:58 +01:00
Ryder Lee
01aa9d1d54 pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range.  Hence the driver also implements the gpio
functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:52 -05:00
Weijie Gao
361e13f1d5 arm: MediaTek: add basic support for MT7623 boards
This adds a general board file based on MT7623 SoCs from MediaTek.

As this u-boot is loaded by MTK proprietary preloader, there is no
low level initializtion codes.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:50 -05:00
Ryder Lee
cbd2fba1ec arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek.

Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:50 -05:00
Ryder Lee
d84982dbfa arm: dts: MediaTek: add device tree for MT7623
This adds device tree for MT7623 development board - Bananapi R2
Detailed hardware information for BPI-R2 which could be found on
http://wiki.banana-pi.org/Banana_Pi_BPI-R2.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:50 -05:00
Ryder Lee
376ac00dc3 arm: dts: MediaTek: add device tree for MT7629
This patch adds MT7629 device tree and the includes it needs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-28 23:04:49 -05:00
Jagan Teki
35f9d9bdd0 spi: Zap CONFIG_HARD_SPI
In legacy CONFIG_HARD_SPI initalizing spi_init code, which
was removed during dm conversion cleanup.

So remove the dead instances of CONFIG_HARD_SPI, and related
code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27 21:06:53 +05:30
Marcin Niestroj
627d74c79b ARM: dts: am335x-chiliboard: add /chosen/stdout-path
Add that node path in u-boot overlay dtsi file for now to keep
am335x-chiliboard.dts in sync with Linux.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26 22:52:13 -05:00
Marcin Niestroj
e067379f88 ARM: dts: am335x-chili*: add chiliSOM and chiliboard DTS files
Import chiliSOM and chiliboard dts files from Linux v4.19. They will
be used after transition to driver model and device-tree based boot.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26 22:52:13 -05:00
Andrew F. Davis
a0106c82d6 ARM: armv7: Add early stack for erratum workarounds
Some erratum workarounds call into C code before the stack
is setup, this can lead to values pushed onto the stack
being lost, firewall exceptions, and other undefined behavior.

Setup a temporary stack to allow these functions to work
correctly.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2018-11-26 22:52:12 -05:00
Lokesh Vutla
ccdb7c2255 armv7r: K3: Allow SPL to run only on core 0
Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.

If efuse settings are in lockstep mode: ROM release R5 cores
and SPL continues to run on the R5 core is lockstep mode.

If efuse settings are in split mode: ROM releases both the R5
cores simultaneously and allow SPL to run on both the cores.
In this case it is bootloader's responsibility to detect core
1 and park it. Else both the core will be running bootloader
independently which might result in an unexpected behaviour.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-26 22:52:11 -05:00
Tom Rini
c06088b360 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-11-26 15:52:47 -05:00
Tom Rini
ef0b75d3d8 Merge git://git.denx.de/u-boot-riscv 2018-11-26 15:52:39 -05:00
Neil Armstrong
d96a782d09 ARM: meson: Add boot device discovery
The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol.

When no other boot medium are available (or by forcing the USB mode), the
ROM sets the primary USB port as device mode and waits for a Host to
enumerate.

When enumerated, a custom protocol described at [1] permits writing to
memory and execute some specific FIP init code to run the loaded
Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage.

In this mode, we can load different binaries that can be used by U-boot
like a script image file.

This adds support for a custom USB boot stage only available when the
boot mode is USB and the script file at a pre-defined address is valid.
This support was heavily copied from the Sunxi Allwinner FEL U-Boot support.

The tool pyamlboot described at [2], permits using this boot mode on boards
exposing the first USB port, either as OTG or Host port.

[1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md
[2] https://github.com/superna9999/pyamlboot/blob/master/README.md

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
b890acc743 ARM: meson: factorize common code out amlogic's boards
Now we have moved all the Amlogic board support to common generic board code,
we can move the identical board_init() and ft_board_setup() functions to
weak functions into the board-common mach-meson file.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
b72794e37e board: amlogic: add support for S400 board
The S400 board is the Amlogic AXG SoC reference board including :
 - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
 - 1GB DDR4 SDRAM
 - 10/100 Ethernet
 - 2 x USB 2.0 Host
 - eMMC
 - Infrared receiver
 - SDIO WiFi Module
 - MIPI DSI Connector
 - Audio HAT Connector
 - PCI-E M.2 Connectors

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
f6eb68b978 clk: Add clock driver for AXG
This patch adds a minimal clock driver for the Amlogic AXG SoC to handle
the basic gates and PLLs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
78a08019cd ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1
Synchronize the Amlogic AXG Device Tree files and bindings include from
the recent Linux 4.20-rc1, because it includes patches fixing support for
U-boot.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Neil Armstrong
485bba395e ARM: meson: Add support for AXG family
This patch adds support for the Amlogic AXG SoC, which is very close from
the Amlogic GXL SoCs with :
- Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max
- DDR Interface limited to DDR4 16bit
- The whole physical register address space has been moved to 0xfxxxxxxx
- The pinctrl setup has changed
- The clock tree is different enough to use a different driver

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
33e3378091 ARM: meson: rework soc arch file to prepare for new SoC
We are about to add support for the Amlogic AXG SoC. While very close to
the Gx SoC family, we will need to handle a few thing which are different
in this SoC. Rework the meson arch directory to prepare for this.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
96a739b460 ARM: rework amlogic configuration
Rework the board SYS_BOARD, SYS_VENDOR and SYS_CONFIG_NAME setup by moving
the board Kconfig into the mach-meson Kconfig to make it easier to add
new boards for a SoC architecture and add a custom config header or custom
board handler for a platform.

This drops the board CONFIGs and the duplicate boards configs headers in
favor of a single meson64.h config header.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:52 +01:00
Jerome Brunet
d54e03b612 board: amlogic: factorise gxbb boards
The nanopi-k2 and the odroid-c2 are similar enough to be supported
by the same u-boot board. This change use odroid-c2 u-boot board
for the nanopi-k2 as well. Dedicated defconfig are kept to customize
the names and device tree.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:51 +01:00
Neil Armstrong
302987b6c5 board: amlogic: move khadas-vim2 as q200 ref board
The Khadas vim2 derive from amlogic s912 reference design (Q200).

This patch moves the khadas-vim2 board support to a generic Q200 board,
while keeping a dedicated defconfig to customize the names and device tree.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:51 +01:00
Jerome Brunet
8bbfb40e57 board: amlogic: remove p212 derivatives
The Khadas vim and the libretech aml-s905x-cc (aka Potato) derive
from amlogic s905x reference design (P212).

All the code in these board is a copy/paste from the p212, which is
tedious to maintain. This change use p212 u-boot board for all these
boards, while keeping a dedicated defconfig to customize the names
and device tree.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:51 +01:00
Jerome Brunet
32caa1e2f1 ARM: meson: clean-up platform selection
Even if multiple board are selected through Kconfig, u-boot will only
compile one. This makes sense since compiling these targets will export
global symbols, such as board_init()

The change rework amlogic Kconfig so only one board may be selected at
a time

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:51 +01:00
Simon Glass
b0edea3c27 spl: Add support for passing handoff info to U-Boot proper
There is some basic informaton that SPL normally wants to pass through to
U-Boot, such as the SDRAM size and bank information.

Mkae use of the new bloblist structure for this. Add a new 'handoff' blob
which is set up in SPL and passed to U-Boot proper. Also adda  test for
sandbox_spl that checks that this works correctly and a new 'sb' command
to show the information passed from SPL.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-26 08:25:37 -05:00
Simon Glass
27028f186d sandbox: Boot in U-Boot through the standard call
Most architectures use jump_to_image_no_args() to jump from SPL to U-Boot.
At present sandbox is special in that it jumps in its
spl_board_load_image() call. This is not strictly correct, and means that
sandbox misses out some parts of board_init_r(), just as calling
bloblist_finish(), for example.

Change spl_board_load_image() to just identify the filename to boot, and
implement jump_to_image_no_args() to actually jump to it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-26 08:25:37 -05:00
Simon Glass
65f3b1f992 sandbox: Filter arguments when starting U-Boot
The current method of starting U-Boot from U-Boot adds arguments to pass
the memory file through, so that memory is preserved. This is fine for a
single call, but if we call from TPL -> SPL -> U-Boot the arguments build
up and we have several memory files in the argument list.

Adjust the implementation to filter out arguments that we want to replace
with new ones. Also print a useful error if the exec() call fails.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-26 08:25:37 -05:00
Simon Glass
fc1f58a4da sandbox: Use malloc() and free() from os layer
At present sandbox calls malloc() from various places in the OS layer and
this results in calls to U-Boot's malloc() implementation. It is better to
use the on in the OS layer, since it does not mix allocations with the
main U-Boot code.

Fix this by replacing calls with malloc() to os_malloc(), etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-26 08:25:37 -05:00
Simon Glass
7b5ea14527 sandbox: Refactor code to create os_jump_to_file()
At present os_jump_to_image() jumps to a given image, and this is written
to a file. But it is useful to be able to jump to a file also.

To avoid duplicating code, split out the implementation of
os_jump_to_image() into a new function that jumps to a file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-26 08:25:36 -05:00
Simon Glass
d66ddafaf9 sandbox: Add a new 'sb' command
The old 'sb' command was deprecated in 2015 and replaced with 'host'. It
is useful to be able to access some internal sandbox state, particularly
for testing.

Resurrect the old command and provide a way to print some basic state
information (currently just the arguments to sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-26 08:25:36 -05:00
Simon Glass
1ca910be5d sandbox: Add an option to display of-platdata in SPL
At present we don't have a test that of-platdata can be accessed in SPL.
Add this in as a command-line option to SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-26 08:25:35 -05:00
Simon Glass
919e7a8fb6 test: Add a simple test for bloblist
Add a unit test for the bloblist functionality and enable bloblist for
sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-26 08:25:33 -05:00
Michal Simek
850e7795cd arm64: zynqmp: Enable SPL_SEPARATE_BSS by default
BSS section was all the time separated for SPL but this symbol wasn't
enabled. It is necessary to have it enabled for OF_SEPARATE
configuration where DTB is appended to u-boot with DTB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:55 +01:00
Michal Simek
f3289d1f0e arm64: zynqmp: Reflect emmc controller ID in model in DT
Make sense to add controller ID to model name to have it visible through
the logs to know which controller is used by which configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:55 +01:00
Siva Durga Prasad Paladugu
c25e804dd8 arm: zynq: cse_qspi: Fix overwriting spi-rx-bus-width property
spi-rx-bus-width property is part of flash, so it should be moved
to flash node from qspi node. This patch fixes the incorrect read
of spi-rx-bus-width property by moving it to flash node.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-26 10:50:54 +01:00
Rick Chen
52923c6db7 riscv: cache: Implement i/dcache [status, enable, disable]
AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.

This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.

This approach also provide the expansion when the
vender specific features are going to join in.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2018-11-26 13:58:01 +08:00
Rick Chen
bae2d72507 riscv: dts: Add ae350_32.dts for RV32I
Add ae350_32.dts for 32 bit. And also rename
ae350.dts to ae350_64.dts for 64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2018-11-26 13:57:55 +08:00
Rick Chen
7424e95a69 riscv: dts: Sync to Linux Kernel ae350 dts.
Use same dts to boot U-Boot and Kernel.

Following are the change notes :
1 Remove early printk bootargs.
2 Timer frequency are changed to 60MHz.
3 Add dma, snd, lcd, virtio nodes which are used
  in kernel drivers. They does not been used by U-Boot.
4 Change spi irq from 3 to 4.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
2018-11-26 13:57:44 +08:00
Lukas Auer
c3b1a99040 riscv: align bootm implementation with that of other architectures
The bootm implementation of RISC-V diverges from that of other
architectures. Update it to match the implementation of other
architectures. The ARM implementation is used as a reference.

This adds the following features and changes to RISC-V.
* Add support for the BOOTM_STATE_OS_FAKE_GO command
* Call the remove function on devices with the removal flag set before
booting Linux
* Force disconnect USB devices from the host before booting Linux
* Print and add bootstage information to the device tree before booting
Linux

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:32 +08:00
Lukas Auer
5d8b2e7711 riscv: save hart ID and device tree passed by prior boot stage
Store the hart ID and device tree passed by the prior boot stage (in a0
and a1) in registers s0 and s1. Replace one use of s1 in start.S to
avoid overwriting it.

The device tree is also stored in memory to make it available to U-Boot
with the configuration CONFIG_OF_PRIOR_STAGE.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:32 +08:00
Lukas Auer
31f9058994 riscv: do not blindly modify the mstatus CSR
The mstatus CSR includes WPRI (writes preserve values, reads ignore
values) fields and must therefore not be set to zero without preserving
these fields. It is not apparent why mstatus is set to zero here since
it is not required for U-Boot to run. Remove it.

This instruction and others encode zero as an immediate.  RISC-V has the
zero register for this purpose. Replace the immediates with the zero
register.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:32 +08:00
Lukas Auer
8bfa231cc6 riscv: remove unused labels in start.S
The labels nmi_vector, trap_vector and handle_reset in start.S are not
used for RISC-V. Remove them.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:32 +08:00
Bin Meng
c95cafd0b1 Drop CONFIG_INIT_CRITICAL
This is now deprecated and no board is using it. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-11-26 13:57:31 +08:00
Lukas Auer
2a23ac6107 riscv: align mtvec on a 4-byte boundary
The machine trap-vector base address (mtvec) must be aligned on a 4-byte
boundary. Add the necessary align directive to trap_entry.

This patch also removes the global directive for trap_entry, which is
not required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:31 +08:00
Lukas Auer
c55309c091 riscv: fix inconsistent use of spaces and tabs in start.S
start.S uses both tabs and spaces after instructions. Fix this by only
using tabs after instructions.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:31 +08:00
Lukas Auer
62a09ad53b riscv: implement the invalidate_icache_* functions
Implement the functions invalidate_icache_range() and
invalidate_icache_all().

RISC-V does not have instructions for explicit cache-control. The
functions in this patch are implemented with the memory ordering
instruction for synchronizing the instruction and data streams. This may
be implemented as a cache flush or invalidate on simple processors,
others may only invalidate the relevant cache lines.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:31 +08:00
Lukas Auer
c93a1c8185 riscv: hang on unhandled exceptions
Hang on unhandled exceptions to prevent execution in a faulty state.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
e8b522b1df riscv: treat undefined exception codes as reserved
Undefined exception codes currently lead to an out-of-bounds array
access. Prevent this by treating undefined exception codes as
"reserved".

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
5a441736b7 riscv: complete the list of exception codes
Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
f105d2efcb riscv: do not reimplement generic io functions
RISC-V U-Boot reimplements the generic io functions from
asm-generic/io.h. Remove the redundant implementation and include the
generic io.h instead.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
fc8c76f42e riscv: make use of the barrier functions from Linux
Replace the barrier functions in arch/riscv/include/asm/io.h with those
defined in barrier.h, which is imported from Linux. This version is
modified to remove the include statement of asm-generic/barrier.h, which
is not available in U-Boot or required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:30 +08:00
Lukas Auer
b2c860c6dc riscv: fix use of incorrectly sized variables
The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in
several places. Fix this.
In addition, BITS_PER_LONG is set to 64 on RV64I systems.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
776e6335bf riscv: enable -fdata-sections
Enable the -fdata-sections compiler option for RISC-V. Buildman reports
the binary size decrease from this as 8365.3 bytes.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
0c074845e5 riscv: set -march and -mabi based on the Kconfig configuration
Use the new Kconfig entries to construct the ISA string for the -march
compiler flag. The -mabi compiler flag is selected based on the base
integer instruction set.

With this change, the C (compressed instructions) ISA extension is now
enabled for all boards with CONFIG_RISCV_ISA_C set. Buildman reports a
decrease in binary size of 71590 bytes.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
d57ffa650f riscv: add Kconfig entries for the C and A ISA extensions
Add Kconfig entries for the C (compressed instructions) and A (atomic
instructions) ISA extensions. Only the C ISA extension is selectable.
This matches the configuration in Linux.

The Kconfig entries are not used yet. A follow-up patch will select the
appropriate compiler flags based on the Kconfig configuration.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
711585649e riscv: select CONFIG_PHYS_64BIT on RV64I systems
CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:29 +08:00
Lukas Auer
862e2e75e8 riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-26 13:57:29 +08:00
Michael Trimarchi
aa09a071c3 sunxi: Fix memory 2-rank initialization for a33 cpu
When we initialize the memory we need to autodetect rank and size
but this can happen only if we send the proper reset to both
memory module including cke signal.
For this reason we need initialize the physical on both channel because
we need to presume that both are connected. This way let the CLKE to be
activated at the right time with the memory reset coming from the cpu

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-22 13:24:15 +05:30
Vasily Khoruzhick
0e21a2ffb3 sunxi-mmc: use new mode on both controllers on A64
Using new mode improves stability of eMMC and SD cards. Without
it SPL fails to load u-boot from SD on Pinebook.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-22 13:20:16 +05:30
Vasily Khoruzhick
2a8882ecef sunxi-mmc: introduce new MMC_SUNXI_HAS_MODE_SWITCH option
Allwinner A64 has new mode but doesn't have a mode switch in CCM,
and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails
if MMC_SUNXI_HAS_NEW_MODE is enabled

Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage
of CCM_MMC_CTRL_MODE_SEL_NEW

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: update commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
2018-11-22 13:19:19 +05:30
Simon Glass
a58986ca8b sf: Add a method to obtain the block-protect setting
It is useful to obtain the block-protect setting of the SPI flash, so we
know whether it is fully open or (perhaps partially) write-protected. Add
a method for this. Update the sandbox driver to process this operation and
add a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
8729b1ae2c misc: Update read() and write() methods to return bytes xfered
At present these functions return 0 on success. For some devices we want
to know how many bytes were transferred. It seems useful to adjust the API
to be more like the POSIX read() and write() functions.

Update these two methods, a test and all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-20 19:14:22 -07:00
Simon Glass
4a5b5e1a46 sandbox: Update some drivers to work in SPL/TPL
At present sandbox drivers are mostly not used before relocation. Some of
these are needed by Chromium OS verified boot, since it uses sandbox TPL,
so update them accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Simon Glass
566bf3a869 sandbox: Add a function to read a host file
Add a way to read a file from the host filesystem. This can be useful for
reading test data, for example. Also fix up the writing function which was
not the right version, and drop the debugging lines.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Heinrich Schuchardt
9190a3eb80 sandbox: remove stray DEBUG
DEBUG should not be defined in production code.
Change printf() to debug() where this writes a debug message.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-20 19:14:22 -07:00
Rabeeh Khoury
5bbf36af7f ARM: mvebu: dts: add Clearfog GT-8K
The SolidRun Clearfog GT-8K is based on Armada 8040.

https://wiki.solid-run.com/doku.php?id=products:a8040:clearfoggt8k

The config file is identical to the Macchiatobin one
(mvebu_mcbin-88f8040_defconfig) with only the default device-tree
changed.

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:44 +01:00
Baruch Siach
2b4d964718 arm64: mvebu: a8k: autodetect RAM size
Some Armada 8K boards like Macchiatobin and Clearfog GT-8K use RAM from
external DIMM. Hard coding the RAM size in the device-tree is not
convenient. Fortunately, the ATF that initializes the RAM knows the size
of RAM, and U-Boot can query the ATF using a SMC call.

The ATF maps the lower 3G of RAM starting at address 0. Higher RAM is
mapped at 4G. This leaves a 1G hole between 3G and 4G for IO
peripherals. Use a second bi_dram[] entry to describe the higher RAM
area. As a result, CONFIG_NR_DRAM_BANKS must be set to 2 to use more
than 3GB RAM.

This code in this commit is mostly taken from downstream Marvell U-Boot
code by Grzegorz Jaszczyk.

Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Baruch Siach
b335e91bd1 linux/sizes.h: sync from kernel
The kernel added SZ_4G macro in commit f2b9ba871b (arm64/kernel: kaslr:
reduce module randomization range to 4 GB).

Include linux/const.h for the _AC macro.

Drop a local SZ_4G definition in tegra code.

Cc: Tom Warren <twarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Baruch Siach
6d4d9bea35 MIPS: drop asm/const.h
Commit 86f21c96f4 (mips: Use common _AC macro now.) removed the _AC
definition from const.h. All other macros defined in const.h are not
used anywhere, and there is now no user of this header. Remove this
header.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Baruch Siach
5c8fd32b22 Use _AC and UL macros from linux/const.h
Drop the _AC and UL macros from common.h. Linux headers is the original
source of this macro, so keep its definition in the same header.

Update existing users of these macros to include const.h directly.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Daniel Schwierzeck
1bef0c530b MIPS: fix linking of standalone programs
Use the global MIPS specific u-boot.lds for linking standalone programs
instead of the outdated ones in examples/standalone/. Also pass --gc-sections
in LDFLAGS_STANDALONE to optimize the size of standalone programs.
Finally remove the deprecated config.mk files in arch/mips/cpu/mips[32,64]/.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:23 +01:00
Daniel Schwierzeck
1d3b97c94e Kbuild: add LDFLAGS_STANDALONE
Introduce a new Makefile variable for passing LDFLAGS to standalone
programs. Currently the variable CONFIG_STANDALONE_LOAD_ADDR is
misued on some archs to pass a specific linker script.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-18 16:02:23 +01:00
Stefan Roese
101860ef69 mips: mt76xx: linkit-smart-7688: Misc updates to dts/config/defconfig
These misc updates include the following changes:
- Change baudrate from 57600 to 115200
- Enable MIPS_BOOT_CMDLINE_LEGACY
- Enable FIT support
- Enable ethernet support
- Enable SPI support
- Enable GPIO support
- Change max image size from 0x40000 to 0x80000

A note about the baudrate change:

The original Mediatek U-Boot version used 57600 baud. Lets move to a
more common and faster speed of 115200 baud. And remove the "console="
property from the DT as its not needed.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:23 +01:00
Stefan Roese
78e2517185 mips: mt76xx: gardena-smart-gateway: Misc updates to dts/config/defconfig
These misc updates include the following changes:
- Change baudrate from 57600 to 115200
- Enable MIPS_BOOT_CMDLINE_LEGACY
- Enable FIT support
- Enable ethernet support
- Enable SPI NOR and NAND support
- Change MTD_UBI_BEB_LIMIT to 22
- Enable MTD Support
- Enable GPIO support
- Enable watchdog support
- Enable bootcounter support
- Enable version variable
- Change max image size from 0x80000 to 0xa0000
- Change SYS_MALLOC_LEN to 16MiB (because of UBI/UBIFS)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:23 +01:00
Stefan Roese
b1f51fc24f mips: mt76xx: gardena-smart-gateway: Add board_late_init() to set LED def state
This is needed to set the LEDs automatically to a default state, as
configured in the dts.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:23 +01:00
Stefan Roese
840293b83c mips: mt76xx: gardena-smart-gateway: Add LEDs to dts
Add the available LEDs to the DTS file so that they can be used.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:23 +01:00
Stefan Roese
4ff942b059 mips: mt76xx: Enable watchdog support
This patch enables and starts the watchdog on the MT7620 platform.
Currently the WD timeout is configured to 60 seconds.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[fixed build error due to missing function prototype arch_misc_init]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:22 +01:00
Stefan Roese
b4a6a1bb3f mips: mt76xx: Kconfig: Add ethernet and GPIO support
Imply DM_ETH and DM_GPIO for ARCH_MT7620, as this platform now supports
ethernet and GPIO as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:22 +01:00
Stefan Roese
9a89b2b9b2 mips: mt76xx: Add watchdog DT node to mt7628a.dtsi
Add the watchdog DT node to the DTS file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:22 +01:00
Stefan Roese
60f6be1241 mips: mt76xx: Add GPIO DT nodes to mt7628a.dtsi
Add the GPIO DT nodes to the DTS file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:22 +01:00
Stefan Roese
82dbe6483c mips: mt76xx: Add ethernet DT node to mt7628a.dtsi
Add the ethernet DT node to the DTS file.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:22 +01:00
Stefan Roese
a8b0bf6313 mips: mt76xx: lowlevel_init.S: Add missing memory controller reset in DDR init
This fixes an issue which has been noticed on the Gardena board, with
the watchdog enabled, where the watdchdog reset (after a system hang)
did result in reporting of 2.9 GiB and a hang after this. With this
patch applied the memory controller is correctly reset and initialized
again even after a watchdog reset.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:22 +01:00
Lokesh Vutla
00b34e9937 armv7r: dts: am654: Add initial support
Add R5 specific dts for am654-evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-16 16:51:59 -05:00
Lokesh Vutla
2d0eba3a45 arm: dts: k3: Sync dts from Linux
Sync the k3-am654 specific dts files from Linux next with tag
20181019. This changes are in queue for Linux v4.20-rc1

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16 16:51:59 -05:00
Lokesh Vutla
59ebf4afa6 armv7R: K3: am654: Add support for triggering ddr init from SPL
In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support
for triggering DDR initialization from board_init_f().

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16 16:51:59 -05:00
Lokesh Vutla
a3501a4a44 armv7R: K3: am654: Add support to start ATF from R5 SPL
Considering the boot time requirements, Cortex-A core
should be able to start immediately after SPL on R5.
Add support for the same.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16 16:51:58 -05:00
Lokesh Vutla
890b2e750d armv7R: K3: am654: Add support for generating build targets
Update Makefiles to generate:
- tiboot3.bin: Image format that can be processed by ROM.

Below is the tiboot3.bin image format that is required by ROM:

		 _______________________
		|	 X509		|
		|     Certificate	|
		| ____________________	|
		| |		      |	|
		| | u-boot-spl.bin    |	|
		| |		      |	|
		| |___________________|	|
		|_______________________|

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2018-11-16 16:51:58 -05:00
Lokesh Vutla
23f7b1a776 armv7R: K3: am654: Enable MPU regions
Enable MPU regions for AM654 evm:
- Region0: 0x00000000 - 0xFFFFFFFF: Device memory, not executable
- Region1: 0x41c00000 - 0x42400000: Normal, executable, WB, Write alloc
- Region2: 0x80000000 - 0xFFFFFFFF: Normal, executable, WB, Write alloc
- region3-15: Disabled

With this dcache can be enabled either in SPL or U-Boot.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-16 16:51:58 -05:00
Lokesh Vutla
06bda1259f ram: Introduce K3 AM654 DDR Sub System driver
K3 based AM654 devices has DDR memory subsystem that comprises
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
intergrate these blocks into the device. This DDR subsystem
provides an interface to external SDRAM devices. Adding support
for the initialization of the external SDRAM devices by
configuring the DDRSS registers and using the buitin PHY
routines.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
2018-11-16 16:51:58 -05:00
Klaus Goger
ba08afe837 arm: Make arch specific memcpy thumb-safe.
The current arch implementation of memcpy cannot be called
from thumb code, because it does not use bx instructions on return.
This patch addresses that. Note, that this patch does not touch
the hot loop of memcpy, so performance is not affected.

Tested on MXS (arm926ejs) with and without thumb-mode enabled.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
2018-11-16 16:51:57 -05:00
Patrice Chotard
f41a824b23 test/py: test pinmux command
Add pinmux test which test the following commands:
  - pinmux list
  - pinmux dev
  - pinmux status

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Mark some tests as sandbox-centric]
Signed-off-by: Tom Rini <trini@konsulko.com>

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-11-16 16:51:57 -05:00
Adam Ford
c3b89468fc ARM: DTS: Resync am3517-evm.dts with Linux 4.19
Some minor changes have been made to the AM3517-evm and the underlying
am3517.dtsi files.  This patch re-sync's the DTS and DTSI files with
Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-11-16 13:34:37 -05:00
Philippe Reynes
786dc91492 bcm968580xref: add initial support
This add the initial support of the broadcom reference
board bcm968580xref with a bcm6858 SoC.

This board has 512 MB of ram, 256 MB of flash (nand),
2 usb port, 1 uart, 4 ethernet ports (LAN), 1 ethernet port (WAN).

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-11-16 13:34:35 -05:00
Philippe Reynes
40b59b0586 bcm6858: add initial support
This add the initial support of the broadcom bcm6858 SoC family,
only the cpu, dram and uart are supported.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-11-16 13:34:35 -05:00
Prasanthi Chellakumar
1473f6ac88 arm: at91: wdt: Convert watchdog driver to dm/dt
Convert the Watchdog driver for AT91SAM9x processors to support
the driver model and device tree. Changes "CONFIG_AT91SAM9_WATCHDOG"
to new "CONFIG_WDT_AT91" Kconfig option.

Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar@microchip.com>
2018-11-16 13:34:34 -05:00
Chee Hong Ang
eb13dddd2c ARMv8: SError exception handling in PSCI exception vectors
Allow platform vendors to handle SError interrupt exceptions from
ARMv8 PSCI exception vectors by overriding this weak function
'plat_error_handler'.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:34 -05:00
Chee Hong Ang
c0f3296f83 ARMv8: Add EL3 exception handling for ARMv8's Kconfig
Kconfig option to allow all External Abort and SError exception
taken to EL3.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:34 -05:00
Chee Hong Ang
a7aab5bcb5 ARMv8: Enable all asynchronous abort exceptions taken to EL3
Allow EL3 to handle all the External Abort and SError interrupt
exception occur in all exception levels.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:33 -05:00
Tom Rini
1d6edcbfed - virtio implementation and supporting patches
- DM_FLAG_PRE_RELOC fixes
 - regmap improvements
 - minor buildman and sandbox things
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Merge tag 'pull-14nov18' of git://git.denx.de/u-boot-dm

- virtio implementation and supporting patches
- DM_FLAG_PRE_RELOC fixes
- regmap improvements
- minor buildman and sandbox things
2018-11-16 08:37:50 -05:00
Tom Rini
6f44333018 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-11-14 18:25:34 -05:00
Bin Meng
25d0fe743d cpu: sandbox: Add "u-boot, dm-pre-reloc" for all cpu nodes
To support CONFIG_DISPLAY_CPUINFO, add "u-boot,dm-pre-reloc" for
all cpu nodes in Sandbox test.dts.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-11-14 09:16:28 -08:00
Bin Meng
c337e1afd3 cpu: Add DM_FLAG_PRE_RELOC flag to various cpu drivers
It turns out commit c0434407b5 broke some boards which have DM CPU
driver with CONFIG_DISPLAY_CPUINFO option on. These boards just fail
to boot when print_cpuinfo() is called during boot.

Fixes: c0434407b5 ("board_f: Use static print_cpuinfo if CONFIG_CPU is active")
Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2018-11-14 09:16:28 -08:00
Bin Meng
ef329a6a73 sysreset: Remove DM_FLAG_PRE_RELOC flag in various drivers
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.

To mitigate this potential impact, the following changes are
implemented:

- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
  only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
  is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
  drivers that support both statically declared devices and
  configuration from device tree

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:28 -08:00
Bin Meng
4854ebc57e arm: stm32mp: Remove DM_FLAG_PRE_RELOC flag
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.

To mitigate this potential impact, the following changes are
implemented:

- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
  only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
  is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
  drivers that support both statically declared devices and
  configuration from device tree

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-14 09:16:28 -08:00
Bin Meng
4f89d4947c test: dm: virtio: Add test cases for virtio uclass
Now that we have a sandbox virtio transport driver, add some test
cases to test virtio uclass driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:28 -08:00
Bin Meng
6f3327658b arm: qemu: Add a Kconfig in the board directory
This adds a Kconfig file in the board directory, so that some
board-specific options can be specified there.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:28 -08:00
Bin Meng
3bf9a8e846 x86: Implement arch-specific io accessor routines
At present the generic io{read,write}{8,16,32} routines only support
MMIO access. With architecture like x86 that has a separate IO space,
these routines cannot be used to access I/O ports.

Implement x86-specific version to support both PIO and MMIO access,
so that drivers for multiple architectures can use these accessors
without the need to know whether it's MMIO or PIO.

These are ported from Linux kernel lib/iomap.c, with slight changes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:27 -08:00
Bin Meng
b1893a9e0d riscv: bootm: Add dm_remove_devices_flags() call to do_bootm_linux()
This adds a call to dm_remove_devices_flags() to do_bootm_linux()
so that drivers that have one of the removal flags set (e.g.
DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may do some
last-stage cleanup before the OS is started.

arm and x86 already did such, and we should do the same for riscv.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:27 -08:00
Mario Six
4d9ada54a2 mips: Implement {in, out}_{le, be}_{16, 32, 64} and {in, out}_8
MIPS is the only architecture currently supported by U-Boot that does
not implement any of the in/out register access functions.

To have a interface that is useable across architectures, add the
functions to the MIPS architecture (implemented using the __raw_write
and __raw_read functions).

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-11-14 09:16:27 -08:00
Simon Glass
bd8b74551b sandbox: Try to start the RAM buffer at a particular address
Use a starting address of 256MB which should be available. This helps to
make sandbox RAM buffers pointers more recognisable.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:27 -08:00
Mario Six
82744c20e6 test: regmap: Increase size of syscon0 memory
The upcoming changes to the regmap interface will contain a proper check
for plausibility when reading/writing from/to a register map. To still
have the current tests pass, increase the size of the memory region for
the syscon0 device, since one of the tests reads and writes beyond this
range.

Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-11-14 09:16:27 -08:00
Bin Meng
2786cd740e test: dm: core: Add a test case for driver marked with DM_FLAG_PRE_RELOC flag
Now that we fixed the pre-relocation driver binding for driver marked
with DM_FLAG_PRE_RELOC flag, add a test case to cover that scenario.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:27 -08:00
Tom Rini
208ecbad2e Merge branch 'next'
This brings in the u-boot-net PR from Joe.
2018-11-14 11:30:07 -05:00
Icenowy Zheng
7d121a8ea4 sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD
DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
let PLL_VIDEO be high enough for them.

Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:17:06 +05:30
Jagan Teki
e6b16e7852 board: allwinner: sun50i-h6: Add Orangepi Lite2 support
OrangePi Lite2 is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- AP6356S Wifi/BT
- USB 2.0, USB 3.0 Host, OTG
- HDMI port
- 5V/2A DC power supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-13 22:13:09 +05:30
Jagan Teki
d45a07aaca arm64: allwinner: h6: Add common orangepi nodes into dtsi
Based on the information from hardware schematics and orangepi
vendor orangepi H6 boards, One Plus and Lite2 shares common nodes
like axp805, uart, mmc0 etc. The common differences between them is
- One Plus, has Ethernet
- Lite2, has Wifi, USB3, CSI port.

So, add common orangepi nodes into sun50i-h6-orangepi.dtsi so-that
it case use on respective orangepi h6 board dts files.

Cc: zhaoyifan <zhao_steven@263.net>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-13 22:13:01 +05:30
Vasily Khoruzhick
b972831c3c sunxi: DT: add support for Pinebook
Pinebook is a laptop produced by Pine64, with USB-connected keyboard,
USB-connected touchpad and an eDP LCD panel connected via a RGB-eDP
bridge from Analogix.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:10:03 +05:30
Vasily Khoruzhick
31a4ac4d79 sun50i: A64: add support for R_I2C controller
Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has
two groups of pinmuxes on PL bank, so it's called R_I2C.

Add support for this I2C controller and the pinmux which doesn't conflict
with RSB.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:09:10 +05:30
Vasily Khoruzhick
20940ef2a3 mmc: sunxi: add support for automatic delay calibration
A64 and H6 support automatic delay calibration and Linux driver uses it
instead of hardcoded delays. Add support for it to u-boot driver.

Fixes eMMC instability on Pinebook

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:07:39 +05:30
Andre Przywara
4f9d34e633 sunxi: A64: Add Pine64-LTS board
The Pine64 LTS is an updated version of the Pine64, copying the
technical updates from the SoPine platform: LPDDR3 DRAM, eMMC socket and
soldered SPI flash chip, even the broken SD card detect pin has been copied.
Consequently this leads to the .dts (copied from the kernel) just including
the SoPine baseboard .dts, and the defconfig being almost identical.
Nevertheless the boards deserves a separate config.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:06:08 +05:30
Andre Przywara
4c974eefbf sunxi: H3/H5: Update .dts files
Update the .dts/.dtsi files from the Linux sunxi/dt64-for-4.20 tree:
commit 679294497be31596e1c9c61507746d72b6b05f26
Author: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz>
Date:   Wed Sep 26 19:48:24 2018 +0000
arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:06:08 +05:30
Andre Przywara
ababb5920e sunxi: A64: Re-add syscon to DT node
The sun50i-a64.dtsi changes introduced in Linux v4.19-rc1 changed the
compatible name for the syscon controller, dropping the generic "syscon"
fallback. Using this new DT node will make the Ethernet driver in every
older kernel (or non-Linux kernels) fail to initialise the MAC device.

To allow booting distribution kernels (from installer images via UEFI,
for instance), re-add the syscon compatible string as a fallback. This
works with both older and newer kernels.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:06:08 +05:30
Andre Przywara
1b39a1834e sunxi: A64: Update .dts/.dtsi files
Update the .dts/.dtsi file from the Linux sunxi/dt64-for-4.20 tree:
commit 679294497be31596e1c9c61507746d72b6b05f26
Author: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz>
Date:   Wed Sep 26 19:48:24 2018 +0000
    arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:06:08 +05:30
Marek Vasut
2f13cf35d2 sunxi: Imply fitImage support
Enable modern fitImage format on sunxi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-13 21:56:57 +05:30
Marcel Ziswiler
43e6f94cbc imx: mkimage: add size check to the u-boot.imx make target
The make macro to check if the binary exceeds the board size limit is
taken straight from the root Makefile.

Without this and e.g. enabled EFI Vybrid fails booting as the regular
size limit check does not take the final u-boot.imx binary size into
account which is bigger due to alignment as well as IMX header stuff.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2018-11-12 11:08:53 +01:00
Christoph Niedermaier
19bbd09825 imx: imx6: perform gpr_init only on suitable cpu types
If the function gpr_init is used in a common MX6 spl
implementation we have to ensure that it is only called for
suitable cpu types, otherwise it breaks hardware parts like
enet1, can1, can2, etc.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.de>
2018-11-08 14:35:40 +01:00
Tom Rini
dd610e616c Fix coverity issues for i.MX8
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Merge tag 'u-boot-imx-20181106' of git://git.denx.de/u-boot-imx

Fix coverity issues for i.MX8
2018-11-06 11:12:00 -05:00
Tom Rini
acf52fb26f Merge git://git.denx.de/u-boot-marvell 2018-11-06 10:37:31 -05:00
Stefan Roese
ae4c38a538 arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGA
The new board version has the 2nd FPGA connected via CS# 0 instead of
2 on SPI bus 1. Change this setup in the DT accordingly. Please note
that this change does still work on the old board version because the
CS signal is not used on this board.

Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-06 13:21:13 +01:00
Stefan Roese
6843db9922 arm: mvebu: armada-xp-theadorable.dts: Add "spi-flash" compatible property
Add the "spi-flash" compatible string so that the generic sf_probe
driver can probe the SPI flash on the theadorable Armada-XP board.

Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-06 13:21:13 +01:00
Stefan Roese
a8483505e8 arm: mvebu: Move PCI(e) MBUS window to end of RAM
With patch 49b23e035d (pci: mvebu: Increase size of PCIe default mapping)
the mapping size for each PCI(e) controller was increased from 32MiB to
128MiB. This leads to problems on boards with multiple PCIe slots / ports
which are unable to map all PCIe ports, e.g. the Armada-XP theadorable:

DRAM:  2 GiB (667 MHz, 64-bit, ECC not enabled)
SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB
Cannot add window '4:f8', conflicts with another window
PCIe unable to add mbus window for mem at f0000000+08000000
Model: Marvell Armada XP theadorable

This patch moves the base address for the PCI(e) memory spaces from
0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now).
This gives move room and flexibility for PCI(e) mappings.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: VlaoMao <vlaomao@gmail.com>
Tested-by: VlaoMao <vlaomao at gmail.com>
2018-11-06 13:21:13 +01:00
Fabio Estevam
78c640fed6 ARM: dts: fsl-imx8qxp-mek: Move regulator outside "simple-bus"
Commit 3c28576bb0 ("arm: dts: imx8qxp: fix build warining")
fixed the dts warning by removing the unnecessary
#address-cells/#size-cells, but the recommendation for regulators is not
to place them under "simple-bus", so move the reg_usdhc2_vmmc regulator
accordingly.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2018-11-06 11:25:55 +01:00
Andy Shevchenko
24109bba6a x86: acpi: Remove redundant Offset (0x00)
New ACPI assembler issues a warning:

board/intel/edison/dsdt.asl.tmp     13:     Offset (0x00),
Remark   2158 -                                       ^ Unnecessary/redundant use of Offset operator

Indeed, in the OperationRegion the offset is 0x00 by default.

Thus, drop unneeded Offset() use as suggested by ACPI assembler.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-06 13:35:06 +08:00
Grygorii Strashko
79d8127168 driver: net: ti: keystone_net: switch to use common mdio lib
Update TI Keystone 2 driver to re-use common mdio lib.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:01 -06:00
Grygorii Strashko
af0cf2178b drivers: net: keystone_net: drop non dm code
Networking support for all TI K2 boards converted to use DM model and
CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop
unused non DM K2 networking code.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:00 -06:00
Grygorii Strashko
ffad5fa0cd driver: net: consolidate ti's code in separate folder
Add drivers/net/ti/ folder and move all TI's code in this folder for better
maintenance.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:41:59 -06:00
Cédric Le Goater
f55f565d71 aspeed: Activate ethernet devices on the ast2500 Eval Board
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:58 -06:00
Cédric Le Goater
6bdccc3025 aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level
This is a large update of the AST2500 SoC DTS file bringing it to the
level of commit 927c2fc2db19 :

    Author:  Joel Stanley <joel@jms.id.au>
    Date:    Sat Jun 2 01:18:53 2018 -0700

         ARM: dts: aspeed: Fix hwrng register address

There are some differences on the compatibility property names. scu,
reset and clock drivers are also different.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:58 -06:00
Tom Rini
5ef76e59c1 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-11-04 08:12:21 -05:00
Daniel Schwierzeck
9630146411 MIPS: make size of relocation table fixed but configurable
Currently the size of the relocation table will be shrunk
to the actual size needed. Although this gives a maximal
space saving, it messes up the _end symbol. This breaks
features like appended DTBs because the _end symbol doesn't
point to the real end of the U-Boot binary.

Remove the size shrinking and make the size of the relocation
table fixed but configurable. This follows the Linux approach
and the user can adjust the size to his needs.

Also rename the relocation table section from .rel to .data.reloc
to follow the Linux approach and to avoid ambiguities with the
.rel.* sections added by the linker.

Reported-by: Lars Povlsen <lars.povlsen@microsemi.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-02 22:39:07 +01:00
Marek Vasut
e5cb6bd9a2 ARM: rmobile: Generate fitting mem_map on Gen3
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire
64bit DRAM space as cachable. On CortexA57, this might result in odd
side effects, where the CPU tries to prefetch from those areas and if
there is no DRAM backing them, CPU bus hang can happen.

This patch fixes it by generating the mem_map structure based on the
actual memory layout obtained from the DT, thus not marking areas
without any DRAM behind them as cachable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Fixes: c1ec347638 ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3")
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-11-02 15:57:13 +01:00
Alexey Brodkin
adc9b09a23 emdk->emsdp: Rename board
Real marketing name of the board was recently updated so
to accommodate that change renaming the board and all
related to it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-11-01 23:04:05 +03:00
Tom Rini
fdaccfeb5e Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-10-31 17:15:55 -04:00
Jun Nie
7bb0d212f2 sunxi: add support for Banana Pi M2 Zero board
Banana Pi M2 Zero is a board by Sinovoip with Allwinner H2+ SoC, 16-bit
512MiB DDR3 memory, a MicroSD slot, two MicroUSB ports (one OTG and one
powering-only) and a miniHDMI port.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
[jagan: Fixed board MAINTAINERS file]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-10-31 12:13:02 +05:30
Simon Goldschmidt
f48db4ede0 arm: socfpga: imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
Using imply for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION instead of
select ensures we can build without partition support (used to build
a network boot only version of SPL and U-Boot).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-10-31 01:41:10 +01:00
Bin Meng
db148f2a69 powerpc: t1040: Correct RCW EC2 settings
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2
settings.

- The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should
  be 0x04000000 (value of 1 in RCW bit [420:421])
- Value of 2/3 are reserved in RCW bit [420:421], hence there is no
  macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 13:19:43 -07:00
Bin Meng
c00d0012f5 powerpc: t1040: Correct RCW MAC2_GMII_SEL value
Per T1040RM (Rev. 1, 08/2015), the value of
FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong
and should be 0x00000080 (bit 440 in the RCW).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 13:13:33 -07:00
Chris Packham
4eaf7f525a fsl/usb: Workaround for USB erratum-A005275
Workaround makes FS as default mode on all affected socs.

Add support to check erratum-A005275 validity for an soc. This info is
required to determine whether a given soc is affected by this erratum.
Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used
to enable workaround for the errata

Force FS mode as default by:
        - making EPS as FS
        - setting PFSC bit to disable HS chirping

This workaround can be disabled by mentioning "no_erratum_a005275" in
hwconfig string

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 13:13:05 -07:00
Tom Rini
2f07a9a6d1 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-10-29 11:21:00 -04:00
Andre Przywara
5776610e9e sunxi: store DRAM size in SPL header
At the moment we rely on the infamous get_ram_size() function to learn
the actual DRAM size in U-Boot proper. This function has two issues:
1) It only works if the DRAM size is a power of two. We start to see
boards which have 3GB of (usable) DRAM, so this does not fit anymore.
2) As U-Boot has no notion of reserved memory so far, it will happily
ride through the DRAM, possibly stepping on secure-only memory. This
could be a region of DRAM reserved for OP-TEE or some other secure
payload, for instance. It will most likely crash in that case.

As the SPL DRAM init routine has very accurate knowledge of the actual
DRAM size, lets propagate this wisdom to U-Boot proper.
We re-purpose a currently reserved word in our SPL header for that.
The SPL itself stores the detected DRAM size there, and bumps the SPL
header version number in that case. U-Boot proper checks for a valid
SPL header and a high enough version number, then uses the DRAM size
from there. If the SPL header field is not sufficient, we fall back to
the old DRAM scanning routine.

Part of the DRAM might be present and probed by SPL, but not accessible
by the CPU. They're restricted in the main U-Boot binary, when accessing
the DRAM size from SPL header.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Icenowy Zheng
f8aa3f8d84 sunxi: add Kconfig option for the maximum accessible DRAM
Allwinner 64-bit SoCs can use 4GiB DRAM chip, however their memory map
has only allocated 3GiB for DRAM, so only 3GiB of the DRAM is
accessible.

Add a Kconfig option for the maximum accessible DRAM.

For A80 it should be a much higher value (8GiB), but as I have no A80
device to test and originally U-Boot only supports 2GiB DRAM on A80, it
currently still falls under the 2GiB situation.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Icenowy Zheng
7009134c99 sunxi: map DRAM part with 3G size
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of
external DRAM, however the size of DRAM part in the MMU translation
table is still 2GiB.

Change the size of DRAM part in MMU table to 3GiB.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Andre Przywara
55d481d201 sunxi: Extend SPL header versioning
On Allwinner SoCs we use some free bytes at the beginning of the SPL image
to store various information. We have a version byte to allow updates,
but changing this always requires all tools to be updated as well.

Introduce the concept of semantic versioning [1] to the SPL header:
The major part of the version number only changes on incompatible
updates, a minor number bump indicates backward compatibility.
This patch just documents the major/minor split, adds some comments
to the header file and uses the versioning information for the existing
users.

[1] https://semver.org

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Icenowy Zheng
c6c2c85e4b sunxi: disable Pine A64 model detection code on other boards
The Pine A64 Plus/non-Plus model detection code is now built on all
64-bit ARM SoCs, even if the code cannot be triggered when H5/H6 is in
use.

Disable them when the board is Pine A64 by adding a Kconfig option that
is only selected on Pine A64.

On GCC 7.3.1 this makes the size of the function reduces 184 bytes, and
saves a 104 byte strstr() function, then makes SPL on H6 succeed to
build.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:07 +05:30
Bin Meng
3d2be8003c x86: Fix car_uninit weak symbol definition
Since commit 80df194f01 ("x86: detect unsupported relocation types"),
an error message is seen on QEMU x86 target during boot:

do_elf_reloc_fixups32: unsupported relocation type 0x1 at fff841f0, offset = 0xfff00087
do_elf_reloc_fixups32: unsupported relocation type 0x2 at fff841f8, offset = 0xfff00091

Check offset 0xfff00087 and 0xfff00091 in the u-boot ELF image,

fff00087  000df401 R_386_32          00000000   car_uninit
fff00091  000df402 R_386_PC32        00000000   car_uninit

we see R_386_32 and R_386_PC32 relocation type is generated for
symbol car_uninit, which is declared as a weak symbol in start.S.

However the actual weak symbol implementation ends up nowhere. As
we can see below, it's *UND*.

$ objdump -t u-boot | grep car_uninit
00000000  w      *UND*  00000000 car_uninit

With this fix, it is normal now.

$ objdump -t u-boot | grep car_uninit
fff00094  w    F .text.start    00000001 car_uninit

Reported-by: Hannes Schmelzer <hannes@schmelzer.or.at>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
2018-10-28 21:02:15 +08:00
Stefan Roese
7d2a0534a6 x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / region
To allow bigger 64 bit prefetchable PCI regions in Linux, this patch
changes the base address and range of the ACPI area passed to Linux.
BayTrail can only physically access 36 bit of PCI address space. So
just chaning the range without changing the base address won't work
here, as 0xf.ffff.ffff is already the maximum address.

With this patch, a maximum of 16 GiB of local DDR is supported. This
should be enough for all BayTrail boards though.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-28 21:02:15 +08:00
Tom Rini
cf033e04da Merged imx8 architecture, fix build for imx8 + warnings
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Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imx

Merged imx8 architecture, fix build for imx8 + warnings
2018-10-25 10:16:21 -04:00
Peng Fan
3c28576bb0 arm: dts: imx8qxp: fix build warining
Fix below build warning.

arch/arm/dts/fsl-imx8qxp-mek.dtb: Warning (avoid_unnecessary_addr_size):
/regulators: unnecessary #address-cells/#size-cells without "ranges"
or child "reg" property

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-10-25 11:48:13 +02:00
Peng Fan
d79611598f imx: mkimage: avoid stop CI when required files not exists
Introduce a new script to check whether file exists and
use that check in Makefile to avoid break CI system.

The script return 1 when the required files not exists, return 0
when files exists. The script will ignore check to u-boot-dtb.bin,
because if there is something wrong to generate u-boot-dtb.bin,
there must be some code error.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-10-25 11:47:53 +02:00
Priit Laes
297963f5b5 sunxi: Fix typos of spelling Allwinner
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-24 22:02:15 +05:30
Tom Rini
c95c666d01 Merge git://git.denx.de/u-boot-x86 2018-10-22 13:56:10 -04:00
Cédric Le Goater
e1a8dfde5a watchdog: aspeed: restore default value of reset_mask
This is required for the current Linux kernel to reboot. It should also
probably be fixed in Linux.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-22 09:18:49 -04:00
Rui Miguel Silva
be277c3a89 imx: mx7: avoid some initialization if low level is skipped
We can have the case where u-boot is launched after some other low level
enabler, like for example when u-boot runs after arm-trusted-firmware
and/or optee. So, because of that we may need to jump the initialization of
some IP blocks even because we may no longer have the permission for that.

So, if the config option to skip low level init is set disable also timer,
board and csu initialization.

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: u-boot@lists.denx.de
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-10-22 14:37:28 +02:00
Peng Fan
0e5c8ce734 arm: imx: include imx8image support
When building i.MX8/8X board, use imx8image type.

`-e $(CONFIG_SYS_TEXT_BASE)` is not needed, but
no harm to keep it for i.MX8/8X

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-10-22 13:01:27 +02:00
Peng Fan
d0dd73974c imx: add i.MX8QXP MEK board support
Add i.MX8QXP MEK board support
Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver.
Added README file.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-10-22 13:00:09 +02:00
Peng Fan
f180f4a482 arm: dts: introduce dtsi for i.MX8QXP
Introduce dtsi for i.MX8QXP, since there is other variants i.MX8DX(P),
so add them there, because i.MX8QXP includes the dtsi of them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2018-10-22 13:00:09 +02:00
Peng Fan
d526f340f7 power: Add power domain driver for i.MX8
Add the power domain DM driver for i.MX8, that it depends on the DTB
power domain trees to generate the power domain provider devices. Users
need to add power domain trees with property "compatible = "nxp,imx8-pd";"

When power on a PD device, the driver will power on its ancestor PD
devices in power domain tree.

When power off a PD device, the driver will check its child PD devices
first. Only if all child PD devices are off, then power off the current PD
device. Then the driver checks sibling PD devices. If sibling PD devices
are off, then it will power off parent PD device.

There is no counter maintained in this driver, but a state to hold current
on/off state. So the request and free functions are empty.

The power domain implementation in i.MX8 DTB set the "#power-domain-cells"
to 0, so there is no ID binding with each PD device. We don't use "id"
variable in struct power_domain. At the same time, we have to set of_xlate
to empty to bypass standard of_xlate in uclass driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
8b2a31f133 gpio: mxc_gpio: add support for i.MX8
Add i.MX8 support, there are 8 GPIO banks.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
2d58296f3e imx8: add dummy clock
This driver is mostly used to avoid build errors.
We use uclass clk driver for clk related operations.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
abeebc19db imx8: add iomux configuration api
Add iomux configuration api.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Anatolij Gustschin
2fdb1a1df9 imx8: cpu: add uclass based CPU driver
print_cpuinfo() in board init code requires uclass CPU driver,
add it to be able to display CPU info when CONFIG_DISPLAY_CPUINFO
option is enabled. CPU node in DT will have to include 'clocks'
and 'u-boot,dm-pre-reloc' properties for generic print_cpuinfo()
to work as expected. The driver outputs info for i.MX8QXP Rev A
and Rev B CPUs.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-10-22 12:59:01 +02:00
Anatolij Gustschin
70b4b49b91 imx8: cpu: add function for reading FEC MAC from fuse
FEC driver requires imx_get_mac_from_fuse(). Add it in preparation
for ENETx support.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-10-22 12:59:01 +02:00
Peng Fan
1ef20a3d81 imx8: add arch_cpu_init arch_cpu_init_dm
Add arch_cpu_init(_dm) mainly to open the channel between ACore and SCU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
930b595291 imx8: add mmu and dram related functions
Add mmu memmap, some memory regions are reserved by M4, Arm Trusted
Firmware, so need to get memreg using SCFW API and setup the memmap.

Add dram_init, dram_init_banksize, get_effective_memsize functions,
according to the memreg.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
c1aae21d89 imx8: implement mmc_get_env_dev
Implement mmc_get_env_dev for i.MX8.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
8aa1505b59 imx8: add boot device detection
Add get_boot_device to detect boot device.
Add print_bootinfo to print the boot device info.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
60d33fcd19 imx8: add basic cpu support
Add basic cpu support, including cpu revision, cpu type,
cpu core detection.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
fa64d8429b armv8: add cpu core helper functions
Add helper functions to identify different armv8 variants.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
5710a48afc imx: add i.MX8 cpu type
Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
0468be6e7c imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined
Include i.MX8QXP pin header when CONFIG_IMX8QXP defined,
if no SoC macro defined, report error.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
8c51872248 imx8: add imx-regs header file
Add imx-regs header file to include the register base definition

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
707effeafd imx: boot_mode: Add FLEXSPI boot entry
i.MX8 support FLEXSPI boot support. So add FLEXSPI boot entry.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
ad9d40acb4 misc: imx8: add scfw api impementation
Add clk/misc/pad/pm/rm scfw api implementaion for different
drivers to invoke. The low level code is using misc_call
to invoke imx8_scu driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
60b9de4f70 arm: global_data: add scu_dev for i.MX8
Add scu_dev for i.MX8, this will be used as a handle
to communite with SCU from A35.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
a6bba0bd00 arm: build mach-imx for i.MX8
Build mach-imx for i.MX8

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
b2b8b9be2f imx: add Kconfig entry for i.MX8QXP
Add Kconfig entry for i.MX8QXP

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Peng Fan
bf494d7e9b imx8: add scfw macro definition
Add SCFW macro definition.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Bin Meng
a39f0554f4 x86: quark: Specify X86_TSC_TIMER_EARLY_FREQ
Specify X86_TSC_TIMER_EARLY_FREQ for Quark SoC so that TSC as
the early timer can be supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-22 17:51:45 +08:00
Bin Meng
49d5ff439c x86: Fix the mystery of printch() during 64-bit boot
At present in arch_setup_gd() it calls printch(' ') at the end which
has been a mystery for a long time as without such call the 64-bit
U-Boot just does not boot at all.

In fact this is due to the bug that board_init_f() was called with
boot_flags not being set. Hence whatever value being there in the
rdi register becomes the boot_flags if without such magic call.
With a printch(' ') call the rdi register is initialized as 0x20
and this value seems to be sane enough for the whole boot process.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-10-22 17:51:45 +08:00
Heinrich Schuchardt
2c78a79ec7 x86: put global data pointer into the .data section
On x86_64 the field global_data_ptr is assigned before relocation. As
sections for uninitialized global data (.bss) overlap with the relocation
sections (.rela) this destroys the relocation table and leads to spurious
errors.

Initialization forces the global_data_ptr into a section for initialized
global data (.data) which cannot overlap any .rela section.

Fixes: a160092a61 ("x86: Support global_data on x86_64")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-22 17:51:45 +08:00
Heinrich Schuchardt
80df194f01 x86: detect unsupported relocation types
Currently we support only relocations of type ELF64_R_TYPE or ELF32_R_TYPE.
We should be warned if other relocation types appear in the relocation
sections.

This type of message has helped to identify code overwriting a relocation
section before relocation and incorrect parsing of relocation tables.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-22 17:51:45 +08:00
Bin Meng
dd4611dea4 x86: Ensure no instruction sets of MMX/SSE are generated in 64-bit build
With the '-march=core2' fix, it seems that we have some luck that
the 64-bit U-Boot boots again. However if we examine the disassembly
codes there are still SSE instructions elsewhere which means passing
cpu type to GCC is not enough to prevent it from generating these
instructions. A simple test case is doing a 'bootefi selftest' from
the U-Boot shell and it leads to a reset too.

The 'bootefi selftest' reset is even seen with the image created by
the relative older GCC 5.4.0, the one shipped by Ubuntu 16.04.

The reset actually originates from undefined instruction exception
caused by these SSE instructions. To keep U-Boot as a bootloader as
simple as possible, we don't want to handle such advanced SIMD stuff.
To make sure no MMX/SSE instruction sets are generated, tell GCC not
to do this. Note AVX is out of the question as CORE2 is old enough
to support AVX yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-22 17:51:45 +08:00
Bin Meng
a139cc1865 x86: Specify -march=core2 to build 64-bit U-Boot proper
With newer kernel.org GCC (7.3.0 or 8.1.0), the u-boot.rom image
built for qemu-x86_64 target does not boot. It keeps resetting
soon after the 32-bit SPL jumps to 64-bit proper. Debugging shows
that the reset happens inside env_callback_init().

000000000113dd85 <env_callback_init>:
 113dd85:       41 54                   push   %r12
 113dd87:       55                      push   %rbp
 113dd88:       31 c0                   xor    %eax,%eax
 113dd8a:       53                      push   %rbx
 113dd8b:       0f 57 c0                xorps  %xmm0,%xmm0

Executing "xorps %xmm0,%xmm0" causes CPU to immediately reset.
However older GCC like 5.4.0 (the one shipped by Ubuntu 16.04)
does not generate such instructions that utilizes SSE for this
function - env_callback_init() and U-Boot boots without any issue.
Explicitly specifying -march=core2 for newer GCC allows U-Boot
proper to boot again. Examine assembly codes of env_callback_init
and there is no SSE instruction in that function hence U-Boot
continues to boot.

core2 seems to be the oldest arch in GCC that supports 64-bit.
Like 32-bit U-Boot build we use -march=i386 which is the most
conservative cpu type so that the image can run on any x86
processor, let's do the same for the 64-bit U-Boot build.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-22 17:51:45 +08:00
Hannes Schmelzer
c74e3295ae x86/bootm: fix error handling in boot_prep_linux(...)
Once we get a zero pointer from load_zimage(...) we must bunch out
instead of continue boot.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-22 17:51:45 +08:00
Marek Vasut
b59349a0c0 test: Add PCI device entry without compat string and with DT node
Add PCI entry without compatible string and with a DT node only with
reg = <...> property into the DT. This is needed for the tests to
verify whether such a setup creates an U-Boot PCI device with the
DT node associated with it in udevice.node.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-20 15:23:38 -04:00
Adam Ford
2fe88d4522 Convert CONFIG_FLASH_CFI_DRIVER et al to Kconfig
This converts the following to Kconfig:
   CONFIG_FLASH_CFI_DRIVER
   CONFIG_SYS_FLASH_USE_BUFFER_WRITE
   CONFIG_FLASH_CFI_MTD
   CONFIG_SYS_FLASH_PROTECTION
   CONFIG_SYS_FLASH_CFI

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Re-migrate]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-19 19:19:50 -04:00
Adam Ford
876ddb558d ARM: mach-omap2: Kconfig: Make SYS_MPUCLK dependent on AM33XX
This value is unly used in arch/arm/mach-omap2/am33xx/
clock_am33xx.c, so let's make it dependent on AM33XX since
that is the only way this file gets compiled into the code
according to the Makefile.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Fix symbol name]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-19 14:16:32 -04:00
Vladimir Zapolskiy
72f6d6b7ea arm: lpc32xx: remove phantom CONFIG_LPC32XX_SDRAM_ config option
The option has never existed and config whitelist script accumulates
it from a comment block, wipe it out from the source code.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2018-10-19 12:56:58 -04:00
Vladimir Zapolskiy
ee54dfea45 arm: lpc32xx: add CONFIG_ARCH_LPC32XX build option
The explicit arch specific build symbol allows to group supported
boards, generalize common config options and it will serve as
a dependency for platform only drivers.

Two related board defconfigs are resynced after the change.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2018-10-19 12:56:58 -04:00
Marek Vasut
bd6debbc94 ARM: rmobile: Drop PRR syscon driver
The PRR syscon driver is available too late for Multi DTB build
of U-Boot. Replace it with simple check whether a platform is
Gen3 or not and produce an address of the PRR.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-10-18 20:38:27 +02:00
Marek Vasut
4cc93fc281 ARM: dts: rmobile: Build -u-boot variants of DTs
Build the -u-boot variants of the device trees so they can be included
in Multi-DTB fitImage, which in turn allows us to build single U-Boot
image for multiple boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-10-18 20:38:27 +02:00
Hiroyuki Yokoyama
2a1eade825 ARM: dts: rmobile: r8a77990: Add USB2.0(EHCI) DT nodes on Ebisu
Add device tree nodes for USB2.0(EHCI) on R-Car E3 Ebisu board.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
2018-10-18 19:07:47 +02:00
Hiroyuki Yokoyama
feaf301f78 ARM: rmobile: Enable cache command on Gen3
This patch enables the cache command, mostly for convenience of testing.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-10-18 19:07:46 +02:00
Tom Rini
e3beca3a2f Patch queue for efi - 2018-10-17
A few bug fixes for the 2018.11 release:
 
   - Fix block seeking on 32bit
   - Fix execution with DEBUG set
   - Fix a few Coverity found bugs
   - Fix warnings
 
 Heinrich Schuchardt (13):
       efi_loader: fix relocation on x86_64
       efi_loader: correct signature of GetPosition, SetPosition
       efi_loader: execute efi_save_gd() first
       efi_loader: efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, ...)
       efi_loader: error handling in read_console()
       efi_loader: return type efi_console_register()
       efi_loader: superfluous statement in is_dir()
       efi_loader: memory leak in efi_set_variable()
       efi_loader: remove lcd.h from efi_net.c
       arm: do not include efi_loader.h twice
       efi_loader: fix typo in efi_boottime.c
       efi_selftest: creating new handle in controller test
       efi_loader: efi_dp_get_next_instance() superfluous statement
 
 Tom Rini (2):
       efi_loader: Fix warning in efi_load_image()
       fs: fat: Fix warning in normalize_longname()
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Merge tag 'signed-efi-2018.11' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-10-17

A few bug fixes for the 2018.11 release:

  - Fix block seeking on 32bit
  - Fix execution with DEBUG set
  - Fix a few Coverity found bugs
  - Fix warnings

Heinrich Schuchardt (13):
      efi_loader: fix relocation on x86_64
      efi_loader: correct signature of GetPosition, SetPosition
      efi_loader: execute efi_save_gd() first
      efi_loader: efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, ...)
      efi_loader: error handling in read_console()
      efi_loader: return type efi_console_register()
      efi_loader: superfluous statement in is_dir()
      efi_loader: memory leak in efi_set_variable()
      efi_loader: remove lcd.h from efi_net.c
      arm: do not include efi_loader.h twice
      efi_loader: fix typo in efi_boottime.c
      efi_selftest: creating new handle in controller test
      efi_loader: efi_dp_get_next_instance() superfluous statement

Tom Rini (2):
      efi_loader: Fix warning in efi_load_image()
      fs: fat: Fix warning in normalize_longname()
2018-10-17 07:20:52 -04:00
Michal Simek
22270ca036 arm64: zynqmp: Enable MP by default via Kconfig
Simplify defconfig for ZynqMP but keep option not to enable it for mini
targets.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Siva Durga Prasad Paladugu
5860bc16b9 arm64: zynqmp: Add new command for TCM initialization
This patch adds new zynqmp command "zynqmp tcminit mode" to
initialize TCM. TCM needs to be initialized before accessing
to avoid ECC errors. This new command helps to perform
the same. It also makes tcm_init() as global and uses it for
doing the TCM initialization.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Siva Durga Prasad Paladugu
12ad2994a5 arm64: zynqmp: Move TCM initialization to a separate routine
This patch moves TCM initialization to a separate routine to
make it modular and can be reused if required. It also prints
warning message now as it writes to TCM.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Michal Simek
ddccf5ef90 arm64: versal: Add Xilinx Versal Virtual QEMU board
Virtual QEMU board is generating DTB self and putting it to
VERSAL_QEMU_DTB_ADDR address.
Board is using CONFIG_OF_BOARD which ensures that u-boot is aligned with
board created by QEMU.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Michal Simek
ec48b6c991 arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:21 +02:00
Heinrich Schuchardt
b417d475b2 arm: do not include efi_loader.h twice
We should not include the same include twice.

Fixes: 99b8db7291 ("arm: print information about loaded UEFI images")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-10-16 16:41:01 +02:00
Michal Simek
e6149576e8 arm64: gic: Do gicv3 secure initialization based on EL level
Do gic cpu initialization based on EL level which u-boot enters.
U-Boot can't access EL3 regs when runs in EL2/EL1, etc.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 14:58:46 +02:00
Michal Simek
e7f327fe4d arm: zynq: Add efuse node for Zynq-7000S devices
Add access to efuse for Zynq-7000S device detection.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 14:58:45 +02:00
Michal Simek
6bfe3fffac arm: zynq: Add support for DLC20 board
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).

Boards have mix of Winbond/ST QSPIs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 14:58:45 +02:00
Marek Vasut
39cb4f3c25 arm: mx5: Add M53Menlo board
Add Menlosystems M53 board, based on the M53 SoM.
This board has Ethernet, USB host, USB gadget, UART and LCD on it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-16 10:34:19 +02:00
Marek Vasut
ed85f77190 arm: mx5: Add LDB clock config code
Add code to configure PLL4, from which the LDB clock are directly
derived.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-16 10:34:02 +02:00
Marek Vasut
0b6b8a3a19 arm: imx: mx5: Make videoskip available on MX5
The board_video_skip() implementation in imx-common/video.c works
on i.MX5x as well, so loosen the SoC filter in Makefile to make it
available.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-16 10:33:26 +02:00
Tom Rini
6e7a186dc5 Merge tag 'arc-more-updates-for-2018.11-rc2-2' of git://git.denx.de/u-boot-arc
More fixes and improvements for ARC here:

Fixes (this time included for real):
 * Take care of global uninitialized variables
   They used to be put right after .bss section and were never
   zeroed as they should be. Now merged with normal .bss

Improvements:
 * Print more verbose CPU info for boards built on real silicon
 * Add support for SD-card detection on all ARC boards
 * Quite a few fixes for IoT DK
   - Support reset by command
   - Print of CPU freq on boot
   - Link for eFlash etc
2018-10-15 07:20:07 -04:00
Alexey Brodkin
6e63314f43 ARC: Don't use COMMON section for global not-initialized variables
By default GCC puts global non-initialized variables in COMMON section.
And we used to ignore existence of COMMON section in our linker
scripts though smart LD silently appended it right after .bss.

And the problem here is variables from COMMON section even though
require zeroing in run-time were not zeroed as they were placed
right after __bss_end symbol.

It was a pure luck we never faced serious problem due to this,
but now it is fixed.

Now as for some other architectures we'll just force GCC to put
those global variables in normal .bss section.

This solution is much nicer than adding COMMON section to each and
every linker script.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-15 13:35:17 +03:00
Tom Rini
19ca29f3ff Merge git://git.denx.de/u-boot-sunxi
[trini: Convert da850evm_nand defconfig now to to SPL_DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-12 15:21:24 -04:00
Alexey Brodkin
ba9f56f3d4 ARC: make generic print_cpuinfo() weak
This allows board to override print_cpuinfo() because
they might know better which ARChitect template was used.
This way we may not only derive base architecture type and
version but more meaningful things like "ARC EM7D" instead of
simple "ARC EM", "ARC HS36" instead of "ARC HS".

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-12 15:14:40 +03:00
Tom Rini
0223462b37 Merge branch 'master' of git://git.denx.de/u-boot-net 2018-10-11 15:28:32 -04:00
Tom Rini
3d5ced9e22 Test improvements to tidy up output and drop duplicate tests
Sandbox SPL/TPL support
 Various dm-related improvements
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Merge tag 'dm-9oct18' of git://git.denx.de/u-boot-dm

Test improvements to tidy up output and drop duplicate tests
Sandbox SPL/TPL support
Various dm-related improvements
2018-10-10 13:35:17 -04:00
Tom Rini
98068b3be5 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-10-10 13:35:14 -04:00
Patrick Delaunay
606f3a74e6 arm: remove duplicated prototypes in u-boot.arm.h
Remove the function prototypes duplicated between u-boot.arm.h
and init.h/common.h

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:10 -04:00
Patrick Delaunay
6180ea7e66 arm: remove prototype for get_timer_masked
The interruption support had be removed for ARM architecture and
the function get_timer_masked() is no more used except in some
the timer.c files.

This patch clean each timer.c which implement this function and
remove the associated prototype in u-boot-arm.h

For timer.c, I don't verify if the weak version of get_timer
(in lib/time.c) can be used

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:09 -04:00
Patrick Delaunay
aa33fe8695 arm: remove prototype for udelay_masked
The interruption support had be removed for ARM architecture and
the function udelay_masked() is no more used except in some timer.c
files  and have the same content than udelay() or __udelay().

This patch update each timer.c implementing this function and
remove the associated prototype in u-boot-arm.h.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:09 -04:00
Patrick Delaunay
aad5b4a351 arm: remove prototype for reset_timer_masked
Remove prototype for function only used in one file

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:09 -04:00
Patrick Delaunay
1c8e9fae16 arm: remove prototype for arch_interrupt_init
Remove prototype for no more existing function

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:09 -04:00
Andrew F. Davis
81089a5430 arm: K3: am654: Add support for getting boot mode
Read the boot mode register to find the boot mode. Only use eMMC boot0
mode when the mode is eMMC boot (called BOOT_DEVICE_MMC1 currently due
to current conflating of boot mode and boot device), and not iff the
boot device is MMC port 0.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-10-10 13:35:08 -04:00
Andrew F. Davis
b5700efbc8 arm: K3: am654: Choose MMC boot device based on boot port
For most devices the boot mode maps directly to the boot
device. For MMC this is not the case as we have two MMC
boot modes and two MMC boot devices (ports). Check the
boot port to determine which MMC device was our boot
device. Make this change for both primary and secondary
boot modes.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-10-10 13:35:08 -04:00
Keerthy
0f3cf2b3e5 gpio: da8xx: Push generic defines of gpio.h out of mach-davinci
Push generic defines of gpio.h out of mach-davinci to drivers/gpio
now that non-davinci architectures are beginning to use this IP.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Fix calimain build]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-10 13:35:03 -04:00
Loic Devulder
8afd4ea5b9 ARM: meson: Add Khadas VIM2 board support
This adds platform code for the Khadas VIM2 board based on a
Meson GXM (S912) SoC with the Meson GXM configuration.

This initial submission supports UART, MMC/SDCard and Ethernet.
USB is partially supported.

All the code is from Neil Armstrong! I just rebased the code, do
some cleanup and tested on my board.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Loic Devulder <ldevulder@suse.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2018-10-10 13:32:40 -04:00
Loic Devulder
2058b7395e ARM: meson: Add Khadas VIM2 board DT
This adds Device Tree for the Khadas VIM2 board.

The meson-gxm-khadas-vim2.dts is synchronized from Linux 4.18.10.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Loic Devulder <ldevulder@suse.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2018-10-10 13:32:40 -04:00
Patrice Chotard
1c547bf732 ARM: dts: stm32mp1: Add usbotg_hs regulator for stm32mp157c-ev1
Add usbotg_hs regulator to allow to use the USB mass-storage
feature on OTG usb port.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-10-10 13:32:40 -04:00
Joe Hershberger
72ff004258 test: eth: Add a test for the target being pinged
The target will respond to pings while doing other network handling.
Make sure that the response happens and is correct.

This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:29:00 -05:00
Joe Hershberger
45988dae4c test: eth: Add a test for ARP requests
This tests that ARP requests made to this target's IP address are
responded-to by the target when it is doing other networking operations.

This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:29:00 -05:00
Joe Hershberger
9cbe5972c3 net: sandbox: Add a priv ptr for tests to use
Tests need to be able to pass their "unit test state" to the handlers
where asserts are evaluated. Add a function that allows the tests to set
this private data on the sandbox eth device.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:59 -05:00
Joe Hershberger
c67a420781 net: sandbox: Allow fake eth to handle more than 1 packet response
Use up to the max allocated receive buffers so as to be able to test
more complex situations.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:58 -05:00
Joe Hershberger
76a503439e net: sandbox: Share the priv structure with tests
If tests want to implement tx handlers, they will likely need access to
the details in the priv structure.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:57 -05:00
Joe Hershberger
c7eb733d60 net: sandbox: Make the fake eth driver response configurable
Make the send handler registerable so tests can check for different
things.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:57 -05:00
Joe Hershberger
e95bb16110 net: sandbox: Refactor sandbox send function
Make the behavior of the send function reusable.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:56 -05:00
Icenowy Zheng
90de3969be sunxi: fix DRAM gate/reset sequence of H6
Currently the DRAM bus gate and reset is changed at the same time in
H6 DRAM initialization code, which disobeys the user manual's
programming guide.

Fix the sequence by follow the sequence suggested by the user manual
(ungate the bus clock after release the reset signal).

By some experiments it seems to fix the DRAM size detection failure that
rarely happens.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2018-10-10 12:04:07 +05:30
Sébastien Szymanski
2f90c62c8a ARM: opos6ul: make the board boot again
Commit 9faa43c4b5 ("ARM: dts: i.MX6UL: U-Boot specific dts for u-boot,
dm-spl") removes the u-boot,dm-spl properties from the imx6ul.dtsi file
and breaks the OPOS6UL board.
Add the u-boot,dm-spl properties into *-u-boot.dts files to make the
board boot again.

Fixes: commit 9faa43c4b5 ("ARM: dts: i.MX6UL: U-Boot specific dts for u-boot, dm-spl")
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-10-09 18:36:03 +02:00
Marcel Ziswiler
2cea8d74dc imx: mx7: fix potential overflow in imx_ddr_size()
The imx_ddr_size() function may overflow as it is possible to kind of
over provision the DDR controller. Fix this by capping it to 2 GB which
is the maximum allowed size as per reference manual.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-10-09 18:32:47 +02:00
Marek Vasut
ae400fde75 ARM: dts: rmobile: Reinstate missing CPLD on ULCB
The CPLD is used to reset the ULCB and it was removed
during DT sync with Linux 4.17. Reinstate it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-09 17:21:44 +02:00
Simon Glass
5d9a88f44a test: panel: Add a test for the panel uclass
At present this uclass has no tests. Add a simple one which checks the PWM
configuration, regulator and GPIO.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09 04:40:27 -06:00
Simon Glass
590cee8315 x86: Update mtrr functions to allow leaving cache alone
At present the mtrr functions disable the cache before making changes and
enable it again afterwards. This is fine in U-Boot, but does not work if
running in CAR (such as we are in SPL).

Update the functions so that the caller can request that caches be left
alone.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-09 04:40:27 -06:00
Simon Glass
e6c5c94a79 dm: core: Update ofnode to read binman-style flash entry
At present ofnode_read_fmap_entry() reads a flash map entry in a format
which is not supported by binman. To allow use to use binman-format
descriptions, update this function.

Also add a simple test.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09 04:40:27 -06:00
Simon Glass
4af3e9ad8a sandbox: Restore blocking I/O on exit
At present sandbox sets non-blocking I/O as soon as any input is read
from the terminal. However it does not restore the previous state on
exit. Fix this and drop the old os_read_no_block() function.

This means that we always enable blocking I/O in sandbox (if input is a
terminal) whereas previously it would only happen on the first call to
tstc() or getc(). However, the difference is likely not important.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09 04:40:27 -06:00
Simon Glass
66613f5dd2 dm: spi: Clean up detection of sandbox SPI emulator
Now that we don't have to deal with the command-line flag we can simplify
the code for detecting the emulator. Remove the lookup based on the SPI
specification, relying just on the device tree to locate the emulator.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09 04:40:27 -06:00
Simon Glass
1c5a81d803 sandbox: Remove the old memory file later
When debugging sandbox it is sometimes annoying that the memory file is
deleted early on. If sandbox later crashes or we quit (using the
debugger), it is not possible to run it again with the same state since
the memory file is gone.

Remove the old memory file when sandbox exits, instead. Also add debugging
showing the memory filename.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09 04:40:26 -06:00
Simon Glass
2b1dc29a12 sandbox: Add a flag to set the default log level
It is useful to be able to set the default log level from the command line
when running sandbox. Add a new -L command-line flag for this. The log
level is set using the enum log_level_t in log.h. At present a number must
be specified, e.g. -L7 for debug.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09 04:40:26 -06:00
Simon Glass
69bc15d5ff sandbox: Support booting from TPL to SPL
At present we support booting from SPL to U-Boot proper. Add support for
the previous stage too, so sandbox can be started with TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09 04:40:26 -06:00
Simon Glass
056a5cea31 sandbox: Add a way to write data to the host filesystem
For debugging it is sometimes useful to write out data for inspection
using an external tool. Add a function which can write this data to a
given file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09 04:40:26 -06:00
Simon Glass
50b288aca3 sandbox: Support file truncation with os_open()
At present files are not truncated on writing. This is a useful feature.
Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-09 04:40:26 -06:00
Loic Devulder
c45414b542 ARM: meson: Extend mem_map to support 3GiB of RAM
The current mem_map definition for Meson SoCs has support for up
to 2GiB of RAM. According to S905, S905X, S912 and S805X datasheets
the DDR region is set from 0x00000000 to 0xBFFFFFFF, so mem_map's
definition should be changed accordingly.

It is also needed to be able to boot Khadas VIM2 board with S912
SoC.

Signed-off-by: Loic Devulder <ldevulder@suse.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2018-10-08 14:45:02 -04:00
Simon Glass
9f8037ea9c sandbox: Unprotect DATA regions in bus tests
On my Ubuntu 18.04.1 machine two driver-model bus tests have started
failing recently. The problem appears to be that the DATA region of the
executable is protected. This does not seem correct, but perhaps there
is a reason.

To work around it, unprotect the regions in these tests before accessing
them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-10-08 07:34:34 -06:00
Jens Wiklander
0a60a81ba3 Kconfig: sandbox: enable cmd_avb and dependencies
Enables cmd_avb and its dependencies need to run the AVB tests.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
[trini: Disable for sandbox_noblk]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-07 13:34:19 -04:00
Jens Wiklander
fe39e8e0ee sandbox: imply CONFIG_TEE (TEE uclass)
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-07 10:48:26 -04:00
Jens Wiklander
fa830ae1e4 sandbox: dt: add sandbox_tee node
Adds a sandbox_tee node to enable the sandbox tee driver in all the
sandbox dts files.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-07 10:48:26 -04:00
Jens Wiklander
7ab5630a42 arm: dt: hikey: Add optee node
Sync with 14e21cb8f811 ("arm64: dt: hikey: Add optee node"
from Linux kernel.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-07 10:47:38 -04:00
Patrice Chotard
362612df53 mach-stm32: Set MPU SDRAM size to 512MB for STM32F7/H7
This allows to boot all STM32F7 and STM32H7 boards independently
of the amount of embedded SDRAM.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2018-10-06 14:09:41 -04:00
Adam Ford
5ad4212ce0 ARM: DTS: Add Logic PD OMAP35/DM37 SOM-LV and OMAP35 Torpedo
With the device trees doing most of the work of pin-muxing and
DM doing much of the peripheral initialization, this creates
new defconfig files for each of the Logic PD variants with
proper register settings/pin-muxing.

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Update MAINTAINERS entry]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-06 14:09:27 -04:00
Adam Ford
e2e30f50a9 ARM: DTS: Add support for Logic PD OMAP35 Torpedo & SOM-LV
The baseboards and SOM's are virtually identical to their DM37
counterparts, but OMAP36/37 and OMAP3 have some minor register
differences.  With the boards being mostly driven by device trees
now, this synchronizes their respective device trees with linux-omap
for-next branch destined for 4.20 (or whatever the version after 4.19
will be called)

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-10-06 09:04:18 -04:00
Adam Ford
c981cb8dda ARM: DTS: Remove unnecessary u-boot.dtsi options from omap3/36xx
With the introduction of the omap serial driver, the need for some
of these U-Boot specific modifications is gone.  This cleans up
this unnneeded stuff.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-10-06 09:04:18 -04:00
Adam Ford
87555d1415 ARM: DTS: LogicPD-SOM-LV & Torpedo: Resync DTS with Kernel
The device tree entries are from linux-omap's for-next branch
destined to me put into 4.20 (or whatever the version is after 4.19)

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-10-06 09:04:18 -04:00
Tom Rini
14573fb78f Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-10-05 21:17:35 -04:00
Tom Rini
1b484736ce Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-10-05 21:17:21 -04:00
Tom Rini
a4b38fca7e Rockchip-focused changes for v2018.11-rc2:
- fixes to rkimage for SPL boot via USB
  - fixes to make_fit_atf.py, incl. entry-point calculation and python3
    compatibility
  - OP-TEE support for ARMv7-based SoCs
  - fixes to RGMII/GMII selection on the RK3328
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Merge tag 'rockchip-for-v2018.11-rc2' of git://git.denx.de/u-boot-rockchip

Rockchip-focused changes for v2018.11-rc2:
 - fixes to rkimage for SPL boot via USB
 - fixes to make_fit_atf.py, incl. entry-point calculation and python3
   compatibility
 - OP-TEE support for ARMv7-based SoCs
 - fixes to RGMII/GMII selection on the RK3328

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-05 13:40:42 -04:00
Alexey Brodkin
5396e8b1dd arc: Add support for IoT development kit
The DesignWare ARC IoT Development Kit is a versatile platform
that includes the necessary hardware and software to accelerate
software development and debugging of sensor fusion,
voice recognition and face detection designs.

More information is avaialble here [1] and here [2].

The board is based on real silicon with
ARC EM9D-based Data Fusion IP Subsystem.

It sports a rich set of I/O including
 * DW USB OTG
 * DW MobileStorage (used for micro SD-card)
 * GPIO
 * multiple serial interface including DW APB UART
 * ADC, PWM and eFlash, SRAM and SPI Flash memory
 * Real-Time Clock (RTC)
 * Bluetooth module with worldwide regulatory compliance
   (FCC, IC, CE, ETSI, TELEC)
 * On-board 9-axis sensor (gyro, accelerometer and compass)

Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18
extension header.

One of the most interesting features for developers is built-in
Digilent USB JTAG probe so only micro-USB cable is needed!

[1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit
[2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdf

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05 16:57:00 +03:00
Alexey Brodkin
7fe46b969d ARC: Implement print_cpuinfo()
Once we enable DISPLAY_CPUINFO for ARC we'll see
ARC core family and version printed on boot.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05 16:55:42 +03:00
Alexey Brodkin
c3dcd508b6 ARC: Add model property to boards .dts
1. This way we sync with Linux kernel where we have model
   set for all ARC boards for quite some time, see [1]

2. Once we enable DISPLAY_BOARDINFO for ARC this info will
   be printed on boot givin some extra data-point about the board

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=618a9cd06dd471ac232f5b27325b24d26eba5571

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05 16:55:42 +03:00
Alexey Brodkin
56ddae7d91 ARC: Don't pre-define CROSS_COMPILE
Even though arc-linux- prefix is used in ARC prebuilt tools and
in Buildroot there're other options like Linux distro cross-tools
etc where prefix is different so let's not rely on this default.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05 16:55:42 +03:00
Mian Yousaf Kaukab
7009eae890 rockchip: make_fit_atf: make python3 compatible
Make script python3 compatible. No functional changes intended.

Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Mian Yousaf Kaukab
e4011e8daa rockchip: make_fit_atf: use elf entry point
make_fit_atf.py uses physical address of first segment as the
entry point to bl31. It is incorrect and causes following abort
when bl31_entry() is called:

U-Boot SPL board initTrying to boot from MMC1
"Synchronous Abort" handler, esr 0x02000000
elr: 0000000000000000 lr : 00000000ff8c7e8c
x 0: 00000000ff8e0000 x 1: 0000000000000000
x 2: 0000000000000000 x 3: 00000000ff8e0180
x 4: 0000000000000000 x 5: 0000000000000000
x 6: 0000000000000030 x 7: 00000000ff8e0188
x 8: 00000000000001e0 x 9: 0000000000000000
x10: 000000000007fcdc x11: 00000000002881b8
x12: 00000000000001a2 x13: 0000000000000198
x14: 000000000007fdcc x15: 00000000002881b8
x16: 00000000003c0724 x17: 00000000003c0718
x18: 000000000007fe80 x19: 00000000ff8e0000
x20: 0000000000200000 x21: 00000000ff8e0000
x22: 0000000000000000 x23: 000000000007fe30
x24: 00000000ff8d1c3c x25: 00000000ff8d5000
x26: 00000000deadbeef x27: 00000000000004a0
x28: 000000000000009c x29: 000000000007fd90

Fix it by using the entry point from the elf header.

Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Kever Yang
aabb51da59 rockchip: add fit source file for pack itb with op-tee
We package U-Boot and OP-TEE into one itb file for SPL,
so that we can support OP-TEE in SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Kever Yang
f00273a3a3 rockchip: make_fit_atf: fix warning unit_address_vs_reg
Patch fix warning:
/builddir/BUILD/u-boot-2018.05-rc2/"arch/arm/mach-rockchip/make_fit_atf.py" \
arch/arm/dts/rk3399-firefly.dtb > u-boot.its
  ./tools/mkimage  -f u-boot.its -E u-boot.itb >/dev/null  && cat
/dev/null
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1
has a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@1 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@2 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@3 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node
/configurations/config@1 has a unit name, but no reg property
make[1]: Leaving directory
'/builddir/BUILD/u-boot-2018.05-rc2/builds/firefly-rk3399'

Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Tom Rini
a1588ac822 Rockchip changes for 2018.11
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Merge tag 'rockchip-for-v2018.11' of git://git.denx.de/u-boot-rockchip

Rockchip changes for 2018.11
2018-10-03 12:09:19 -04:00
Ooi, Joyce
8be11fb3c1 arm: socfpga: stratix10: add sgmii in phymode setup
Additional sgmii phymode is added in socfpga_phymode_setup() along with
a minor fix for maximum number of GMACs.

Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
2018-10-03 12:56:50 +02:00
Ley Foon Tan
74c78024a0 arm: socfpga: Remove unused function socfpga_emac_manage_reset()
Remove code from the reset manager that is never called.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-10-03 12:56:50 +02:00
Marek Vasut
806df252c1 ARM: rmobile: Enable PHY framework on Gen3
Enable PHY framework on Gen3, this is required for USB EHCI PHY support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 12:56:13 +02:00
Marek Vasut
c1ec347638 ARM: rmobile: Mark 4-64GiB as DRAM on Gen3
Mark area 0x1_0000_0000 - 0x10_0000_0000 as DRAM on Gen3 as the
chip is capable of addressing that and U-Boot can make use of it.
This patch prevents exception when accessing those areas.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 12:56:13 +02:00
Marek Vasut
2da6d39e26 ARM: dts: rmobile: Reinstate missing i2c6 on Porter
The I2C6 is used to communicate with the PMIC and it was removed
during DT sync with Linux 4.17. Reinstate it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 12:56:12 +02:00
Heinrich Schuchardt
5845f66123 riscv: allow native compilation
If environment variable CROSS_COMPILE is not set, this indicates native
compilation. In this case we should not set an arbitrary value which is
not applicable for 64bit anyway.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-10-03 17:49:44 +08:00
Rick Chen
9d9b3dc0d5 riscv: cosmetic: Reword do_reset() printf message.
The Sentence "reset unsupported yet" is not
grammatically correct and should say
"reset not supported yet" instead.

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Rick Chen <rick@andestech.com>
2018-10-03 17:49:27 +08:00
Bin Meng
b984ddc2dd riscv: Move do_reset() to a common place
We don't have a reset method on any RISC-V board yet. Instead of
adding the same 'unsupported' message for each CPU variant it might
make more sense to add a generic do_reset function for all CPU
variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c).

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:43 +08:00
Bin Meng
510e379c49 riscv: Add QEMU virt board support
This adds QEMU RISC-V 'virt' board target support, with the hope of
helping people easily test U-Boot on RISC-V.

The QEMU virt machine models a generic RISC-V virtual machine with
support for the VirtIO standard networking and block storage devices.
It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
it also uses device-tree to pass configuration information to guest
software. It implements RISC-V privileged architecture spec v1.10.

Both 32-bit and 64-bit builds are supported. Support is pretty much
preliminary, only booting to U-Boot shell with the UART driver on
a single core. Booting Linux is not supported yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:37 +08:00
Bin Meng
cd1f45c21d riscv: kconfig: Imply DM support for some common drivers
This implies DM support for some common drivers that are used on
RISC-V.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:31 +08:00
Bin Meng
bf6cc82c7c riscv: kconfig: Select DM and OF_CONTROL
RISC-V is a pretty new architecture and should support DM and
OF_CONTROL by default.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:25 +08:00
Bin Meng
4694c93fef riscv: ae350: Clean up mixed tabs and spaces in the dts
There are quite a lot of mixed tabs and spaces in the ae350.dts.
Clean them up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:19 +08:00
Bin Meng
b5369c5813 riscv: Make start.S available for all targets
Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:14 +08:00
Bin Meng
ed49ba4dcc riscv: bootm: Pass mhartid CSR value to kernel
So far this is hardcoded to zero, and we should read the value from
mhartid CSR and pass it to Linux kernel.

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:48:08 +08:00
Bin Meng
e5ea1e5860 riscv: Remove CSR read/write defines in encoding.h
There is no reason to keep two versions of CSR read/write defines
in encoding.h. We already have one set of defines in csr.h, which
is from Linux kernel, and let's drop the one in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:48:02 +08:00
Bin Meng
2fab2e9c88 riscv: Add a helper routine to print CPU information
This adds a helper routine to print CPU information. Currently
it prints all the instruction set extensions that the processor
core supports.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:55 +08:00
Bin Meng
ce7a8e0740 riscv: Explicitly pass -march and -mabi to the compiler
At present the compiler flag against which architecture and abi
variant the riscv image is built for is not explicitly indicated
which means the default compiler configuration is used. But this
does not work if we want to build a different target (eg: 32-bit
riscv images using a toolchain configured for 64-bit riscv).

Fix this by explicitly passing -march and -mabi to the compiler.
Since generically we don't use floating point in U-Boot, specify
the RV[32|64]IMA ISA and software floating ABI.

This also fix some alignment coding style issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:43 +08:00
Bin Meng
3d6015651b riscv: Fix coding style issues in the linker script
There are several coding style issues in the linker script. Fix them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:37 +08:00
Bin Meng
dfb828ed1c riscv: Move the linker script to the CPU root directory
The linker script can be shared by all RISC-V targets. Move it to
a common place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:31 +08:00
Bin Meng
8cdc6b58d7 riscv: Remove mach type
Since the mach_id is not used by RISC-V, remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:19 +08:00
Bin Meng
4afeedf172 riscv: bootm: Correct the 1st kernel argument to hart id
The first argument of Linux kernel is the risc-v core hart id,
from which the kernel is booted from. It is not the mach_id,
which seems to be copied from arm.

While we are here, this also changes the Linux kernel entry
parameters' type to support both 32-bit and 64-bit.

Note the hart id is hardcoded to zero for now, and we should
change to fill in it with the value read from mhartid CSR of
the hart which this routine is currently running on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:46:51 +08:00
Bin Meng
3ad4866dd7 riscv: Remove setup.h
This was copied from ARM, and does not apply to RISC-V. While we
are here, bootm.h is eventually removed as its content is only
the inclusion of setup.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:44:44 +08:00
Bin Meng
117a433d9e riscv: kconfig: Normalize architecture name spelling
It's RISC-V that is the official name, not RISCV.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:44:38 +08:00
Tom Rini
592cd5defd Merge branch 'master' of git://git.denx.de/u-boot-spi
This is the PR for SPI-NAND changes along with few spi changes.

[trini: Re-sync changes for ls1012afrwy_qspi*_defconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-02 17:01:46 -04:00
Heiko Stuebner
e4d5fa3db0 rockchip: rk3188: explicitly set vcc_sd0 pin to gpio on rk3188-radxarock
It is good practice to make the setting of gpio-pinctrls explicitly in the
devicetree, and in this case even necessary.
Rockchip boards start with iomux settings set to gpio for most pins and
while the linux pinctrl driver also implicitly sets the gpio function if
a pin is requested as gpio that is not necessarily true for other drivers.

The issue in question stems from uboot, where the sdmmc_pwr pin is set
to function 1 (sdmmc-power) by the bootrom when reading the 1st-stage
loader. The regulator controlled by the pin is active-low though, so
when the dwmmc hw-block sets its enabled bit, it actually disables the
regulator. By changing the pin back to gpio we fix that behaviour.

[picked from the identical linux patch
https://patchwork.kernel.org/patch/10609253/]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-02 09:35:39 +02:00
Heiko Stuebner
598a26a8fb rockchip: rk3188: add u-boot-specific mmc properties
The dwmmc controllers on rk3188 do not have idma support, so need to
use the fifo-mode and it my tests they became confused and stopped
working if the frequency was to high.

While I only tested in somewhat bigger steps, 32MHz for example
hung the controller, while reducing it to 16MHz worked just fine
and is reasonably fast to load a kernel from mmc.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-02 09:35:19 +02:00
Tom Rini
d24c1d0f4d Merge git://git.denx.de/u-boot-dm 2018-09-30 18:16:51 -04:00
Ramon Fried
665e452515 dts: db410c: Add bindings for MSM USB phy
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-09-30 13:00:36 -04:00
Ramon Fried
2df573e6a5 db410c: serial# env using msm board serial
The serial# environment variable needs to be
defined so it will be used by fastboot as serial
for the endpoint descriptor.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-09-30 13:00:35 -04:00
Ramon Fried
6b0861a942 dts: db410c: add alias for USB
Alias is required so req-seq will be filled.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-09-30 13:00:35 -04:00
Tom Rini
b592936d35 Merge branch 'master' of git://git.denx.de/u-boot-video
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-09-29 22:28:44 -04:00
Rajan Vaja
31b8217e83 dm: test: Add "/firmware" node scan test
Add a test which verifies that all subnodes under "/firmware"
nodes are scanned.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added 'imply FIRMWARE' to sandbox Kconfig to fix test failures, fixed
ordering of lines in arch/sandbox/dts/test.dts and test/dm/Makefile,
updated #if condition in drivers/firmware/firmware-uclass.c:
Signed-off-by: Simon Glass <sjg@chromium.org>
2018-09-29 11:49:35 -06:00
Mario Six
e6fd018108 test: Add tests for board uclass
Add tests for the new board uclass.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-29 11:49:35 -06:00
Tom Rini
cc49e2bdb8 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-09-29 11:48:02 -04:00
Tom Rini
d29a583161 Use device tree for mpc85xx with binman. Enabled for T2080QDS.
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Merge tag 'mpc85xx-for-v2018.11-rc1' of git://git.denx.de/u-boot-mpc85xx

Use device tree for mpc85xx with binman. Enabled for T2080QDS.
2018-09-29 11:47:50 -04:00
Tom Rini
27f622d568 Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
 Switch to driver model for SATA on LS1021A and LS1043A.
 Add support for LS1012AFRWY rev C board.
 Enable SMMU for LS1043A.
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Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
Switch to driver model for SATA on LS1021A and LS1043A.
Add support for LS1012AFRWY rev C board.
Enable SMMU for LS1043A.
2018-09-29 11:47:32 -04:00
Adam Ford
973fcc8dae ARM: da850evm_direct_nor_defconfig: Enable DM_SERIAL
With DM enabled, this patch enables DM_SERIAL and removes
the NS16550 initialization from da850_lowlevel since the driver
will take care of that itself.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-29 08:07:28 -04:00
Adam Ford
96a82d33f8 ARM: DTS: various omap3: Remove cd-inverted from u-boot.dtsi
With the omap_mmc driver no longer supporting cd-inverted, this
patch removes all these references since they are not needed.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-29 08:07:26 -04:00
Adam Ford
f4df405f0e mmc: omap_mmc: Remove invert references
With DM_GPIO and DM_MMC translating GPIO_ACTIVE_LOW, any boards
using the 'cd-invert' option will no longer need to do this.  This
patch removes the support for 'invert' from the MMC driver.

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Fix warning over when !DM_GPIO]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-09-29 08:06:56 -04:00
Eugen Hristev
57fb8b4654 ARM: dts: at91: sama5d4_xplained: add onewire connector for LCD eeprom
Add onewire node in device tree for TM series LCDs

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:44 -04:00
Eugen Hristev
db17fbfd96 ARM: dts: at91: sama5d2_ptc: add onewire connector for LCD eeprom
Add onewire node in device tree for TM series LCDs

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:43 -04:00
Eugen Hristev
d656875372 ARM: dts: at91: sama5d27_som1_ek: add onewire connector for LCD eeprom
Add onewire node in device tree for TM series LCDs

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:43 -04:00
Eugen Hristev
2b238c6cdb ARM: dts: at91: sama5d3_xplained: add onewire connector for LCD eeprom
Add onewire node in device tree for TM series LCDs

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:43 -04:00
Eugen Hristev
7f0110d47e ARM: dts: at91: sama5d2_xplained: add onewire connector for LCD eeprom
Add onewire node in device tree for TM series LCDs

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:42 -04:00
Eugen Hristev
cc1bdd23c0 board: sama5d2_ptc_ek: add pda detect call at init time
Call the PDA detection mechanism at boot time so we can have
the pda environment variable ready for use.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:40 -04:00
Eugen Hristev
59e43c3291 board: sama5d3_xplained: add pda detect call at init time
Call the PDA detection mechanism at boot time so we can have
the pda environment variable ready for use.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:40 -04:00
Eugen Hristev
81b8e96511 sandbox: DTS: w1: add node for one wire interface on GPIO
Add a node for the one wire uclass and one wire gpio driver
in sandbox.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-28 20:22:37 -04:00
Jagan Teki
9ad93c0c96 ARM: dts: sun8i: Update A23/A33/r16 dts(i) files from Linux-v4.18-rc3
Update all A23/A33/r16 devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commits.

A23:
commit bc3bd041fe766219a44688b182c260064007f0cc
Author: Miquel Raynal <miquel.raynal@bootlin.com>
Date:   Tue Apr 24 17:55:02 2018 +0200

    ARM: dts: sun8i: a23/a33: declare NAND pins

A33:
commit 88fe315d2c0a397ef42d7639addab0e021ae911d
Author: Maxime Ripard <maxime.ripard@bootlin.com>
Date:   Wed Apr 4 11:57:15 2018 +0200

    ARM: dts: sun8i: a33: Add the DSI-related nodes

r16:
commit 9621d0bd1b0d61167e1853ac68cf4869c31bcc96
Author: Miquel Raynal <miquel.raynal@bootlin.com>
Date:   Tue Apr 24 17:55:03 2018 +0200

    ARM: dts: nes: add Nintendo NES/SuperNES Classic Edition support

Note:
- Drop pinctrl from sun8i-r16-nintendo-nes-classic-edition.dts since
  sun8i-a23-a33.dtsi is added with Linux sync.
- Don't sync non U-Boot supported dts files
   sun8i-a23-ippo-q8h-v1.2.dts
   sun8i-a23-ippo-q8h-v5.dts
   sun8i-a33-et-q8-v1.6.dts
   sun8i-a33-ippo-q8h-v1.2.dts
   sun8i-r16-nintendo-nes-classic.dts
   sun8i-r16-nintendo-super-nes-classic.dts

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-09-28 22:09:24 +05:30
Jagan Teki
b9d59d08a6 ARM: dts: sun7i: Update A20 dts(i) files from Linux-v4.18-rc3
Update all A10 devicetree dtsi and dtsi files from Linux-v4.18-rc3
with below commit:
commit 5d9ef839f874f4e3923c8a9ae7b136c6c3912cd5
Author: Stefan Mavrodiev <stefan@olimex.com>
Date:   Wed May 16 14:38:08 2018 +0300

    ARM: dts: sun7i: Add Olimex A20-SOM-EVB-eMMC board

Note:
- Update sun7i-a20-primo73.dts as per Linux, since
  this dts is U-Boot specific.
- Drop sun7i-a20-olimex-som-evb-emmc.dts since no board
  added for this.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-09-28 22:09:24 +05:30
Jagan Teki
d1d4295aab ARM: dts: sun6i: Update A31/A31s dts(i) files from Linux-v4.18-rc3
Update all A31/A31s devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commit:
commit b240b419db5d624ce7a5a397d6f62a1a686009ec
Merge: 9c2dd8405c0c 518d2f43c358
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Thu Apr 5 21:18:09 2018 -0700

    Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-09-28 22:09:24 +05:30
Jagan Teki
13b36face7 ARM: dts: sun5i: Update A10s/A13/gr8/r8 dts(i) files from Linux-v4.18-rc3
Update all A10s/A13/gr8/r8devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commit:
commit 190e3138f9577885691540dca59c2f07540bde04
Merge: cafc87023b0d a7affb13b271
Author: Arnd Bergmann <arnd@arndb.de>
Date:   Tue Mar 27 14:58:00 2018 +0200

    Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-09-28 22:09:24 +05:30
Jagan Teki
3c92cca3cd ARM: dts: sun4i: Update A10 dts(i) files from Linux-v4.18-rc3
Update all A10 devicetree dtsi and dtsi files from Linux-v4.18-rc3
with below commit:
commit 590b0c0cfc6162aeebbf43eaafb9753b56df1532
Author: Pascal Roeleven <dev@pascalroeleven.nl>
Date:   Fri Apr 20 12:21:12 2018 +0200

    ARM: dts: sun4i: Fix incorrect clocks for displays

Note: Update pinctrl-0 for sun4i-a10-inet-3f.dts, sun4i-a10-inet-3w.dts
like other dts file since there dts file are U-Boot specific.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-09-28 22:09:24 +05:30
Mario Six
4eea531859 video_osd: Add osd sandbox driver and tests
Add sandbox driver and tests for the new OSD uclass.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-28 18:26:52 +02:00
Jagdish Gediya
432054b947 powerpc: dts: Enable device tree support for T2080QDS
Add device tree for T2080QDS board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Update board README for device tree usage.

Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:14:14 -07:00
Jagdish Gediya
3a2f59e244 powerpc: dts: Add u-boot.dtsi to use binman for MPC85xx boards
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:14:06 -07:00
Jagdish Gediya
96699f097a powerpc: mpc85xx: Use binman to embed dtb inside U-Boot
Below is the sequence to embed dtb inside U-Boot,
1. Remove bootpg and resetvec section if needed
2. Append dtb
3. Append bootpg and resetvec section back if removed in step 1

Above procedure is required only when CONFIG_MPC85xx and
CONFIG_OF_SEPARATE are defined.

Add new config CONFIG_MPC85XX_HAVE_RESET_VECTOR to indicate that
image has resetvec section. Step 1 and step 3 described above are
required only if this config is y.

Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:13:59 -07:00
Jagdish Gediya
52fcb717b5 powerpc: mpc85xx: Select BINMAN by default
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:13:55 -07:00
Jagdish Gediya
7d7a8e99e4 powerpc/dts: Makefile changes to clean and build dts
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:13:38 -07:00
Jagdish Gediya
4d3294b1d5 powerpc/dts: Define '_end' symbol in mpc85xx U-Boot lds files
'board_fdt_blob_setup' function sets up fdt blob at '&_end' so
define '_end' symbol in mpc85xx lds files.

Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:13:24 -07:00
Ran Wang
26cbc0d663 armv7: ls102xa: Disable QE before enter deep sleep
Otherwise system will hang after executing wfi.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:01:28 -07:00
Laurentiu Tudor
dc29a4c177 armv8: ls1043a: add icid setup support
Reuse the existing ICID setup code done for LS1046A smmu enablement
and add the equivalent setup for LS1043A chips.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:58:15 -07:00
Laurentiu Tudor
2131079356 armv8: ls1043a: advertise QMan v3 in configuration
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:58:03 -07:00
Laurentiu Tudor
6fae6a1fd6 armv8: fsl-layerscape: add missing qe base address define
Add define for QUICC Engine register block base address.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
[York S: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:56:40 -07:00
Nipun Gupta
a78df40cba u-boot: fixup the iommu-map property of fsl-mc node
The iommu-map property in the fsl-mc node is updated by
valid stream-ids by u-boot. This patch is to fixup this
property for LS208x and LS1088.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:55:05 -07:00
Peng Ma
9ed5ec9b53 armv7: dts: fsl-ls1021a: add sata node support enable sata for ls1021a-qds and ls1021a-twr
Add sata node to support this feature.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:53:13 -07:00
Peng Ma
686203737e armv7: fsl: remove sata support
Remove the old implementation in order to enable DM for sata

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:53:03 -07:00
Peng Ma
d92116566b armv8: dts: fsl-ls1043a: add sata node support
Add sata node to support ls1043a.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:52:11 -07:00
Yinbo Zhu
46d471f5b8 armv7: ls1021a: enable esdhc
This patch is to enable eSDHC for ls1021a.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:51:36 -07:00
Yinbo Zhu
2fd425f8e3 armv8: ls1046a: add eSDHC node
This patch is to add eSDHC node for ls1046a.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:51:22 -07:00
Yinbo Zhu
bdccf12839 armv8: ls1043a: add eSDHC node
This patch is to add eSDHC node for ls1043a.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:51:16 -07:00
Yinbo Zhu
585d357522 armv8: ls1088a: add eSDHC node
This patch is to add eSDHC node for ls1088a.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:51:11 -07:00
Yinbo Zhu
99e0071df5 armv8: ls2088a: add eSDHC node
This patch is to add eSDHC node for ls2088a.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:50:39 -07:00
Yinbo Zhu
0fdf696721 armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support
This patch adds esdhc clock support for ls1088a and ls2088a.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:50:26 -07:00
Yinbo Zhu
c3ced8a6ed ppa/fm/qe: use block layer in ppa/fm/qe driver
At present the MMC subsystem maintains its own list of MMC devices.
This cannot work with driver model when CONFIG_BLK is enabled, use
blk_dread to replace previous mmc read interface, use
mmc_get_blk_desc to get the mmc device property.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
[York S: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:48:51 -07:00
Tom Rini
bbef20d479 Xilinx changes for v2018.11
- Handle BOARD_LATE_INIT via Kconfig
 
 SPL:
 - Enable GZIP for all partitions types(not only for kernel)
 
 ZynqMP:
 - Rearrange pmufw version handling
 - Support newer PMUFW with improved fpga load sequence
 
 Zynq:
 - Cleanup config file
 - Simplify zybo config by enabling option via Kconfig
 
 net:
 - Fix gems max-speed property reading
 - Enable support for fixed-link phys
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Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.11

- Handle BOARD_LATE_INIT via Kconfig

SPL:
- Enable GZIP for all partitions types(not only for kernel)

ZynqMP:
- Rearrange pmufw version handling
- Support newer PMUFW with improved fpga load sequence

Zynq:
- Cleanup config file
- Simplify zybo config by enabling option via Kconfig

net:
- Fix gems max-speed property reading
- Enable support for fixed-link phys
2018-09-27 08:29:10 -04:00
Tom Rini
0ae8dcfef7 Patch queue for efi - 2018-09-26
A lot of goodness in this release. We're *very* close to running the
 UEFI Shell and SCT natively. The only missing piece are HII protocols.
 
   - FAT write support (needed for SCT)
   - improved FAT directory support (needed for SCT)
   - RTC support with QEMU -M virt
   - Sandbox support (run UEFI binaries in Linux - yay)
   - Proper UTF-16 support
   - EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell)
   - EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell)
   - Fix window size determination
   - Fix Tegra by explicitly unmapping RAM
   - Clean up handle entanglement
   - Lots of generic code cleanup
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-09-26

A lot of goodness in this release. We're *very* close to running the
UEFI Shell and SCT natively. The only missing piece are HII protocols.

  - FAT write support (needed for SCT)
  - improved FAT directory support (needed for SCT)
  - RTC support with QEMU -M virt
  - Sandbox support (run UEFI binaries in Linux - yay)
  - Proper UTF-16 support
  - EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell)
  - EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell)
  - Fix window size determination
  - Fix Tegra by explicitly unmapping RAM
  - Clean up handle entanglement
  - Lots of generic code cleanup

[trini: Fixup merge conflict in include/configs/qemu-arm.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-09-26 17:02:46 -04:00
Siva Durga Prasad Paladugu
fbf7fb0f9f fpga: zynqmp: Modify PL bitstream loading sequence
This patch modifies PL bitstream loading sequence as per
latest Xilfpga which supports all variants of bitstream images
generated from vivado and from bootgen. With this new change in
Xilfpga, uboot doesn't need to validate and swap bitstream as it will
be taken care inside Xilfpga. ZynqMP PL driver now checks for supporting
PMUFW version before skipping the validation and swap sequence as there
can be old PMUFW which doesn't supports this feature. In this case, driver
uses old way of PL bitstream loading sequence.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Siva Durga Prasad Paladugu
b94a8271cc arm64: zynqmp: Return pmufw version for zynqmp_pmufw_version()
Modify the zynqmp_pmufw_version() routine to return PMUFW version so
that it can be reused wherever required. Get PMUFW version from PMU
only once at bootup and later just return stored value.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Siva Durga Prasad Paladugu
fe68f2332d arm64: zynqmp: Move PM version related macros to .h
This patch moves the PM version related macros to .h file so that
they can be reused in other files.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Michal Simek
8eb55e1965 arm64: zynqmp: Handle CONFIG_BOARD_LATE_INIT via Kconfig
Disable BOARD_LATE_INIT via Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Bin Meng
d8d81d4a5d config.mk: Remove duplicated -fno-strict-aliasing
Now that we already disable the "strict-aliasing" globally, remove
the duplicates in the nds32/riscv/x86 arch-specific Makefiles.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-25 21:50:34 -04:00
Chris Packham
47cef9c805 xtensa: use asm-generic/atomic.h
Make use of asm-generic/atomic.h.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-25 21:49:18 -04:00
Chris Packham
02df9c5a67 mips: use asm-generic/atomic.h
Make use of asm-generic/atomic.h.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2018-09-25 21:49:18 -04:00
Chris Packham
4d9f7a014d ARM: use asm-generic/atomic.h
Make use of asm-generic/atomic.h retaining the smp_mb_... definitions.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-25 21:49:18 -04:00
Adam Ford
03190a7888 mmc: omap_hsmmc: Fix pbias for omap3_logic to enable CD pin
The MMC card detect pin is connected to gpio127 on omap3_logic.
When setting up the pbias register for MMC, let's also enable
gpio_127 for the card detect.  As part of the package deal,
gpio_126 and gpio_129 are also enabled.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-25 21:49:18 -04:00
Quentin Schulz
484a878273 arm: spear: fix enabling of SSP2 clock
The SSP2 clock is at bit 6 in the register, so the value is 0x40 unlike
the current 0x70 which enables the clock of UART2, SSP1 and SSP2.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Stefan Roese <sr@denx.de>
2018-09-25 21:49:18 -04:00
Quentin Schulz
ac47fbee6d arm: spear: enable SSP1, 2 and 3 clocks when SPI controller driver is built
SPI controllers SSP1, 2 and 3 require to enable their respective clocks.
Let's enable them only when the SPI controller driver is built.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-25 21:49:18 -04:00
Patrice Chotard
bad48a4062 ARM: dts: stm32mp1: Add EHCI support for stm32mp157c-ev1 board
Add DT nodes to enable EHCI support

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-09-25 21:47:39 -04:00
Patrice Chotard
8e9c94d766 ARM: dts: stm32mp1: Add usb gadget support for stm32mp157c-ev1 board
Add DT nodes to enable DWC2 gadget support

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-09-25 21:47:39 -04:00
AKASHI Takahiro
a47c1b5b87 arm: qemu-arm: enable RTC (PL031) by default
Virtual machine provided by qemu-arm has a ARM PL031 Real Time Clock
device. With this patch, the driver is enabled by default.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:31 +02:00
Alexander Graf
6e6e4b2f73 sandbox: Allow to execute from RAM
With efi_loader, we may want to execute payloads from RAM. By default,
permissions on the RAM region don't allow us to execute from there though.

So let's change the default allocation scheme for RAM to also allow
execution from it. That way payloads that live in U-Boot RAM can be
directly executed.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:30 +02:00
Alexander Graf
3fcb714758 sandbox: Fix setjmp/longjmp
In sandbox, longjmp returns to itself in an endless loop because
os_longjmp() calls into longjmp() which is provided by U-Boot which
again calls os_longjmp().

Setjmp on the other hand must not return because otherwise the
return freees up stack elements that we need during longjmp().

The only straight forward fix that doesn't involve nasty hacks I
could find is to directly link against the system setjmp/longjmp
implementations. That means we just provide the compiler with
hints that the symbol will be available and actually fill them
out with versions from libc.

This approach should be reasonably platform agnostic

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:30 +02:00
Simon Glass
428aa0ca56 sandbox: Enhance map_to_sysmem() to handle foreign pointers
At present map_sysmem() maps an address into the sandbox RAM buffer,
return a pointer, while map_to_sysmem() goes the other way.

The mapping is currently just 1:1 since a case was not found where a more
flexible mapping was needed. PCI does have a separate and more complex
mapping, but uses its own mechanism.

However this arrange cannot handle one important case, which is where a
test declares a stack variable and passes a pointer to it into a U-Boot
function which uses map_to_sysmem() to turn it into a address. Since the
pointer is not inside emulated DRAM, this will fail.

Add a mapping feature which can handle any such pointer, mapping it to a
simple tag value which can be passed around in U-Boot as an address.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:30 +02:00
Simon Glass
fe938fb0df sandbox: Add support for calling abort()
This function is useful to signal that the application needs to exit
immediate. It can be caught with a debugger (e.g. gdb). Add a stub for it
so that it can be called from within sandbox when an internal error
occurs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:30 +02:00
Simon Glass
613185023f sandbox: Align RAM buffer to the machine page size
At present the sandbox RAM buffer is not aligned to any particular
address boundary. This makes the internal pointers somewhat random with
respect to the associated RAM buffer addresses.

Align the buffer to the page size of the machine to help with this. Note
that there is a header at the start of the allocated pointer. To avoid
returning a pointer which is not aligned to a page boundary, we waste
almost an entire page of memory for each allocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:30 +02:00
Stephen Warren
0797f7f0b7 ARM: tegra: reserve unmapped RAM so EFI doesn't use it
Tegra U-Boot ensures that board_get_usable_ram_top() never returns a value
over 4GB, since some peripherals can't access such addresses. However, on
systems with more than 2GB of RAM, RAM bank 1 does describe this extra
RAM, so that Linux (or whatever OS) can use it, subject to DMA
limitations. Since board_get_usable_ram_top() points at the top of RAM
bank 0, the memory locations describes by RAM bank 1 are not mapped by
U-Boot's MMU configuration, and so cannot be used for anything.

For some completely inexplicable reason, U-Boot's EFI support ignores the
value returned by board_get_usable_ram_top(), and EFI memory allocation
routines will return values above U-Boot's RAM top. This causes U-Boot to
crash when it accesses that RAM, since it isn't mapped by the MMU. One
use-case where this happens is TFTP download of a file on Jetson TX1
(p2371-2180).

This change explicitly tells the EFI code that this extra RAM should not
be used, thus avoiding the crash.

A previous attempt to make EFI honor board_get_usable_ram_top() was
rejected. So, this patch will need to be replicated for any board that
implements board_get_usable_ram_top().

Fixes: aa909462d0 ("efi_loader: efi_allocate_pages is too restrictive")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:29 +02:00
Stephen Warren
9b5e6396bf efi_loader: simplify ifdefs
Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL
too. This simplifies the conditional.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:29 +02:00
Stefan Roese
fdd1a9ff78 mips: mt7628a.dtsi: Add SPI clock-frequency property
This patch adds the clock-frequency property to the SPI controller
DT node. It will be used by the SPI driver to calculate the baud rate.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-23 14:27:51 +02:00
Stefan Roese
41f6e6eb64 mips: mt76xx: Add sysreset support
This patch adds the necessary sysreset DT node and enables the required
drivers via Kconfig.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-23 14:27:51 +02:00
Stefan Roese
88dc409914 mips: Add Gardena Smart-Gateway board support
The Gardena Smart-Gateway boards have a MT7688 SoC with 128 MiB of RAM
and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND storage.

This patch also includes 2 targets. One is the target that can be
programmed into the SPI NOR flash and a 2nd target "xxx-ram" is
added to support loading and booting via an already running U-Boot
version. This allows easy development and testing without the
need to flash the image each time.

Signed-off-by: Stefan Roese <sr@denx.de>
[fixed and regenerated defconfig files]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-23 14:27:51 +02:00
Stefan Roese
b02f76a835 mips: Add LinkIt Smart 7688 support
The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM
and 32 MiB of flash (SPI NOR).

This patch also includes 2 targets. One is the target that can be
programmed into the SPI NOR flash and a 2nd target "xxx-ram" is
added to support loading and booting via an already running U-Boot
version. This allows easy development and testing without the
need to flash the image each time.

Signed-off-by: Stefan Roese <sr@denx.de>
[fixed and regenerated defconfig files]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-23 14:27:19 +02:00
Stefan Roese
4c835a607b mips: Add basic MediaTek MT7620/88 support
This patch adds basic support for the MediaTek MT7620/88 SoCs. Parts of
the code is copied from the MediaTek GitHub repository:

https://github.com/MediaTek-Labs/linkit-smart-uboot.git

The mt7628a.dtsi file is imported from Linux v4.17.

Support for the LinkIt Smart 7688 module and the Gardena Smart Gateway
both based on the MT7688 will be added in further patches.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 21:18:33 +02:00
Stefan Roese
503f6f759c mips: Add arch/mips/include/asm/atomic.h
This is needed for the UBIFS support. The file is a copy of
arch/xtensa/include/asm/atomic.h

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 21:17:54 +02:00
Daniel Schwierzeck
46203baf66 MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE
Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT
(or CONF_CM_CACHABLE_COW when a CM is available). There is no
need to make this configurable.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 21:04:10 +02:00
Daniel Schwierzeck
5ef337a037 MIPS: cache: make index base address configurable
The index base address used for the cache initialisation is currently
hard-coded to CKSEG0. Make this value configurable if a MIPS system
needs to have a different address (e.g. in SRAM or ScratchPad RAM).

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 21:02:03 +02:00
Daniel Schwierzeck
b838586086 MIPS: cache: optimise changing of k0 CCA mode
Changing the Cache Coherency Algorithm (CCA) for kernel mode
requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1
before changing the CCA mode. Jump back to KSEG0 afterwards.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 21:02:03 +02:00
Daniel Schwierzeck
2f85c2be21 MIPS: cache: reimplement dcache_[status, enable, disable]
Those functions are not needed during cache init and can be
implemented in C. Only support the safe disabling of caches when
this is required for booting an OS. Reenabling caches is much
harder to implement if an optional coherency manager must be
supported. As there is no real use-case anyway, dcache_enable
is implemented with an error message.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 21:02:03 +02:00
Daniel Schwierzeck
d1c3d8bdfa MIPS: start.S: make boot config at offset 0x10 configurable
Some MIPS systems store some board-specific boot configuration
in the U-Boot binary at offset 0x10. This is used by Malta boards
and by Lantiq/Intel SoC's when booting from parallel NOR flash.

Convert the hard-coded values to Kconfig options to remove such
board-specific stuff out of the generic start.S code. This also
deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 20:59:22 +02:00
Philippe Reynes
e98a260eb5 dt: bcm6838: add pinctrl
Add pinctrl node and related syscon node for broadcom bcm6838 SoC.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2018-09-22 20:49:59 +02:00
Miquel Raynal
a430fa06a4 mtd: move NAND files into a raw/ subdirectory
NAND flavors, like serial and parallel, have a lot in common and would
benefit to share code. Let's move raw (parallel) NAND specific code in a
raw/ subdirectory, to ease the addition of a core file in nand/ and the
introduction of a spi/ subdirectory specific to SPI NANDs.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-09-20 20:10:49 +05:30
Tom Rini
9dc8d155d4 Merge git://git.denx.de/u-boot-imx
- changes in pico-* boards
- fix imx6ull pinmux
2018-09-19 20:35:27 -04:00
Tom Rini
333279af23 Merge git://git.denx.de/u-boot-marvell
- Multiples updates to the turris boards / platform
- Changes / enhancements to the Marvell PHY drivers, mainly
  to support the turris platform
- Many fixes and enhancements to the pxa3xx NAND driver
- Fixes for the UART boot mode in kwboot
- Misc minor changes to other 32bit and 64bit boards
2018-09-19 20:35:05 -04:00
Marek Behún
863949e383 board: turris_mox: Fixup U-Boot's device tree if PCIe connected
If PCIe Mox module is connected we want to have PCIe node enabled
in U-Boot's device tree.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:39 +02:00
Baruch Siach
f26e379b31 dts: mvebu: mcbin: drop redundant SD slot node
Commit 61dccf73d3 (dts: mvebu: a80x0: Enable SD/eMMC interfaces) added
a redundant DT node for SD card slot. Drop it.

Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:38 +02:00
Marek Behún
0f6686e228 arch/arm/dts: Update Turris Mox device tree
Remove smi_pins definition since it is already in armada-37xx.dtsi.
Add assigned-clocks definitions to spi0.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 09:00:38 +02:00
Chris Packham
2fd4284051 ARM: mach-mvebu: handle fall-back to UART boot
The bootROM in the Armada-38x (and similar) SoC has two modes for UART
boot. The first is when the normal boot media is blank (or otherwise
missing the kwb header). The second is when the boot sequence has been
interrupted with the magic byte sequence on the UART lines.

In the first mode the bootROM routine and error code register will
indicate that there was an error booting from the configured media in
bits 7:0. In the second mode there is no error to indicate but the boot
source is provided via bits 31:28.

Handle both situations so that kwboot can be used for both boot
strapping a blank board and for intercepting a regular boot sequence.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 08:59:26 +02:00
Chris Packham
e0977297e8 Revert "arm: mvebu: fix boot from UART when in fallback mode"
This reverts commit e83e2b3900. This
prevents kwboot from overriding the hardware strapped boot source.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 08:59:26 +02:00
Baruch Siach
7e1d32208e arm64: mvebu: armada-8k: support environment in SD/eMMC
Detect the SD/eMMC boot device at run-time. Load the environment from
the boot deice, as well as save to it.

Leave the environment offset the same as in the SPI flash.

Make SD/eMMC 0 the default environment device when the boot device is
not detected.

Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-09-19 08:59:26 +02:00
Tom Rini
4e710ebb44 Merge git://git.denx.de/u-boot-dm
- MPC83xx device tree additions (CPU and RAM)
- Fix sandbox build error
- Sync bitrev with Linux
- Various ofnode/DT improvements
2018-09-18 20:42:37 -04:00
Stefano Babic
0eee446ee8 Merge branch 'master' of git://git.denx.de/u-boot into master
Signed-off-by: Stefano Babic <sbabic@denx.de>
2018-09-18 16:53:55 +02:00
Mario Six
d2166319df misc: Add MPC83xx serdes driver
Add a driver to configure the SerDes (Serializer/Deserializer) lanes on
the MPC83xx architecture.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-18 08:12:21 -06:00
Mario Six
19fbdca47b cpu: Add MPC83xx CPU driver
Add a CPU driver for the MPC83xx architecture.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-18 08:12:21 -06:00
Mario Six
fa44b53398 test: Add tests for CPU uclass
Add a sandbox CPU driver, and some tests for the CPU uclass.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-18 08:12:21 -06:00
Mario Six
2c21749d71 timer: Add MPC83xx timer driver
Add a timer driver for the MPC83xx architecture.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-18 00:01:18 -06:00
Mario Six
07d538d281 clk: Add MPC83xx clock driver
Add a clock driver for the MPC83xx architecture.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-18 00:01:18 -06:00
Mario Six
76fdad1f21 mpc83xx: Add sysreset driver
Add a sysreset driver for the MPC83xx platform.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-18 00:01:18 -06:00
Mario Six
08f5b0b23a powerpc: Add read*_*/write*_* macros
Define the read*_*/write*_* macros for the PowerPC platform to be able
to use the macros in wait_bit.h.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-18 00:01:18 -06:00
Mario Six
e40615565d ram: Add driver for MPC83xx
Add a RAM driver for the MPC83xx architecture.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-18 00:01:18 -06:00
Bin Meng
0f1caa9880 sandbox: Enable bitrev library build
Imply CONFIG_BITREVERSE for Sandbox.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-18 00:01:18 -06:00
Andy Shevchenko
e599c4e7d8 sandbox: Build with -fPIC
Sandbox is not a real bootloader and it does require
a position independent code to be supported.

Thus, build it with -fPIC explicitly.

Fixes: 16940f720f9b ("Makefile: Don't generate position independent code")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reported-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2018-09-18 00:01:18 -06:00
Tom Rini
b57f1895b6 Merge git://git.denx.de/u-boot-x86 2018-09-17 08:04:25 -04:00
Georgii Staroselskii
6321da5263 x86: cpu: add docstring to scu_ipc_command()
These comments were copied from the Linux kernel driver in
drivers/platform/x86/intel_scu_ipc.c

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-17 17:35:53 +08:00
Georgii Staroselskii
f7ce2d6e65 x86: tangier: acpi: add I2C6 node
Now that we have I2C#6 working, it's time to add a corresponsing
ACPI binding.

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-17 17:35:53 +08:00
Georgii Staroselskii
f26b260c69 x86: dts: edison: configure I2C#6 pins
Now that we have the pinctrl driver for Merrifield in place we can make
use of it and set I2C#6 pins appropriately.

Initial configuration came from the firmware.  Which quite likely has
been used in the phones, where that is not part of Atom peripheral, is
in use. Thus we need to override the leftover.

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-17 17:35:52 +08:00
Georgii Staroselskii
355c9b757e x86: tangier: pinmux: add API to configure protected pins
This API is going to be used to configure some pins that are protected
for simple modification.

It's not a comprehensive pinctrl driver but can be turned into one
when we need this in the future. Now it is planned to be used only
in one place. So that's why I decided not to pollute the codebase with a
full-blown pinctrl-merrifield nobody will use.

This driver reads corresponding fields in DT and configures pins
accordingly.

The "protected" flag is used to distinguish configuration of SCU-owned
pins from the ordinary ones.

The code has been adapted from Linux work done by Andy Shevchenko
in pinctrl-merrfifield.c

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix build warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-17 17:35:52 +08:00
Georgii Staroselskii
224742a390 x86: cpu: introduce scu_ipc_raw_command()
This interface will be used to configure properly some pins on
Merrifield that are shared with SCU.

scu_ipc_raw_command() writes SPTR and DPTR registers before sending
a command to SCU.

This code has been ported from Linux work done by Andy Shevchenko.

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-17 14:34:15 +08:00
Tom Rini
40e44c8bf5 Merge branch 'master' of git://git.denx.de/u-boot-coldfire 2018-09-16 10:32:33 -04:00
Tom Rini
9e45008b39 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-09-16 10:30:16 -04:00
Angelo Dureghello
2c92e4fbc6 m68k: ColdFire mcf5441x, add eSDHC support
This patch adds mcf5441x eSDHC support for the mcf5441x family.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2018-09-16 00:01:13 +02:00
Angelo Dureghello
faae49543a m68k: fix multiple memory accesses on swap operations
On a
	u32 val = __sw32(*addr);

multiple memory accesses are not welcome, since "addr" may
be an IO peripheral register address.
This patch changes __sw16/32 to perform a single memory
access for the source value.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2018-09-16 00:01:13 +02:00
Angelo Dureghello
a1ed3a83be m68k: fix mcf5441x total interrupt number
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
2018-09-16 00:01:13 +02:00
Marek Vasut
0e286c529f sh: tmu: Zap get_tbclk and timer_read_counter
Replace those two functions with generic ones by defining the
timer macros in include/config/*.h .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-09-15 03:19:07 +02:00
Marek Vasut
f02c1f695e sh: tmu: Clean up register usage
The code uses all in all three TMU registers, drop the massive
register layout structures and just define the required timer
registers and use them throughout the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-09-15 03:19:07 +02:00
Marek Vasut
8b39df9e78 sh: tmu: Inline sh_tmu.h
The header contains only the TMU register layout, just inline it
into the TMU timer implementation and drop the header completely.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-09-15 03:19:07 +02:00
Marek Vasut
ccce3acfe7 sh: tmu: Clean up CONFIG_SH_TMU_CLK_FREQ
The R-Car Gen2 feeds the TMU with CONFIG_SYS_CLK_FREQ / 2,
while the old SH parts use CONFIG_SYS_CLK_FREQ directly.
Just put this into the TMU implementation and drop the
CONFIG_SH_TMU_CLK_FREQ config option.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-09-15 03:19:07 +02:00
Marek Vasut
ae59a9f8f7 sh: tmu: Inline get_tmu0_clk_rate()
This function just returns CONFIG_SH_TMU_CLK_FREQ, use the constant
directly instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-09-15 03:19:07 +02:00
Marek Vasut
15f11fc6d7 sh: tmu: Inline tmu_timer_{start,stop}()
These functions are always called for timer = 0, so drop the
timer check. Since these functions are called from one place
only and they are reduced to one line of code, just inline
them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-09-15 03:19:07 +02:00
Marek Vasut
eb05dcfea2 sh: tmu: Simplify the tmu_bit math
The tmu_bit value evaluates to (ffs(4) >> 1) - 1 = (3 >> 1) - 1 = 0.
Just drop the tmu_bit completely as well as CONFIG_SYS_TMU_CLK_DIV.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-09-15 03:19:07 +02:00
Marek Vasut
d1da5d6cd8 sh: tmu: Clean up CONFIG_SYS_TMU_CLK_DIV
This constant is always 4 , for all boards that exist. Define it
once in arch/sh/lib/time.c and remove it from the configs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-09-15 03:19:07 +02:00
Marek Vasut
2606deb22b sh: sh7724: Drop EDMR macro
Drop the macro as it is never used and it collides with sh_eth.h macros.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-09-15 03:19:06 +02:00
Dalon Westergreen
02d8d32591 socfpga: stratix10: fix sdram_calculate_size
Incorrect type of size variable results in 0 being
returned for sdram sizes greater than or equal to
4GB.

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2018-09-15 03:17:01 +02:00
Tom Rini
ecb10a41c9 Revert "ARM: da850evm_direct_nor_defconfig: Enable DM_SERIAL"
This commit is breaking several variants of da850, so:

This reverts commit 5f389201de.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-09-14 13:52:15 -04:00
Heiko Schocher
df158705a8 imx: imx6ull: fix pinmux input_val for uart5 rx pin
just try to bring up an imx6ull board with console
on uart5 and found, that input_val for pin
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX is 7 and
not 5 on imx6ull.

With this patch rx works now.

Signed-off-by: Heiko Schocher <hs@denx.de>
2018-09-14 15:22:52 +02:00
Fabio Estevam
82a8a93327 pico-imx6ul: Convert to SPL
There are two versions of imx6ul pico SOMs: one with 256MB and another
one with 512MB of RAM.

Convert to SPL so that both versions can be supported. This patch
doesn't rework the clock initialization to avoid changing the behavior
in this same patch, so it will be cleaned up in future.

Currently only the 256MB is tested/supported.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2018-09-14 15:04:24 +02:00
Adam Ford
5f389201de ARM: da850evm_direct_nor_defconfig: Enable DM_SERIAL
With DM enabled, this patch enables DM_SERIAL and removes
the NS16550 initialization from da850_lowlevel since the driver
will take care of that itself.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-11 21:42:41 -04:00
Adam Ford
668146128a ARM: mach-omap2: Don't initialize I2C if DM_I2C is enabled
boot-common.c checks to see if I2C is enabled in SPL, but
it doens't check for DM_I2C before initializing it.  This
will now only initialize the I2C is the DM_I2C is not enabled
to avoid initializing it more than once.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-11 21:39:02 -04:00
Adam Ford
abb205ded1 ARM: dts: da850-evm-u-boot: Remove redundant entries
With the re-sync from Linux 4.18, several entries in
da850-evm-u-boot.dtsi are no longer necessary, so this patch
removes them.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-11 21:38:08 -04:00
Adam Ford
8e12559193 arm: dts: da850: Re-sync da850-evm.dts from Linux 4.18
Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-11 21:38:04 -04:00
Tom Rini
d1e15041ab Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2018-09-11 08:50:10 -04:00
Lokesh Vutla
853f7f5018 arm64: dts: k3: Add u-boot specific nodes
Add the minimum dt nodes required to boot. These nodes
will get deleted as kernel gets these nodes added in the
main dts files.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
ea8ad1d9b6 arm64: dts: k3: Add Support for AM654 SoC
Add initial DT support for AM654 EVM that runs on A53.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
0911d95263 board: ti: am654: a53: Add initial support for am654
Add initial support for AM654 based EVM running on A53. Enable
4GB of DDR available on the EVM so that kernel DTB file
can be updated accordingly.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[Andreas: Added 4GB ddr support]
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
3980b16137 gpio: do not include <asm/arch/gpio.h> for ARCH_K3
As no gpio.h is defined in arch/arm/mach-k3/include/,
to avoid compilation failure, do not include asm/arch/gpio.h.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
82f29fd513 armv8: K3: am654: Add support for generating build targets
Update Makefile to generate
- tispl.bin: First stage bootloader on ARMv8 core
- u-boot.img: Second stage bootloader on ARMv8 core.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
e091832f25 armv8: K3: am654: Add custom MMU support
Add MMU mappings for AM654 SoC.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Andreas Dannenberg
c68721d93a arm: K3: am654: Unlock control module registers during init
By default the device control module registers are locked,
preventing any writes to its registers.
Unlock those registers as part of the init flow.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
e00646099f arm: K3: am654: Add support for boot device detection
AM654 allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
f70b72e353 arm: K3: Update _start instruction
On K3 family SoCs, once the ROM loads image on R5, M3 resets R5 and
expects to start executing from 0x0. In order to handle this ROM
updates the boot vector of R5 such that first 64 bytes of image load
address are mapped to 0x0.

In this case, it is SPL's responsibility to jump to the proper image
location. So, update the PC with address of reset vector(like how
other exception vectors are handled), instead of branching to reset.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
ed0e605124 arm: K3: Add support for AM654 SoC definition
The AM654 device is designed for industrial automation and PLC
controller class platforms among other applications. Introduce
base support for AM654 SoC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-11 08:32:55 -04:00
Lokesh Vutla
586bde93eb arm: K3: Add initial support for TI's K3 generation of SoCs
Add support for Texas Instruments' K3 Generation Processor
families.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-11 08:32:55 -04:00
Masahiro Yamada
e39eed8f47 ARM: uniphier: remove ad-hoc clock enabling for EHCI
The MIO clock is enabled by default, and the STDMAC clock is
enabled by the clk driver.  The ad-hoc way to enable the clock
is no longer needed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-11 20:37:19 +09:00
Masahiro Yamada
c3ab1e118f mmc: uniphier-sd: sync with Linux
Sync with the driver code and the binding recently merged in Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-11 20:37:18 +09:00
Masahiro Yamada
33aae6b5ed ARM: dts: uniphier: sync DT with Linux 4.19-rc1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-11 20:37:16 +09:00
Vikas Manocha
d22336aad9 arm: armv7m: clean up armv7m unified code compilation
unified syntax should be selected by config ARM_ASM_UNIFIED

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2018-09-10 21:19:33 -04:00
Vikas Manocha
680223a2da arm: armv7m: remove un-necessary If then instruction
With gas option -mimplicit-it=always, IT block is inserted by the assembler
for thumb2.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2018-09-10 21:19:33 -04:00
Vikas Manocha
17d2887a9e arm: stm32: Remove redundant thumb build selection
All armv7m arch builds are thumb & SYS_THUMB_BUILD is already selected by
CPU_ARMV7M.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2018-09-10 21:19:33 -04:00
Quentin Schulz
d2d908d258 arm: spear: enable GPIO3 and 4 clocks when the GPIO controller driver is built
There are multiple GPIOs that can be used with the same driver depending
on the CONFIG_GPIO_BASE defined in the controller driver.

GPIO3 and 4 require a clock to be enabled so let's enable them when the
driver is built.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-10 21:19:32 -04:00
Thomas Fitzsimmons
3f20321ad8 board: arm: Add support for Broadcom BCM7260
Add support for loading U-Boot on the Broadcom 7260 SoC.  This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
2018-09-10 21:19:31 -04:00
Adam Ford
93b283d49f ARM: CPU: arm926ejs: Consolidate cache routines to common file
Four different boards had different options for enabling cache
that were virtually all the same.  This consolidates these
common functions into arch/arm/cpu/arm926ejs/cache.c

This also has the positive side-effect of enabling cache on
the Davinci (da850) boards.

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add mach-at91 to the list of consolidations]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-09-10 21:19:16 -04:00
Eugen Hristev
51330c72f0 at91: fix devicetree warnings
This commit fixes various devicetree warnings in the at91 devicetrees
like:
arch/arm/dts/sama5d36ek_cmp.dtb: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property

These warnings make buildman report failed builds for most of at91 boards.
Thus, fixing it.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-10 20:48:18 -04:00
Eugen Hristev
6e18adaf11 ARM: dts: Makefile: fix build for at91family
For at91family, makefile was building unwanted DTBs
Moved them under specific target configuration.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2018-09-10 20:48:18 -04:00
Masahiro Yamada
dee37fc99d Remove <inttypes.h> includes and PRI* usages in printf() entirely
In int-ll64.h, we always use the following typedefs:

  typedef unsigned int         u32;
  typedef unsigned long        uintptr_t;
  typedef unsigned long long   u64;

This does not need to match to the compiler's <inttypes.h>.
Do not include it.

The use of PRI* makes the code super-ugly.  You can simply use
"l" for printing uintptr_t, "ll" for u64, and no modifier for u32.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10 20:48:17 -04:00
Masahiro Yamada
3747bdbb2b arch: types.h: factor out fixed width typedefs to int-ll64.h
All architectures have the same definition for s8/16/32/64
and u8/16/32/64.

Factor out the duplicated code into <asm-generic/int-ll64.h>.

BTW, Linux unified the kernel space definition into int-ll64.h
a few years ago as you see in Linux commit 0c79a8e29b5f
("asm/types.h: Remove include/asm-generic/int-l64.h").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10 20:48:16 -04:00
Masahiro Yamada
9865543ae6 Remove CONFIG_USE_STDINT
You do not need to use the typedefs provided by compiler.

Our compilers are either IPL32 or LP64.  Hence, U-Boot can/should
always use int-ll64.h typedefs like Linux kernel, whatever the
typedefs the compiler internally uses.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10 20:48:16 -04:00
Adam Ford
de39dc7162 arm: armv7-a: Compile and tune for armv7-a instead of armv5
arch/arm/Makefile references armv5 for backwards compatibility with
older compilers.  This patch removes those references to armv5,
since by now newer compilers are required which should have armv7
support enabled.

The Makefile also also has a list of options for mtune, but the
entry for CONFIG_CPU_V7A is empty, so this patch tunes the
CPU_V7A architecture to generic-armv7-a.

The following size changed apply to omap3_logic using GCC.

Stock
text data bss dec hex filename
50910 429 67580 118919 1d087 spl/u-boot-spl
540713 22700 327072 890485   d9675 u-boot

Without Armv5
text data bss dec hex filename
50916 429 67580 118925   1d08d spl/u-boot-spl
540719 22700 327064 890483   d9673 u-boot

mtune=generic-armv7-a
text data bss dec hex filename
50932 429 67580 118941   1d09d spl/u-boot-spl
540519 22700 327080 890299   d95bb u-boot

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-10 20:48:16 -04:00
Chen-Yu Tsai
792b204798 ARM: Specify aligned address for secure section instead of using attributes
In commit a1274cc94a ("ARM: Page align secure section only when it is
executed in situ"), we used output section attributes (the "ALIGN"
keyword after the colon) to specify the alignment requirements. Using
the constant "COMMONPAGE" there was recently broken in binutils 2.31 [1].

Binutils maintainer Alan Modra suggested the former method would still
work. Since both methods achieve the same result, this patch does just
that. This fixes the "reboot after bootm" issue we've been seeing on
sunxi when booting non-secure.

  [1] https://sourceware.org/bugzilla/show_bug.cgi?id=23571

Suggested-by: Alan Modra <amodra@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-07 09:11:42 -04:00
Adam Ford
548c35ff6e ARM: dts: logicpd-torpedo-37xx-devkit-u-boot: Fix MMC Card Detect
When re-syncing the DTS files from the kernel, something caused
the MMC driver to no longer detect the MMC card. Undoing the
CD-invert appears to fix the issue.

Fixes: e6ea2390cd ("ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit
with Linux 4.18-RC4")

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-05 16:01:22 -04:00
Tom Rini
8a51db1d54 Merge tag 'arc-updates-for-2018.09' of git://git.denx.de/u-boot-arc
Minor changes for ARC

1. Fix CPU clock value in HSDK's .dts so time is counted properly.
2. Enable bootelf command on EMDK
2018-09-05 11:39:03 -04:00
Eugeniy Paltsev
13e57722fe ARC: HSDK: Fix timer frequency value
CPU (and hence cpu timers) on HSDK board runs at 500MHz after
preloader so fix wrong CPU frequency value in hsdk.dts

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2018-09-05 18:11:45 +03:00
Tom Rini
b2f90c461e Merge branch 'master' of git://git.denx.de/u-boot-imx 2018-09-04 17:45:53 -04:00
Anson Huang
57b620255e imx: mx7: add system suspend/resume support
This patch adds system suspend/resume support,
when linux kernel enters deep sleep mode, SoC will go
into below mode:

 - CA7 platform goes into STOP mode;
 - SoC goes into DSM mode;
 - DDR goes into self-refresh mode;
 - CPU0/SCU will be powered down.

When wake up event arrives:

 - SoC DSM mdoe exits;
 - CA7 platform exit STOP mode, SCU/CPU0 power up;
 - Invalidate L1 cache;
 - DDR exit self-refresh mode;
 - Do secure monitor mode related initialization;
 - Jump to linux kernel resume entry.

Belwo is the log of 1 iteration of system suspend/resume:

[  338.824862] PM: suspend entry (deep)
[  338.828853] PM: Syncing filesystems ... done.
[  338.834433] Freezing user space processes ... (elapsed 0.001 seconds) done.
[  338.842939] OOM killer disabled.
[  338.846182] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
[  338.869717] PM: suspend devices took 0.010 seconds
[  338.877846] Disabling non-boot CPUs ...
[  338.960301] Retrying again to check for CPU kill
[  338.964953] CPU1 killed.
[  338.968104] Enabling non-boot CPUs ...
[  338.973598] CPU1 is up
[  339.267155] mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
[  339.275833] mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
[  339.284158] mmc1: queuing unknown CIS tuple 0x80 (6 bytes)
[  339.385065] PM: resume devices took 0.400 seconds
[  339.389836] OOM killer enabled.
[  339.392986] Restarting tasks ... done.
[  339.398990] PM: suspend exit

The resume entry function has to initialize stack pointer before calling
C code, otherwise there will be an external abort occur, in additional,
invalidate L1 cache must be done in secure section as well, so this
patch also adds assembly code back and keep it as simple as possible.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
2018-09-04 08:47:23 +02:00
Anson Huang
b059837850 imx: mx7: add gpc initialization for low power mode
Add i.MX7D GPC initialization for low power mode
support like system suspend/resume from linux kernel:

 - Pending IOMUXC IRQ to workaround GPC state machine issue;
 - Mask all GPC interrupts for M4/C0/C1;
 - Configure SCU timing;
 - Configure time slot ack;
 - Configure C0/C1 power up/down timing;
 - Configure wakeup source mechanism;
 - Disable DSM/RBC related settings.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-04 08:47:23 +02:00
Anson Huang
11e52bca84 imx: mx7: psci: improve cpu hotplug flow
This patch improves cpu hotplug, previous cpu_off
implementation is NOT safe, a CPU can NOT power down
itself in runtime, it will cause system bus hang due
to pending transaction. So need to use other online
CPU to kill it when it is ready for killed.

Here use SRC parameter register and a magic number
of ~0 as handshake for killing a offline CPU,
when the online CPU checks the psci_affinity_info,
it will help kill the offline CPU according to
the magic number stored in SRC parameter register.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-04 08:47:23 +02:00
Martin Kaiser
69f78cf840 watchdog: mx25: use the imx_watchdog driver for mx25
The existing imx_watchdog driver is compatible with mx25 chipsets.
Add a WDOG1_BASE_ADDR define for the base address and enable the driver
in watchdog's Makefile.

To use the driver, a board must define CONFIG_IMX_WATCHDOG and
CONFIG_HW_WATCHDOG.

This fixes an issue when booting an mx25 chip via usb/serial. In this
case, the boot rom will always enable the watchdog. If u-boot is running
in interactive mode and the watchdog is not serviced, the system is
rebooted when the watchdog expires.

Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-09-04 08:47:23 +02:00
Ye Li
25baafc44c dts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boards
Add the board DTS files for 14x14 EVK and 9x9 EVK. They are necessary
for converting to use u-boot DM driver.

Two -u-boot.dtsi are added to modify compatible string of SPI flash
device to "spi-flash".

Signed-off-by: Ye Li <ye.li@nxp.com>
2018-09-04 08:47:23 +02:00
Ye Li
9e1e6f6fe8 dts: imx6ul: Update alias to support DM
Add spi0 alias for qspi for enabling DM SPI.
Change usb alias for usbotg1 and usbotg2 for enabling DM USB

Signed-off-by: Ye Li <ye.li@nxp.com>
2018-09-04 08:47:23 +02:00
Ye Li
3b82335015 imx: imx7d-sdb: Add DM QSPI support
On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default).
To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399
populate R392-R395, R299, R300). So we add new DTS file and new defconfig
dedicated for QSPI.

Other changes to support the DM QSPI:
 - Add QSPI node and alias spi0.
 - Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req
   conflict
 - Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to
   align with kernel and also present the conflict.
 - Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to
   "spi-flash"
 - Remove iomux settings of qspi in board codes which is not needed
   for DM driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
2018-09-04 08:47:23 +02:00
Ye Li
0925ee2185 imx: imx6sx-sabreauto: convert to use DM QSPI driver
To support DM QSPI driver:
 - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string
   to "spi-flash" and add "num-cs" property.
 - Enable DM SPI and DM SPI FLASH configurations
 - Remove iomux settings of qspi1 in board codes which is not needed
   for DM driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
2018-09-04 08:47:23 +02:00
Ye Li
536c5c7a33 imx: imx6sx-sdb: Enable DM QSPI driver
To support DM QSPI driver
 - Add spi0 and spi1 alias for qspi1 and qspi2.
 - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string
   to "spi-flash" and add "num-cs" property.
 - Enable DM SPI/QSPI relavent configurations
 - Remove iomux settings of qspi2 in board codes which is not needed
   for DM driver.
 - Add sf default settings. So running "sf probe" can detect the flash

Signed-off-by: Ye Li <ye.li@nxp.com>
2018-09-04 08:47:23 +02:00
Tom Rini
4b69e870e9 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2018-08-30 10:06:19 -04:00
Bin Meng
e69cc6bc42 x86: zimage: Remove acpi_rsdp_addr propagation to kernel boot parameters
As of today, the proposal of adding "acpi_rsdp_addr" to the kernel
boot protocol does not make its way to the kernel mainline. This
creates some confusion if we leave it in the U-Boot code base.
Remove it for now until we have a clear picture with kernel upstream.

Note this eventually does a partial revert to commit 3469bf4274
("x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters")

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-30 11:23:15 +08:00
Bin Meng
1fdeacd32c x86: zimage: Support booting Linux kernel from an EFI payload
At present Linux kernel loaded from U-Boot as an EFI payload does
not boot. This fills in kernel's boot params structure with the
required critical EFI information like system table address and
memory map stuff so that kernel can obtain essential data like
runtime services and ACPI table to boot.

With this patch, now U-Boot as an EFI payload becomes much more
practical: it is another option of kernel bootloader, ie, can be
a replacement for grub.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-30 11:23:14 +08:00
Bin Meng
aac79251c7 x86: efi: payload: Install E820 map from EFI memory map
This implements payload-specific install_e820_map() to get E820 map
from the EFI memory map descriptors.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-30 09:56:58 +08:00
Kever Yang
feb64f9d51 rockchip: dts: fix unnecessary '-cells' warning
Fix warning below:
unnecessary #address-cells/#size-cells without "ranges" or child "reg"
property

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-08-29 20:44:50 +02:00
Masahiro Yamada
c6cca10b9c cmd: ubi: change 'default y' for SUNXI to 'imply' in Kconfig
It is not preferred to put SUNXI-specific code in the common place.

Change it to 'imply' property of ARCH_SUNXI.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-26 12:24:03 -04:00
Tom Rini
a376702f76 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-08-24 16:11:12 -04:00
Tom Rini
15fd1b7903 Merge branch 'master' of git://git.denx.de/u-boot-usb 2018-08-24 16:11:01 -04:00
Thomas Fitzsimmons
a5e34fc0b6 board: arm: bcmstb: Declare get_ticks in timer.h
In an earlier proposed patch, bcmstb.c implemented timer_read_counter,
but it was updated to implement get_ticks instead.  This patch updates
the declaration in timer.h accordingly.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
2018-08-24 13:20:19 -04:00
Marek Vasut
a029f540c5 ARM: dts: socfpga: Add missing NAND reset
The NAND reset is missing from DT, so the reset manager cannot unreset the NAND.
Add the missing DT reset entry.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24 12:05:21 +02:00
Marek Vasut
b67f80148e ARM: dts: socfpga: Drop ad-hoc UART clock frequency encoding from DT
The UART clock frequency can be obtained from the clock framework by the
ns16550 driver, so drop this redundant DT node.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24 12:05:21 +02:00
Marek Vasut
331c372210 ARM: socfpga: Convert Arria10 to timer framework
Switch the Arria10 from ad-hoc hardcoded timer to timer framework
and the DW APB timer driver. This allows the A10 to extract timer
information, like timer rate, from clock framework and thus DT
instead of having it hardcoded in U-Boot configuration files.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24 12:05:20 +02:00
Marek Vasut
cca9af63a3 ARM: dts: socfpga: Flag timer clock as pre-reloc
Flag timer clock as DM pre-reloc, so that a timer driver can be used and
it can extract information about it's clock rate using the clock framework.
This patch also moves some of the pre-reloc flags into the core dtsi file,
this is because the timer is not board specific, but rather is used on all
boards.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24 12:05:20 +02:00
Marek Vasut
0b8f6378cb ARM: socfpga: Reorder Arria10 SPL
The Arria10 SPL is a complete mess of calls to functions which are
called in the wrong context and it is surprise it works at all. This
patch tries to clean that mess up by shuffling the function calls
around and moving the calls into the correct context. Due to the
delicate nature of the reordering, this is done in one huge patch.

The following changes happen in this patch:
- Security policy init and NIC301 happens first in board_init_f()
- The clock init happens very early in board_init_f() in SPL only
- arch_early_init_r() only registers the FPGA, just like on Gen5
- arch_early_init_r() is never called from any _f() function
- Dedicated FPGA pins are inited in board_init_f() as on Gen5

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24 12:05:20 +02:00
Ley Foon Tan
8497cb9b25 arm: socfpga: stratix10: Fix mailbox urgent command with urgent register
According to mailbox spec, software should send urgent command with
urgent register instead of COUT location. This patch write urgent
command index to urgent register.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24 12:05:20 +02:00
Ley Foon Tan
db3b5e9898 arm: socfpga: stratix10: Enable EMAC to FPGA bridge based on handoff
Code checking and setting EMAC use fpga is in
populate_sysmgr_fpgaintf_module(). So, call to sysmgr_pinmux_init()
instead of populate_sysmgr_pinmux().
In sysmgr_pinmux_init(), it will call to both populate_sysmgr_pinmux()
and populate_sysmgr_fpgaintf_module().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-24 12:05:20 +02:00
Tom Rini
3b1c0d89b9 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-08-23 20:05:37 -04:00
Simon Glass
7bf07cf872 Partially revert "efi_loader: Rename sections to allow for implicit data"
This partially reverts commit 7e21fbca26.

That change broke sandbox EFI support for unknown reasons. It also changes
sandbox to use--gc-sections which we don't want.

For now I am just reverting the sandbox portion as presumably this change
is safe on other architectures.

Fixes: 7e21fbca26 (efi_loader: Rename sections to allow for implicit data)
Signed-off-by: Simon Glass <sjg@chromium.org>
2018-08-23 16:17:41 -04:00
York Sun
50f566d6ee armv8: fsl-layerscape: Update README.falcon for compression
Update README.falcon to use "none" for compression property for
ramdisk image to avoid being uncompressed upon loading.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-08-23 08:17:35 -07:00
Tom Rini
2418734ed4 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2018-08-22 22:36:08 -04:00
Tom Rini
26699998e9 Patch queue for efi - 2018-08-21
A few fixes for 2018.09. Most noticable are:
 
   - unbreak x86 target (-fdata-section fallout)
   - fix undefined behavior in a few corner cases
   - make Jetson TX1 boot again
   - RTS fixes
   - implement reset for simple output
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Merge tag 'signed-efi-2018.09' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-08-21

A few fixes for 2018.09. Most noticable are:

  - unbreak x86 target (-fdata-section fallout)
  - fix undefined behavior in a few corner cases
  - make Jetson TX1 boot again
  - RTS fixes
  - implement reset for simple output
2018-08-21 13:15:21 -04:00
Stephen Warren
3d186cf3f3 ARM: tegra: avoid more operations in non-secure world
A secure monitor that runs before U-Boot, and hence causes U-Boot to run
in non-secure world, must implement a few operations that U-Boot
otherwise implements when running in secure world. Fix U-Boot to skip
these operations when running in non-secure world. In particular:

- The secure monitor must provide the LP0 resume code and own LP0
  configuration in order to maintain security, so must initialize all
  the PMC scratch registers used by the boot ROM during LP0 resume.
  Consequently, U-Boot should not attempt to clear those registers,
  since the register accesses will fail or cause an error.

- The secure monitor owns system security, and so is responsible for
  configuring security-related items such as the VPR.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-08-21 08:41:00 -07:00
Nicolas Chauvet
0de68cf3f8 arm: tegra: Restore host1x/dc dm-pre-reloc properties
Since commit f2faffecb0, tegra: Convert to use binman
the dm-pre-reloc properties are removed.

This leads U-Boot not to enable the display on paz00

This patch restore the dm-pre-reloc properties allowing
the bootloader to output to the display panel

v4: - Spell project name as appropriate
v3: - Fix few typos
v2: - Add more characters to commit hash

Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-08-21 08:34:55 -07:00
Jean-Jacques Hiblot
49c752c93a cmd: Add bind/unbind commands to bind a device to a driver from the command line
In some cases it can be useful to be able to bind a device to a driver from
the command line.
The obvious example is for versatile devices such as USB gadget.
Another use case is when the devices are not yet ready at startup and
require some setup before the drivers are bound (ex: FPGA which bitsream is
fetched from a mass storage or ethernet)

usage example:

bind usb_dev_generic 0 usb_ether
unbind usb_dev_generic 0 usb_ether
or
unbind eth 1

bind /ocp/omap_dwc3@48380000/usb@48390000 usb_ether
unbind /ocp/omap_dwc3@48380000/usb@48390000

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-08-21 16:21:37 +02:00
Jean-Jacques Hiblot
7ec9181d6a dm: convert device_get_global_by_of_offset() to device_get_global_by_ofnode()
Also add device_find_global_by_ofnode() that also find a device based on
the OF node, but doesn't probe the device.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-08-21 16:21:37 +02:00
Tom Rini
b71d9e8b38 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-08-20 13:41:56 -04:00
Alexander Graf
122347f366 riscv: Include bss subsections in linker script
When we build with -fdata-sections we may end up with bss subsections. Our
linker script explicitly lists only a single consecutive bss section though.

Adapt the statement to also include subsections.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-08-20 14:25:59 +02:00
Alexander Graf
1acbd0ea99 x86: Enable -fdata-sections always
We left -fdata-sections disabled for x86_64 before because we encountered
random bugs that were at that time inexplicable.

Turns out this really was just side effects of missing .bss* statements
in the linker scripts. With those fixed, we can enable data sections for all
targets.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-08-20 14:20:53 +02:00
Alexander Graf
6331cb2165 x86: Include bss subsections in linker script
When we build with -fdata-sections we may end up with bss subsections. Our
linker script explicitly lists only a single consecutive bss section though.

Adapt the statement to also include subsections.

This fixes booting efi-x86_app_defconfig.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-08-20 14:17:43 +02:00
Icenowy Zheng
7ac5f33483 sunxi: fix sid base address macro name for H6
In the current H6 CPU memory space code, the SUNXI in the macro name of
the SID address base is wrongly spelled as SNUXI, which leads to SID
readout not working.

Fix this macro name.

Fixes: 55f6b1c351c9 ("sunxi: add basic memory map definitions of H6 SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2018-08-20 17:22:59 +05:30
Alexander Graf
18e684dd4c sandbox: Move BSS after EFI sections
Something went wrong when writing the sandbox linker scripts and so we
ended up with a .bss section marker right before the efi runtime sections.

That obviously is a terrible idea, as it may result in overwriting efi
runtime code and data. So let's move the .bss identifier behind the efi
sections.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-08-20 11:39:19 +02:00
Bin Meng
7bdf39cfaf x86: efi: payload: Add default TSC frequency in the device tree
It was observed sometimes U-Boot as the EFI payload fails to boot on
QEMU. This is because TSC calibration fails with no valid frequency.
This adds default TSC frequency in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-20 13:52:49 +08:00
Bin Meng
864915561b x86: coreboot: Add default TSC frequency in the device tree
It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-08-20 13:52:49 +08:00
Bin Meng
1cf6825a68 x86: dts: Remove coreboot_fb.dtsi
There is no need to keep a separate coreboot_fb.dtsi since now we
have a generic coreboot payload dts.

While we are here, this also remove the out-of-date description in
the documentation regarding to coreboot framebuffer driver with
U-Boot loaded as a payload from coreboot. As the testing result with
QEMU 2.5.0 shows, the driver just works like a charm.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-20 13:52:49 +08:00
Bin Meng
6e71a6ab2d x86: Remove support for Advantech SOM-6896
Now that we have generic coreboot payload support, remove the
dedicated support for Advantech SOM-6896.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-08-20 13:52:49 +08:00
Bin Meng
ceeee8f7b5 x86: coreboot: Add generic coreboot payload support
Currently building U-Boot as the coreboot payload requires user
to change the build configuration for a specific board during
menuconfig process. This uses the board's native device tree
to configure the hardware. For example, the device tree provides
PCI address range for the PCI host controller and U-Boot will
re-program all PCI devices' BAR to be within this range. In order
to make sure we don't mess up the hardware, we should guarantee
the range matches what coreboot programs the chipset.

But we really should make the coreboot payload support easier.
Just like EFI payload, we can create a generic coreboot payload
for all x86 boards as well. The payload is configured to include
as many generic drivers as possible. All stuff that touches low
level initialization are not allowed as such is the coreboot's
responsibility. Platform specific drivers (like gpio, spi, etc)
are not included.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-08-20 13:52:06 +08:00
Adam Ford
d7869b2183 Convert CONFIG_MII et al to Kconfig
This converts the following to Kconfig:
   CONFIG_MII
   CONFIG_DRIVER_TI_EMAC

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-17 13:03:54 -04:00
Tom Rini
8297e648b8 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-08-17 07:25:04 -04:00
Tom Rini
719afeb0b3 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-08-17 07:24:34 -04:00
Tom Rini
86cf1c8285 configs: Migrate CONFIG_NR_DRAM_BANKS
We have the following cases:
- CONFIG_NR_DRAM_BANKS was defined, migrate normally
- CONFIG_NR_DRAM_BANKS_MAX was defined and then used for
  CONFIG_NR_DRAM_BANKS after a check, just migrate it over now.
- CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 +
  2), set this to 8.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-16 16:45:02 -04:00
Tom Rini
0bdea7c430 CONFIG_SYS_GENERIC_BOARD: Finish migration
While we have long since migrated to CONFIG_SYS_GENERIC_BOARD being
enabled, we had just a few places left that still referenced or defined
it.  Update.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-08-16 16:45:02 -04:00
Ley Foon Tan
b0c0a715f9 arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-15 12:41:09 +02:00
Marek Vasut
4f10989280 ARM: rmobile: Enable USB PHY on Gen2
Enable support for USB PHY on the R-Car Gen2. This allows for both
of the USB host ports to be used on such boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-08-14 11:31:25 +02:00
Marek Vasut
d81b5da3fe ARM: socfpga: clk: Convert to clock framework
Use clock framework functions to fetch clock information now that there
is a clock driver for Arria10, instead of custom coded register parsing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
ccc97432ad ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodes
Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
f4c3e0dcf5 ARM: socfpga: clk: Drop unused variables on Arria10
The variables removed in this patch are never used, they are only ever
assigned and then waste precious memory. Drop both the assignment and
the variables.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
49e508e962 ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
The L4SP and MMC clock precalculation is specific to Gen5, it is not
needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper
clock driver for Gen5, at which point this will go away completely.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
934aec71d6 ARM: socfpga: clk: Obtain handoff base clock via DM
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
d6a61da462 ARM: socfpga: Remove adhoc ethernet reset and configuration
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
6385a8a964 ARM: socfpga: Zap unused reset code
Remove code from the reset manager that is never called.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00
Marek Vasut
f9edeb32a9 ARM: socfpga: Zap all the UART handling complexity
The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and console framework. Nuke all this comlexity, since it is just
duplicating the same functionality, badly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-08-13 22:35:40 +02:00
Marek Vasut
fe88c2fea7 ARM: socfpga: Enable DM I2C framework on A10
Enable the DM I2C framework on Arria10, so that the DM capable
Designware I2C driver can handle the reset via DM reset framework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:17 +02:00
Marek Vasut
8145c1c299 ARM: socfpga: Enable DM reset framework on A10
Enable the DM reset framework and DM reset driver on Arria10 both
in U-Boot and in SPL. This lets U-Boot parse reset control from DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:17 +02:00
Marek Vasut
c29508045f ARM: dts: socfpga: Add i2c alias to A10 SoCDK
The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign
the I2C bus a bus number. Add the missing alias.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
3d8685f155 ARM: dts: socfpga: Add missing I2C resets
The I2Cx resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
da61e50fc4 ARM: dts: socfpga: Fix Arria10 GMAC resets
Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs
to work and add GMAC2 reset and OCP resets which were missing altogether.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
f5775e69cc ARM: dts: socfpga: Add missing UART resets
The UART0 and UART1 resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
6f96ed7e20 ARM: dts: socfpga: Flag reset manager on A10 as pre-reloc
The Altera reset manager block must be available very early on, since
it controls ie. UART resets. Flag it as pre-reloc.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:16 +02:00
Marek Vasut
af74658e04 ARM: socfpga: Register the FPGA on A10 in SPL again
The restructuring of the SPL dropped registration of the FPGA in SPL,
readd it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Fixes: c859f2a77d ("arm: socfpga: Restructure the SPL file")
2018-08-13 22:35:16 +02:00
Simon Goldschmidt
e4ff8420c5 arm: socfpga: gen5: combine some init code for SPL and U-Boot
Some of the code for low level system initialization in SPL's
board_init_f() and U-Boot's arch_early_init_r() is the same,
so let's combine it into a single function called from both.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 22:35:06 +02:00
Simon Goldschmidt
79a436d568 arm: socfpga: fix device trees to work with DM serial
Device trees need to have the serial console device available
before relocation and require a stdout-path in chosen at least
for SPL to have a console.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 22:35:06 +02:00
Patrick Delaunay
2deaf5cc63 ARM: dts: stm32f4: Fix DT dtc warnings
This patch fix the following warnings for for stm32f429
evaluation and discovery boards:

unnecessary #address-cells/#size-cells without "ranges" or
child "reg" property

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrice Chotard
638ee5af6b ARM: dts: stm32mp157: Add ADC DT node
Add ADC device tree node. This allows to get analog conversions on
stm32mp157.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrice Chotard
6effb56fbc ARM: dts: stm32: remove cd-inverted for stm32f746-disco
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.

Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Patrice Chotard
4c55c83989 ARM: dts: stm32: remove cd-inverted for stm32f769-disco
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.

Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-13 14:04:04 -04:00
Ramon Fried
e0b04a1525 snapdragon: added MAC generation functions
Add support for generation of unique MAC address
that is derived from board serial.
Algorithm for generation of MAC taken from LK.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-13 14:04:04 -04:00
Ramon Fried
86e5e42946 snapdragon: added msm_board_serial() func
This commit adds a function to get the board
serial number.
In snapdragon it's actually the eMMC serial number.

Function added in a new file misc.c that will
include further snapdragon miscellaneous functions.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-13 14:04:04 -04:00
Thomas Fitzsimmons
dc7685e2c5 arm: bcm7445: Fix parallel make race condition
Move the contents of prior_stage.h into bcmstb.h to prevent a build
failure when bcmstb.h is #include'ed before the asm/arch symbolic link
is present.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
2018-08-13 14:03:57 -04:00
Tom Rini
b8a1f47be3 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-08-13 12:34:55 -04:00
Simon Goldschmidt
c0b4fc1a1b arm: socfpga: cyclone5: handle debug uart
If CONFIG_DEBUG_UART is enabled, correctly initialize
the debug uart before console is initialized to debug
early boot problems in SPL.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 15:29:54 +02:00
Simon Goldschmidt
20905f5fa6 arm: socfpga: spl_gen5: clean up malloc_base assignment
In spl_gen5's board_init_f(), gd->malloc_base is manually assigned
at the end of the function to point to sdram.  This code is outdated
as by now, the heap is switched to sdram by the common function
spl_relocate_stack_gd() if the appropriate defines are set.

As it was, the value assigned manually was directly overwritten by
this common code, so remove the manual assignment.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 15:29:54 +02:00
Simon Goldschmidt
40c36f8d49 arm: socfpga: fix SPL on gen5 after moving to DM serial
There were NULL pointers dereferenced because DM was used
too early without correct initialization:
- malloc_simple returned NULL when called from preloader_console_init()
  because gd->malloc_limit was 0
- uclass_add dereferenced gd->uclass_root members which were NULL because
  dm_init (or one of its relatives) has not been called.

All this is fixed by calling spl_early_init before calling
preloader_console_init.

This fixes commit 73172753f4 ("ARM: socfpga: Convert to DM serial")

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-08-13 15:29:54 +02:00
Andre Przywara
8094f0cb0c sunxi: A64: fix default DRAM_ODT_EN symbol
"default" lines in Kconfig are processed in order, the first hit will
stop considering subsequent lines. In the case of the DRAM_ODT_EN symbol
that means that everything following the first two lines will never be
checked:
------------
config DRAM_ODT_EN
	bool "sunxi dram odt enable"
	default n if !MACH_SUN8I_A23
	default y if MACH_SUN8I_A23
	default y if MACH_SUN8I_R40
	default y if MACH_SUN50I
------------

Assuming that the "default y" for the A64 and the R40 were a deliberate
choice, fix the Kconfig stanza to take this into account.
Also remove the now redundant lines from the respective defconfigs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: droped 'default n' on original change]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # A64, R40
Tested-by: Chen-Yu Tsai <wens@csie.org> # A23
2018-08-13 16:47:38 +05:30
Jagan Teki
25b3d90b2c ARM: dts: sun8i: Update R40/V40 dts(i) files from Linux-v4.18-rc3
Update all R40/V40 devicetree dtsi and dtsi files from Linux-v4.18-rc3
with below commit:

R40:
commit c36fd5a48bd20820855e3e91a89297eeaa31836e
Author: Chen-Yu Tsai <wens@csie.org>
Date:   Wed May 2 00:12:25 2018 +0800

    ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable GMAC ethernet controller

V40:
commit c5f0bb472795170ab5c33be12e29ce7465fb31ed
Author: Icenowy Zheng <icenowy@aosc.io>
Date:   Fri Apr 6 22:03:44 2018 +0800

    ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # BPI-M2-Ultra, BPI-M2-Berry
2018-08-13 13:10:09 +05:30
Jagan Teki
0ca4d40cfe ARM: dts: sun8i: Update A83T dts(i) files from Linux-v4.18-rc3
Update all A83T devicetree dtsi and dtsi files from Linux-v4.18-rc3
with below commit:
commit 221cb9fd2ee3042689fe0e6613d0f34eb46a5af6
Author: Mylène Josserand <mylene.josserand@bootlin.com>
Date:   Fri May 4 21:05:44 2018 +0200

    ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

Note: bananapi-m3 and cubietruck-plus board dts files has
usb_otg enabled in U-Boot which were not present in Linux.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-08-13 13:07:35 +05:30
Tom Rini
8fee226da3 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2018-08-11 19:49:29 -04:00
Tom Rini
282ce6454c Merge branch 'master' of git://git.denx.de/u-boot-video 2018-08-11 19:48:13 -04:00
Mario Six
004e67c216 test: Add tests for misc uclass
Add a set of tests for the misc uclass.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-11 16:00:38 +02:00
Mario Six
957983e00b sandbox: Add and build AXI bus and device
Add test AXI drivers to the sandbox.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-11 08:10:07 +02:00
Mario Six
9a8bcabd8a axi: Add AXI sandbox driver and simple emulator
Add test infrastructure and tests for the AXI uclass.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-11 08:09:39 +02:00
Ramon Fried
36adb7c9e8 snapdragon: Add DRAM detection & FDT fixup
Fixup the Linux FDT with the detection of onboard DRAM as
provided by SBL (Secondary boot loader) by reading
the shared-memory region.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-10 13:45:35 -04:00
Ran Wang
9add5a4b75 armv8: layerscape: Enable EHCI access for LS1012A
Program Central Security Unit (CSU) to grant access to USB 2.0
controller.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: rewrite commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:37:39 -07:00
Ran Wang
cd35855492 armv8: layerscape: move ns_dev[] define from h to c file.
Move ns_dev[] from header file to C file to avoid compiling warning
when header file is included by others.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: rewrite commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:36:03 -07:00
Laurentiu Tudor
5651f438f8 armv8: ls1046a: setup SEC ICIDs and fix up device tree
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.

Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:46 -07:00
Laurentiu Tudor
b50ff5e1b6 armv8: ls1046a: setup fman ports ICIDs and device tree
Add support for ICID setting of fman ports and the required device
tree fixups.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:42 -07:00
Laurentiu Tudor
599a97d49c armv8: ls1046a: add icid setup for qman portals
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:36 -07:00
Laurentiu Tudor
3cb4fe65f9 armv8: ls1046a: initial icid setup support
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:33 -07:00
Laurentiu Tudor
703d18f7fe armv8: fsl-layerscape: add missing debug stream ID
Add a define with a value for the missing debug stream ID.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:29 -07:00
Laurentiu Tudor
92d2e89c8c misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:22 -07:00
Laurentiu Tudor
5bdfdb7d4f armv8: ls1046a: advertise QMan v3 in configuration
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:11 -07:00
Laurentiu Tudor
fa0706ef92 armv8: fsl-layerscape: add missing register blocks base address defines
Add defines for the edma and qdma register block base addresses.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:34:42 -07:00
Patrick Delaunay
8e1665102f stm32mp1: add gpio led support
This patch add the 4 LED available on the ED1 board and activated
gpio led driver.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-08-10 10:27:32 -04:00
Tom Rini
cdec3ea7e4 Merge branch 'master' of git://git.denx.de/u-boot-usb 2018-08-10 07:21:02 -04:00
Tom Rini
b243f41f12 Merge git://git.denx.de/u-boot-dm 2018-08-09 11:10:41 -04:00
Tom Rini
9d17682a57 Merge branch 'master' of git://git.denx.de/u-boot-mips 2018-08-08 20:02:39 -04:00
Alberto Panizzo
f68c8e827c usb: rockchip: implement K_FW_LBA_ERASE_10 command
This command is part of the write partition sequence performed by
rkdeveloptool: one partition is first completely erased and
than wrote.

Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 22:22:07 +02:00
Alberto Panizzo
e11f9166f3 usb: rockchip: implement K_FW_LBA_READ_10 command
This patch implement reading blocks form selected device with
LBA addressing.

Corresponding command on workstation is:
rkdeveloptool rl <start_blk> <blk_cnt> <file>

While we support reading more than one blocks per K_FW_LBA_READ_10
request, rkdeveloptool and original rockchip tool do perform
chunk reads limiting the maximum size per chunk far lower
than max int values.

Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 22:22:07 +02:00
Bin Meng
95e11069b5 test: dm: pci: Add cases for finding PCI capability APIs
Add several PCI capability and extended capability ID registers
in the swap_case driver, so that we can add test case for
dm_pci_find_capability() and dm_pci_find_ext_capability().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
3ed214ac9b test: dm: pci: Add tests for mixed static and dynamic devices on the same bus
In the Sandbox test configuration, PCI bus#0 only has static devices
while bus#1 only has dynamic devices. Create a bus#2 that has both
types of devices and test such.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
490d13a523 sandbox: Update test.dts for dynamic PCI device driver matching
At present we have two PCI buses in the test configuration. Both
buses have static device-tree config devices. Now we switch the
2nd bus to use dynamic PCI devices for testing.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
59a160e8b9 pci: sandbox: swap_case: Declare dynamic driver matching
This adds a U_BOOT_PCI_DEVICE() declaration to the swap_case driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
dee4d752be test: dm: pci: Test more than one PCI host controller
So far there is only one PCI host controller in the sandbox test
configuration. This is normally the case for x86, but it can be
common on other architectures like ARM/PPC to have more than one
PCI host controller in the system.

This updates the case to cover such scenario.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
2db7f2b722 test: dm: pci: Test more than one device on the same bus
It's quite common to have more than one device on the same PCI bus.
This updates the test case to test such scenario.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Philippe Reynes
990cebf0a2 bcm968380gerg: add initial support
This add the initial support of the broadcom reference
board bcm968380gerg with a bcm68380 SoC.

This board has 512 MB of RAM, 128 MB of flash (nand),
2 USB port, 1 UART, 4 ethernet ports and BCM43217 (wifi).

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-08-08 13:38:17 +02:00
Philippe Reynes
341032d3f1 bcm6838: add initial support
This adds the initial support of the Broadcom BCM6838 SoC familly,
only cpu, dram, uart and leds are supported.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-08-08 13:38:17 +02:00
Tom Rini
481ea2e39d mips: au1x00: Remove support for these SoCs
The only platform left for the AU1x00 SoCs was the pb1x00 platform, an
apparent clone of the dbau1x00 platform.  As pb1x00 had no listed
maintainer I am assuming that it is also orphaned.  Remove this platform
and then remove the unused SoC support.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-08-08 13:34:27 +02:00
Tom Rini
215b4fae51 mips: dbau1x00: Remove this board
This platform has been marked as orphan since June of 2016 and should
have been removed some time ago.  Do so now.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-08-08 13:33:51 +02:00
Tom Rini
fc82e7684b Merge branch 'master' of git://git.denx.de/u-boot-samsung 2018-08-07 21:36:20 -04:00
Brendan Shanks
e784cf1bf2 arm: ls102xa: Fix RGMII phy-connection-type FDT fixup
In ft_fixup_enet_phy_connect_type(), use strlen() instead of sizeof()
on the pointer result of phy_string_for_interface(). sizeof() was
returning the size of the pointer (4 bytes), resulting in the
phy-connection-type being set to "rgmi" rather than "rgmii-id".

Signed-off-by: Brendan Shanks <brendan.shanks@teradek.com>
Cc: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-07 14:42:15 -07:00
Tom Rini
188ebc7b59 Xilinx fixes for v2018.09-rc2
xilinx:
 - Add support for zybo z7 and ultra96
 - Tune zynq and zynqmp mini configurations
 - Move SYS_MALLOC_LEN to Kconfig
 
 fdt
  - make static funcs
 
 gpio:
 - Fix soft gpio driver
 - Fix Zynq gpio driver by using platdata
 
 microblaze:
 - Fix Kconfig entry
 
 spi
 - Move ISSI to Kconfig
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Merge tag 'xilinx-for-v2018.09-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx fixes for v2018.09-rc2

xilinx:
- Add support for zybo z7 and ultra96
- Tune zynq and zynqmp mini configurations
- Move SYS_MALLOC_LEN to Kconfig

fdt
 - make static funcs

gpio:
- Fix soft gpio driver
- Fix Zynq gpio driver by using platdata

microblaze:
- Fix Kconfig entry

spi
- Move ISSI to Kconfig
2018-08-07 11:32:50 -04:00
Luis Araneda
a492fdffa3 arm: zynq: dts: add spi flash node to zedboard
Add a flash node to fix the detection of the memory IC.
With the changes introduced with commit 8fee8845e7
("enf_sf: reuse setup_flash_device instead of open coding it")
the SPI speed is now read from device-tree or a default value
is applied. This replaced the old behavior of setting the
SPI speed to CONFIG_ENV_SPI_MAX_HZ.

As this board didn't have a flash node, the default value
was applied to the SPI speed, producing an error when probing
the flash memory (speed too slow).

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-07 11:03:43 +02:00
Chris Packham
a6477f7cbc ARM: kirkwood: add SBx81LIFXCAT board
This is a series of line cards for Allied Telesis's SBx8100 chassis
switch. The CPU block is common to the SBx81GP24 and SBx81GT24 cards
cards collectively referred to as SBx81LIFXCAT in u-boot.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Jon Nettleton
14deee2081 arm: mvebu: clearfog: add u-boot, dm-spl tag for spi
This is required so SPL and u-boot can boot from spi
flash devices that use the dm drivers.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
[baruch: use -u-boot.dtsi]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Baruch Siach
69601ce003 arm: mvebu: helios4: remove duplicate sdhci pins node
The same pinctrl node appears in the solidrun-microsom dtsi. Use that
instead.

Cc: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Dennis Gilmore <dennis@ausil.us>
Tested-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Jon Nettleton
334eebefc2 arm: mvebu: Better align Clearfog dts file with Linux kernel
This makes changes so the u-boot dts file is structured more
similar to the mainline linux dtsi file.  It provides a minimal
common dts that can work for most boards based on the ClearFog
platform.  Ethernet support is only supported for eth0 however
all devices are left enabled so u-boot can generate and
provide mac addresses for all of the network interfaces.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
[baruch: rebase on recent changes]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Dennis Gilmore <dennis@ausil.us>
Tested-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Baruch Siach
a4adb1f576 arm: mvebu: clearfog: use the microsom .dtsi
Use hardware description from the recently introduced microsom .dtsi
file to reduce duplication.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Dennis Gilmore <dennis@ausil.us>
Tested-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Baruch Siach
bf3eaa3e5c arm: mvebu: solidrun-microsom: update SPI flash compatible
Add the "spi-flash" compatible string so that the generic sf_probe
driver can probe the SPI flash on the SolidRun SOM.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-07 10:53:52 +02:00
Baruch Siach
72c4e67d08 mvebu: support UART boot image
The kwboot utility can use the generated image to boot mvebu SoCs from
UART.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06 14:07:23 +02:00
Baruch Siach
ca1a4c8632 mvebu: select boot device at SoC level
Move the gdsys Controlcenter DC specific build time kwbimage.cfg
generation code into the mach-mvebu/ directory to be shared by all 32bit
mvebu platforms.

Remove board specific kwbimage.cfg files, and use the generated one
instead. These files are all identical, with two exceptions. Clearfog
and Helios4 use the sdio boot device, whereas all others use spi. Update
the defconfigs for the exceptional boards to generate the same
kwbimage.cfg as before.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06 14:07:23 +02:00
Baruch Siach
ad105f5f86 mvebu: consolidate SPL boot device config symbols
Use MVEBU_SPL_BOOT_DEVICE_* to select between SPI and MMC, instead of
board specific symbols. This commit enables the boot device selection
menu to all mvebu platforms, but it is only effective on Turris Omnia
and gdsys Controlcenter DC platforms. A following commit will enable
boot selection for other platforms.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06 14:07:23 +02:00
Baruch Siach
d38f04f7c2 mvebu: a38x: drop duplicate platform id symbols
Use generic mvebu Kconfig symbols like all other mvebu boards.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-08-06 14:07:23 +02:00
Michal Simek
2570e12960 arm64: zynqmp: Add support for Avnet Ultra96
Avnet Ultra96 is rebranded Xilinx zcu100 revC/D. Add new defconfig files
and point to origin internal board name.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Luis Araneda
58f449676a arm: zynq: add support for the zybo z7 board
The board is manufactured by Digilent
Main features:
- Soc: XC7Z010 (Z7-10) or XC7Z020 (Z7-20)
- RAM: 1 GB DDR3L
- FLASH: 16 MB QSPI
- 1 Gbps Ethernet
- USB 2.0
- microSD slot
- Pcam camera connector
- HDMI Tx and Rx
- Audio codec: stereo out, stereo in, mic
- 5 (Z7-10) or 6 (Z7-20) Pmod ports
- 6 push-buttons, 4 switches, 5 LEDs
- 1 (Z7-10) or 2 (Z7-20) RGB LEDs

Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Siva Durga Prasad Paladugu
01aa5b8f05 Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq
This patch moves the the config SYS_MALLOC_LEN to
Kconfig. It will be just for Zynq arch and to do
will be for all other archs.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Michal Simek
df09969070 arm: zynq: Fix indentation for zynq-cse targets
Trivial DT style fixes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Michal Simek
7996fcca9d arm: zynq: Remove fclk-enable property for cse-nor target
Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Michal Simek
92226b5a6d arm: zynqmp: Fix sdhci clock in emmc1 mini configuration
Add missing clocks property with fix clock-names property to be aligned
with emmc0 configuration and binding doc.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Minkyu Kang
972d8576d2 arm: spring: fix alias of mmc correctly
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06 11:24:48 +09:00
Minkyu Kang
2f43135551 arm: exynos5: fix warning of dts
remove this warning: avoid_unnecessary_addr_size

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06 11:24:45 +09:00
Minkyu Kang
8d93a31014 arm: exynos4: fix warning of dts
remove this warning: avoid_unnecessary_addr_size

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2018-08-06 11:24:42 +09:00
Tom Rini
0cba6e906a Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-08-04 19:41:30 -04:00
Patrice Chotard
11c1b55827 ARM: dts: stm32: remove cd-inverted for stm32429i-eval
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.

Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-08-03 19:53:54 -04:00
Andre Przywara
1416e2d225 armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.

On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.

Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03 19:53:54 -04:00
Andre Przywara
15b6184971 armv8: Reduce exception handling code
The arm64 exception handling code is quite big, mostly due to
architectural alignment requirements. Each exception entry spans 32
instructions, which sounds generous, but is too small to fit all of the
save/branch/restore code in there. So at the moment we use only four
instructions, branching into shared save and restore routines.
To not leave the space for those remaining 28 instructions wasted, let's
split the save and restore routines and stuff them into the gaps.
This saves about 250 bytes of code, which is helpful for those tight
SPLs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03 19:53:54 -04:00
Fabrice Gasnier
1fe243a1e4 clk: add clk_valid()
Add clk_valid() to check for optional clocks are valid.
Call clk_valid() in test/dm/clk.c and add relevant test routine to
sandbox clk tests.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-03 19:53:10 -04:00
Tom Rini
a30691a538 Merge git://git.denx.de/u-boot-dm 2018-08-03 10:08:13 -04:00
Stephen Warren
a839c3641e ARM: tegra: align carveout size
Align the size of the carveout region to 2M. This ensures that the size
can be accurately represented by an LPAE page table that uses sections.

This solves a bug (hang at boot time soon after printing the DRAM size)
that only shows up when the following two commits are merged together:
d32e86bde8 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported
6e584e633d ARM: tegra: avoid using secure carveout RAM

Cc: Mark Kettenis <kettenis@openbsd.org>
Cc: Alexander Graf <agraf@suse.de>
Acked-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2018-08-01 20:06:10 -04:00
Simon Glass
3ab9598df7 binman: Rename 'position' to 'offset'
After some thought, I believe there is an unfortunate naming flaw in
binman. Entries have a position and size, but now that we support
hierarchical sections it is unclear whether a position should be an
absolute position within the image, or a relative position within its
parent section.

At present 'position' actually means the relative position. This indicates
a need for an 'image position' for code that wants to find the location of
an entry without having to do calculations back through parents to
discover this image position.

A better name for the current 'position' or 'pos' is 'offset'. It is not
always an absolute position, but it is always an offset from its parent
offset.

It is unfortunate to rename this concept now, 18 months after binman was
introduced. However I believe it is the right thing to do. The impact is
mostly limited to binman itself and a few changes to in-tree users to
binman:

   tegra
   sunxi
   x86

The change makes old binman definitions (e.g. downstream or out-of-tree)
incompatible if they use the 'pos = <...>' property. Later work will
adjust binman to generate an error when it is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-08-01 16:30:06 -06:00
Tom Rini
61523dde17 Merge tag 'arc-updates-for-2018.09-rc2' of git://git.denx.de/u-boot-arc
That's a set of prety minor changes and fixes for ARC.

Among them:
 * Improvement in CREG GPIO driver used on ARC dev boards
   that allow us to re-use the driver for SPI's chip select

 * Enable SPI-flsh on AXS10x boards which allows to update
   U-Boot binary that gets loaded by boot-ROM

 * Fix accommodating always utilized unaligned access by
   GCC for ARC starting from 8.1.0
2018-08-01 09:26:15 -04:00
Michal Simek
b3815fc4e5 dm: Fix CMD_DM enabling
The patch "dm: Change CMD_DM enabling"
(sha1: 08a00cba06) was incorrectly updated
and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice.
This patch is fixing it.

Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-31 14:46:22 -04:00
Jagan Teki
89a897fc4d board: sun50i: h6: Add OrangePi One Plus initial support
OrangePi One Plus is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- 1Gbps GMAC via RTL8211
- USB 2.0 Host, OTG
- HDMI port
- 5V/2A DC power supply

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-07-31 20:50:01 +05:30
Icenowy Zheng
a8407b5642 sunxi: add support for Pine H64 board
Pine H64 is a SBC with Allwinner H6 SoC produced by Pine64. It features
1GiB/2GiB/4GiB(3GiB usable) DRAM, two USB 2.0 ports, one USB 3.0 port
and a mPCIE slot.

Add support for it.

The device tree is from Linux next-20180720.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
6f796a9bb4 sunxi: add support for Allwinner H6 SoC
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe
interfaces.

This patch adds support for it.

The corresponding DTSI file, from Linux next-20180720, is also
introduced.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
da2616543a sunxi: add DRAM support to H6
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo.
Both the controller and the PHY seem to be originate from DesignWare,
and are similar to the ones in ZynqMP SoCs.

This commit introduces an initial DRAM driver for H6, which contains
only LPDDR3 support. The currently known SBCs with H6 all come with
LPDDR3 memory, including Pine H64 and several Orange Pi's.

The BSP DRAM initialization code is closed source and violates GPL. Code
in this commit is written by experimenting, referring the code/document
of other users of the IPs (mainly the ZynqMP, as it's the only found PHY
reference) and disassebling the BSP blob.

Thanks for Jernej Skrabec for review and fix some issues in this driver
(including the most critical one which made it to work), and rewrite
some code from register dump!

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
42956f1b85 sunxi: add MMC support for H6
The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
the MMC2 come with the capability to do crypto by EMCE.

Add MMC support for H6. EMCE support is not added yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
7f51a4020e sunxi: add UART0 setup for H6
The UART0 on H6 is available at PH bank (and PF bank, but the PF one is
muxed with SD card).

Add pinmux configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
10196c9627 sunxi: use sun6i-style watchdog for H6
The H6 SoC has a sun6i-style watchdog in its timer part.

Enable the usage of it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
0558676d4b sunxi: add clock code for H6
The new Allwinner H6 SoC has a brand new CCU layout.

Add clock code for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
80197801f4 sunxi: change RMR64's RVBAR address for H6
Allwinner H6 has a different RVBAR address with A64/H5.

Add conditional RVBAR configuration into the code which does RMR switch.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
e77b7496c6 sunxi: add basic memory map definitions of H6 SoC
The Allwinner H6 SoC come with a totally new memory map.

Add basical definition of the new memory map into a header file, and let
the cpu.h header include it in the situation of H6.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
cadc7c20e5 sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS
The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but
it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored
to support this new configuration.

Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM
A1 in the memory map.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Alexey Brodkin
8f590063ba ARC: Enable unaligned access in hardware if compiler uses it
Even if ARC core might handle unaligned access to data this
hardware feature by default is disabled.

But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores.
Which leads to quite strange and fatal run-time failures like the one
below if HW is not configured properly:
| hsdk# sf probe
| Misaligned data access exception @ 0xbff794d4
| ECR:    0x000d0000
| RET:    0xbff794d4
| BLINK:  0xbff79644
| STAT32: 0x00000800
| GP: 0x1003e000   r25: 0xbfd58f08
| BTA: 0xbff794a4  SP: 0xbfd58cd4  FP: 0xbfd58ef0
| LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000
| r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf
| r03: 0x00000000 r04: 0x00000100 r05: 0x00000000
| r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500
| r09: 0x00000000 r10: 0x00200000 r11: 0x00000000
| r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68
| r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000
| r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40
| r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000
| r24: 0xbfd59ba8
| Resetting CPU ...

Now we're checking for __ARC_UNALIGNED__ define emitted by the
compiler if it's going to use unaligned access and then we
force-enable it in hardware too.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Eugeniy Paltsev
cdfe6913c1 AXS10x: add spi flash support
AXS10x boards have n25q512 spi flash IC, so add corresponding
nodes to device tree and enaple corresponding options in
defconfig.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Eugeniy Paltsev
fe3eb7a887 GPIO: CREG: improve flexibility of hsdk-creg-gpio driver
CREG GPIO is a driver for weird soc-specific output ports, which are
controlled by some fields in memory mapped register.

Example:

31                 9        7        5           0   < bit number
|                  |        |        |           |
[     not used     | gpio-1 | gpio-0 | <-shift-> ]   < 32 bit register
                       ^        ^
                       |        |
                write 0x2 == set output to "1" (activate)
                write 0x3 == set output to "0" (deactivate)

As of tooday we only support fixed (hardcoded) bit per gpio line,
activate / deactivatei and shift values. Fix that by read them from
device tree to be able to use this driver for other boards.

Remove "hsdk" prefix from compatible string as this driver can be
used with different boards like HSDK, AXS101, AXS103, etc.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Tom Rini
406fd7e207 Patch queue for efi - 2018-07-25
Highlights this time:
 
   - Many small fixes to improve spec compatibility (found by SCT)
   - Almost enough to run with sandbox target
   - GetTime() improvements
   - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-07-25

Highlights this time:

  - Many small fixes to improve spec compatibility (found by SCT)
  - Almost enough to run with sandbox target
  - GetTime() improvements
  - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
2018-07-30 16:02:29 -04:00
Michal Simek
58008cbab5 Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:48 -04:00
Michal Simek
08a00cba06 dm: Change CMD_DM enabling
CMD_DM is used for debug purpose and it shouldn't be enabled by default
via Kconfig. Unfortunately this is in the tree for quite a long time
that's why solution is to use imply DM for all targets which are
enabling DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:48 -04:00
Michal Simek
5ed063d10f Kconfig: Sort bool, default, select and imply options
Fix Kconfig bool, default, select and imply options to be
alphabetically sorted.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-07-30 07:18:48 -04:00
Michal Simek
6e7bdde4fe Kconfig: Replace spaces with tabs and missing newline
Trivial Kconfig cleanup. Use tabs instead of spaces and every Kconfig
entry should be separated by newline.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:47 -04:00
Tom Rini
0e8a8a3110 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-07-27 13:09:30 -04:00
Tom Rini
53885e76ce Merge branch 'master' of git://git.denx.de/u-boot-tegra 2018-07-26 23:12:39 -04:00
Tom Warren
2eea126916 tegra: beaver/apalis: Fix DTC warning
Fix warning when compiling tegra30-beaver/-apalis.dts with latest DTC:

  "Warning (avoid_unnecessary_addr_size): /pci/pch@1f,0: unnecessary
   #address-cells/#size-cells without "ranges" or child "reg" property"

Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:31 -07:00
Stephen Warren
6e584e633d ARM: tegra: avoid using secure carveout RAM
If a secure carveout exists, U-Boot cannot use that memory. Fix
carveout_size() to reflect this, and hence transitively fix
usable_ram_size_below_4g() and board_get_usable_ram_top(). This change
ensures that when U-Boot copies the secure monitor code to install it, the
copy target is not in-use for U-Boot code/data.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:30 -07:00
Stephen Warren
74c69cdcc0 ARM: PSCI: Enable the PSCI node
When fixing up the DT to report PSCI support, explicitly enable the node.
DTs may ship with the node disabled in case a PSCI implementation is not
present, and expect any PSCI implementation to enable the node if they are
actually present.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:30 -07:00
Stephen Warren
326bd726d0 ARM: PSCI: Support PSCI v0.2
Enhance the PSCI DT editing code to allow setting a PSCI v0.2 compatible
value in the DT. The CONFIG_ option is added to the whitelist to match the
existing PSCI_1_0 option. While not adding new options to Kconfig isn't
ideal, I figure it's better to keep related options together.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:30 -07:00
Stephen Warren
3e3b2b4776 ARM: define MON_MODE
Add a MON_MODE define for ARM's monitor mode. This can be used later by
a secure monitor to avoid hard-coding mode IDs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:30 -07:00
Bibek Basu
3cc7942a4a ARM: tegra: implement RAM repair
RAM repair has a few pre-requisites:
1) PMIC power supply (rail) enabled.
2) PMC CRAIL power partition powered.
3) Fuse clock active (it's the default).
4) PLLP reshift branch enabled (it's the default, when PLLP is active).

RAM repair also only need run whenever specific partitions are powered
(main SoC and CCPLEX respectively); RAM repair does not need to be
triggered when any other partition changes state.

start_cpu() needs to be re-ordered slightly to match these requirements.
Note that C0NC and CE0 aren't required for RAM repair to
operate, but they also do no harm, so the entire of powerup_cpus() is
moved rather than splitting it up. The call to remove_cpu_resets() is
moved last to ensure that all other actions complete before releasing
reset; since the PMC power partitions are now enabled early, releasing
reset is what causes the CPUs to start executing code, and RAM repair must
complete before the CPU boots.

Note that this commit is the result of squashing a numbmer of commits
in NVIDIA's downstream L4T branch, hence the multiple signoffs below.

Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Signed-off-by: Sandipan Patra <spatra@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:29 -07:00
Stephen Warren
daebd48fe8 Revert "tegra: Introduce SRAM repair on tegra124"
This reverts commit 701b7b1d2c. It will
be immediately replaced by a different implementation that is more
complete and runs are more targetted times.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-07-26 13:15:29 -07:00
Tom Rini
a57d45db90 Merge branch 'master' of git://git.denx.de/u-boot-net 2018-07-26 15:55:42 -04:00
Joe Hershberger
9cce566321 arm: Prevent redefinition error in fsl-layerscape
The include/phy.h will start including dm.h, which pulls in
linux/compat.h after the attempted redefinition in
arch/arm/include/asm/armv8/mmu.h, so move this include to allow
redefinition.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:21 -05:00
Joe Hershberger
f40a31e695 sandbox: eth-raw: Add a SIMPLE_BUS to enumerate host interfaces
Ask the OS for each of its interfaces and for each one, bind a U-Boot
device and then probe it. This will allocate the priv data structure
that is then populated.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:19 -05:00
Joe Hershberger
c9e2caff85 sandbox: eth-raw: Allow interface to be specified by index
With systemd stable interface names, eth0 will almost never exist.
Instead of using that name in the sandbox.dts, use an index.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
ac13270b49 sandbox: eth-raw: Add a function to ask the host about localhost
Instead of doing a simple string compare against "lo", look for the flag
that indicates a localhost interface.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
8c7988b6db net: sandbox-raw: Convert raw eth driver to livetree
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
50ed0ef832 sandbox: eth-raw: Make sure descriptors are always initialized
If we let descriptors equal 0, we can end up closing STDIN. Make sure
they start out as -1.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:17 -05:00
Joe Hershberger
c6fa51a499 sandbox: Fix format of fake-host-hwaddr in test.dts
test.dts specified the fake MAC address as a u32 array. Instead it
should be a u8 array.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:17 -05:00
Joe Hershberger
97367df109 sandbox: eth-raw: Correct valid socket test in send/recv
In open, the socket is correctly checked to be -1 in the error case.
In send and recv, we checked for 0, but that is a valid socket number.

Correct this by checking for -1 as a bad socket everywhere.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:17 -05:00
York Sun
038b965c2b armv8: ls1046ardb: Add falcon mode for for QSPI boot
A new defconfig is introduced to support SPL boot from QSPI NOR
flash. This is to support falcon mode for faster booting into
Linux.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 11:51:23 -07:00
York Sun
9960609275 armv8: layerscape: spl: Initialize QSPI AHB for QSPI boot
To get full access of QSPI space, initialize AHB interface.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Yuantian Tang
86bff2bb09 armv8: dts: fsl-ls1012a: add sata node support
One ls1012a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Yuantian Tang
ed167eb1c7 armv8: fsl: remove sata support
Remove the old implementation in order to enable DM for sata.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
York Sun
61ab8aac60 armv8: layerscape: Enabled I-cache for SPL boot
Enable I-cache for SPL boot to boost performance. Earlier MMU was
enabled only for LS2080A and has since been dropped by commit
f539c8a4a7 ("armv8: ls2080a: Drop early MMU for SPL build").

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Tom Rini
ff6bef4852 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-07-26 11:43:26 -04:00
Tom Rini
de4b4ef36f Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-07-26 11:43:23 -04:00
Alexander Graf
42a3d42688 x86: Add efi_loader bits to x86_64 linker script
The x86_64 linker script was missing efi runtime information. Add it.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:44 +02:00
Alexander Graf
7e21fbca26 efi_loader: Rename sections to allow for implicit data
Some times gcc may generate data that is then used within code that may
be part of an efi runtime section. That data could be jump tables,
constants or strings.

In order to make sure we catch these, we need to ensure that gcc emits
them into a section that we can relocate together with all the other
efi runtime bits. This only works if the -ffunction-sections and
-fdata-sections flags are passed and the efi runtime functions are
in a section that starts with ".text".

Up to now we had all efi runtime bits in sections that did not
interfere with the normal section naming scheme, but this forces
us to do so. Hence we need to move the efi_loader text/data/rodata
sections before the global *(.text*) catch-all section.

With this patch in place, we should hopefully have an easier time
to extend the efi runtime functionality in the future.

Signed-off-by: Alexander Graf <agraf@suse.de>
[agraf: Fix x86_64 breakage]
2018-07-25 14:57:44 +02:00
Alexander Graf
dae73c4cdc elf: Move x86 reloc defines to common elf.h
We need to know about x86 relocation definitions even in cases where
we don't officially build against the x86 target, such as with sandbox.

So let's move the x86 definitions into the common elf header, where all
other architectures already have them.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:43 +02:00
Mark Kettenis
d32e86bde8 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported
ARMV7_LPAE is required in order to enable the MMU in HYP mode.
And we really want to enable the MMU in HYP mode such that we can
enable the the caches.  Otherwise U-Boot code (such as the EFI
implementation) that runs in HYP mode will run at a snils pace.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:43 +02:00
Mark Kettenis
907ee2945e ARM: HYP/non-sec: migrate stack
The current code that switches into HYP mode doesn't bother to set
up a stack for HYP mode.  This doesn't work for EFI applications
as they expect a usable stack.  Fix this by migrating the stack
pointer from SP_svc to SP_hyp while in Monitor mode.
This restores the stack pointer when we drop into HYP mode.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:43 +02:00
Masahiro Yamada
7ef5b1e7ed ARM: uniphier: enable distro boot
Switch to the distro boot for UniPhier platform.

 - Remove the environment vairalbes used to load images from raw
   block devices.

 - Keep the command to download images via tftp.  This will be
   useful to boot the kernel when no valid kernel image is ready
   yet in the file system.

 - Use root.cpio.gz instead of root.cpio.uboot because we always know
   the file size of the init ramdisk; it is loaded via either a file
   system or network.

 - Rename fit_addr_r to kernel_addr_r, which the distro command
   checks to get the load address of FIT image.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-25 08:47:53 +09:00
Masahiro Yamada
bb04d2ec4d ARM: uniphier: support fdt_fixup_mtdparts
Propagate the "mtdparts" environment variable to the DT passed
in to OS.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-25 08:47:53 +09:00
Masahiro Yamada
65fce76301 ARM: uniphier: split ft_board_setup() out to a separate file
Prepare to add more fdt fixup code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-25 08:47:53 +09:00
Masahiro Yamada
e968715302 ARM: uniphier: clean-up ft_board_setup()
The 'bd' is passed in ft_board_setup() as the second argument.
Replace 'gd->bd' with 'bd'.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-25 08:47:53 +09:00
Marek Vasut
a6759e3dfc ARM: rmobile: gen2: Enable ACTLR[0] (Enable invalidates of BTB) to facilitate CVE_2017-5715 WA in OS
Enable CVE_2017_5715 mitigation on CPU0 on R-Car H2, M2W, M2N, V2H,
which all contain Cortex-A15 cores. R-Car E2 contains only Cortex-A7
cores and is not affected. Without this enabled, Linux kernel reports:

  CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable

With this enabled, Linux kernel reports:

  CPU0: Spectre v2: using ICIALLU workaround

NOTE: This by itself does not enable the workaround for other CPUs
      than CPU0 and may require additional kernel patches for the
      other CPUs in SMP configurations.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-07-25 00:14:19 +02:00
Marek Vasut
64eeb15854 ARM: dts: socfpga: Adjust NAND register layout on Arria10
Adjust the NAND register size on Arria10 to reflect reality.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-25 00:13:32 +02:00
Marek Vasut
42f4b83b52 ARM: socfpga: Init missing security policies on A10
The Arria10 requires proper configuration of the NOC firewall, otherwise
the access to certain areas of the LWHPS bridge fails in Linux. Add the
missing setup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-25 00:13:32 +02:00
Marek Vasut
937db7188e ARM: socfpga: Assure correct CPACR configuration
Make sure the ARM CPACR register is zeroed out, this is mandatory
on Arria10.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-07-25 00:13:32 +02:00
Ley Foon Tan
00057eea66 arm: socfpga: Fixes: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET
Commit bfc6bae8fa

This commit rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET. Update
with new CONFIG name and enable CONFIG_SPL_DM_RESET when CONFIG_DM_RESET is enabled.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
2018-07-25 00:13:32 +02:00
Adam Ford
d7cc15bb53 ARM: DTS: am3517-evm-u-boot: Mark MMC1 with cd-inverted
In order to use the device tree for MMC, the card-detect pin
needs to be inverted.  This patch places this into the
am3517-evm-u-boot.dtsi file to keep the main DTS and DTSI files
clean and in-sync with Linux

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
972edd4930 ARM: dts: am3517-evm-uboot: Add reg-shift for UART
With the resync of the omap3.dtsi file, the reg-shift was removed
so it breaks the UART.  Adding the reg-shift into the
am3517-evm-u-boot.dtsi keeps the reg-shift for U-Boot, but keeps
the dts/dtsi files clean from Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
5448ff33f2 ARM: DTS: Resync Logic PD SOM-LV 37xx devkit with Linux 4.18-RC4
There have been some significant changes to the DM37 SOM-LV device
tree.  This patch re-syncs it with Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
e6ea2390cd ARM: DTS: Resync LogicPD-Torpedo-37xx-devkit with Linux 4.18-RC4
There have been some refactoring of the DTS files for the Logic PD
DM37 Torpedo.  This patch re-sync's the DTS files with Linux

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
66dae3bbca ARM: dts: Resync OMAP3 and omap36xx with Linux 4.18-RC4
There have been several minor changes to the OMAP3.dtsi, so this
patch re-syncs it with Linux.  An addition include/dt-binding was
also brought with it.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Adam Ford
b8dbec5fb6 ARM: DTS: Resync am3517-evm.dts with Linux 4.18-rc4
Several changes have been made to the AM3517-evm and the underlying
am3517.dtsi file.  This patch re-sync's the DTS and DTSI files with
Linux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Tom Rini
b740074ac4 m68k: m5253evbe: Remove this board
The m5253evbe board has been marked as orphan since June of 2014 and
should have been dropped a while ago.  Do so now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-07-23 14:33:21 -04:00
Martin Kaiser
0d38a5fd44 mx25: fix the offset between the USB ports' registers
The USBOH module on imx25 chips contains two USB controllers which are
called USB OTG Controller and USB Host Controller. Each one has its EHCI
root hub. The OTG Controller's EHCI registers start at offset 0, the Host
Controller's registers start at offset 0x400.

We set CONFIG_MXC_USB_PORT=0 to select the OTG Controller and 1 for the
Host Controller. Therefore, IMX_USB_PORT_OFFSET must be 0x400. Using
this setting, the Host Controller starts working on my imx25 board.

Please note that the imx25 reference manual claims that the Host
Controller's registers start at 0x200. This is not correct. The Linux
Kernel uses the correct offset 0x400 in imx25.dtsi.

Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-07-23 11:05:04 +02:00
Adam Ford
bbbb50f9fd imx: i.mx6q: imx6q_logic: Migrate to SPL and enable SDP
Since the vast majority of i.MX6 boards are migrating to SPL,
this patch converts im6q_logic to SPL and enables the SDP for
loading SPL and u-boot.img over USB.  The Falcon mode only
supports NAND flash as of now due to limited space/RAM, but
all i.MX6D/Q SOM's from Logic PD have internal NAND from which
to boot.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 11:03:20 +02:00
Fabio Estevam
d5b7177f91 pico-imx7d: Add SPL support
Convert pico-imx7d to SPL support.

There are two variants of pico-imx7d SOMs:
- One with 512MB of RAM
- One with 1GB of RAM

The 512MB module contains two Hynix H5TC2G63GFR-PBA.
The 1GB module contains two Hynix H5TC4G63GFR-PBA.

The RAM size is determined in runtime by reading GPIO1_12.

While at it, also add USB Serial Download mode support as it
is very helpful for loading SPL and u-boot.img via imx_usb_loader.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2018-07-23 10:59:48 +02:00
Mark Jonas
9ea7519383 arm, imx6: add alternative PAD_CTL_DSE constants
Not all i.MX6 pads use the same drive strength table. So far only the
240 Ohm to 34 Ohm table was available. Because the constants used have
speaking names it can be confusing to use e.g. PAD_CTL_DSE_48ohm when
according to the reference manual 52 Ohm is the correct value. This
patch adds the 260 Ohm to 37 Ohm table.

For example, the IOMUXC_SW_PAD_CTL_PAD_SD2_CLK register (SD-card clock)
uses the added table.

Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-07-23 10:57:39 +02:00
Stefan Agner
f97df68898 imx: mx7: psci: implement MIGRATE_INFO_TYPE
Implement MIGRATE_INFO_TYPE. This informs Linux that no migration
for the trusted operating system is necessary:
  [    0.000000] psci: Trusted OS migration not required

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:54:32 +02:00
Stefan Agner
28a5af11f8 imx: mx7: psci: support CPU0 on/off
So far psci_cpu_(on|off) only worked for CPU1. Allow to control
CPU0 too. This allows to run the Linux PSCI checker successfully:
  [    2.213447] psci_checker: PSCI checker started using 2 CPUs
  [    2.219107] psci_checker: Starting hotplug tests
  [    2.223859] psci_checker: Trying to turn off and on again all CPUs
  [    2.267191] IRQ21 no longer affine to CPU0
  [    2.293266] Retrying again to check for CPU kill
  [    2.302269] CPU0 killed.
  [    2.311648] psci_checker: Trying to turn off and on again group 0 (CPUs 0-1)
  [    2.354354] IRQ21 no longer affine to CPU0
  [    2.383222] Retrying again to check for CPU kill
  [    2.392148] CPU0 killed.
  [    2.398063] psci_checker: Hotplug tests passed OK
  [    2.402910] psci_checker: Starting suspend tests (10 cycles per state)
  [    2.410019] psci_checker: cpuidle not available on CPU 0, ignoring
  [    2.416452] psci_checker: cpuidle not available on CPU 1, ignoring
  [    2.422757] psci_checker: Could not start suspend tests on any CPU
  [    2.429370] psci_checker: PSCI checker completed

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:54:23 +02:00
Stefan Agner
a89eb89b38 imx: mx7: psci: provide complete PSCI 1.0 implementation
PSCI 1.0 require PSCI_VERSION, PSCI_FEATURES, AFFINITY_INFO and
CPU_SUSPEND to be implemented. Commit 0ec3d98f76 ("mx7_common:
use psci 1.0 instead of 0.1") marked the i.MX 7 implementation to
be PSCI 1.0 compliant but failed to implement those functions.
Especially the missing PSCI version callback was noticeable when
booting Linux:

  [    0.000000] psci: probing for conduit method from DT.
  [    0.000000] psci: PSCIv65535.65535 detected in firmware.
  [    0.000000] psci: Using standard PSCI v0.2 function IDs
  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.
  [    0.000000] psci: SMC Calling Convention v1.0

This patch provides a minimal implementation thereof. With this
patch applied Linux detects PSCI 1.0:

  [    0.000000] psci: probing for conduit method from DT.
  [    0.000000] psci: PSCIv1.0 detected in firmware.
  [    0.000000] psci: Using standard PSCI v0.2 function IDs
  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.
  [    0.000000] psci: SMC Calling Convention v1.0

Fixes: 0ec3d98f76 ("mx7_common: use psci 1.0 instead of 0.1")
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:54:01 +02:00
Stefan Agner
cff38c5504 imx: mx7: psci: use C code exclusively
There is no need for assembly in the platform specific part of
the PSCI implementation.

Note that this does not make it a complete PSCI 1.0 implementation
yet but aids to do so in upcoming patches.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:53:42 +02:00
Stefan Agner
77fcc2cc90 ARM: PSCI: initialize stack pointer on secondary CPUs
A proper stack is required to safely use C code in psci_arch_cpu_entry.

Fixes: 486daaa618 ("arm: psci: add a weak function psci_arch_cpu_entry")
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Patrick DELAUNAY <Patrick.delaunay@st.com>
Tested-by: Patrick DELAUNAY <Patrick.delaunay@st.com>
2018-07-23 10:53:12 +02:00
Michael Trimarchi
4a72abcb71 imx: imx6: Add comment to gpr_init function
This function can be used only for some of the nxp SoC. Make
it explicit in the comment. This adjust a bit commit
3aa4b703b4 ("imx: imx6: Move gpr_init() function to soc.c")

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-23 10:50:53 +02:00
Fabio Estevam
2756d31fae mx7: Remove BMODE support
i.MX7 does not support BMODE due to the erratum e10574 ("Watchdog:
A watchdog timeout or software trigger will not reset the SOC"), so
remove its support.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-07-23 10:50:00 +02:00
Michael Trimarchi
9236269de5 imx: mx6: Fix implementantion reset_misc
lcdif_power_down should not be included in spl build to avoid build
failure introduced by commit eb111bb31d

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-07-23 10:31:52 +02:00
Stefan Agner
31b1e17f44 board: toradex: add Colibri iMX6ULL support
Add support for the Colibri iMX6ULL module which comes with
on-board raw NAND.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:12:00 +02:00
Stefan Agner
55f34f3a9e ARM: dts: imx6ull: use same compatible string as Linux is using
The GPMI NAND IP seems to be the same as used in i.MX 6Quad. Use
the fsl,imx6q-gpmi-nand compatible string like Linux devices trees
are.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-07-23 10:12:00 +02:00
Stefan Agner
23eaf4180f imx: add macro to detect whether USB has been initialized
This macro allows to detect whether the boot ROM initialized USB
already (serial downloader). This is helpful to reliably detect
if the system has been recovered via USB serial downloader.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2018-07-23 10:12:00 +02:00
Tom Rini
83853366e3 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2018-07-20 22:35:49 -04:00
Carlo Caione
315ded9730 rockchip: veyron: Set vcc33_sd regulator value
On the veyron board the vcc33_sd regulator is used as vmmc-supply for
the SD card. This regulator is powered in the MMC core during power on
but its value is never actually set.

In the veyron platform the reset value for the LDO output is 1.8V while
the standard (min and max) value for this regulator defined in the DTS
is 3.3V. When the MMC core enable the regulator without setting its
value, the output is automatically set to 1.8V instead of 3.3V.

With this patch we preemptively set the value to 3.3V.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:27 +02:00
Carlo Caione
389167c3c4 rk3288: Disable JTAG function from sdmmc0 IO
The GRF_SOC_CON0.grf_force_jtag bit is automatically set at boot and it
is preventing the SDMMC to work correctly. Disable the JTAG function on
the assumption that a working SD has higher priority over JTAG.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:27 +02:00
Carlo Caione
0d4d5fd73c rk3288: veyron: Init boot-on regulators
Use regulators_enable_boot_on() to init all the regulators with
regulator-boot-on property.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:27 +02:00
Heinrich Schuchardt
9125947687 rockchip: rk3399: spl: add missing \n to output
Without the patch SPL (in case of an error) creates an output like:

	U-Boot SPL board initMissing DTB

The patch adds the missing line feed. So now we get:

	U-Boot SPL board init
	Missing DTB

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:26 +02:00
Philipp Tomsich
e5f2ecc750 rockchip: rk3399: inject 'u-boot, spl-boot-device' for next-stage
This implements the new 'spl_perform_fixups' hook for RK3399-based
boards and injects the /chosen/u-boot,spl-boot-device with an ofpath
corresponding to the boot device used.

The intended usage is for the full U-Boot stage to evaluate this in
scripts and then adapt its boot-order when using distro-boot.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2018-07-21 01:55:26 +02:00
Alexander Kochetkov
706afa46c7 rockchip: rk3188: add rk_board_late_init() hook
All other rockchip boards have rk_board_late_init() hook,
so add it to rk3188 boards also.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-07-21 01:55:25 +02:00
Tom Rini
e0ed8332fa Merge git://git.denx.de/u-boot-x86 2018-07-20 19:31:30 -04:00
Loic Devulder
77dd09211b ARM64: meson: Sync DT with Linux 4.17.5
Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.17.5
(Linux commit 54fb3c180d05e9dfda892a93413514e99f0cbb19).

This will enable HDMI_5V for USB Amlogic Meson GXL P212 based boards.

Signed-off-by: Loic Devulder <ldevulder@suse.de>
2018-07-20 15:55:09 -04:00
Patrick Delaunay
8a07d5bfe1 stm32mp1: clock tree update
Configure clock tree for all the devices.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20 15:55:06 -04:00
Patrick Delaunay
5f16f655cc stm32mp1: add support for stm32mp157c-ev1 board
Add support of stm32mp157c-ev1, the evaluation board with pmic stpmu1
(ev1 = mother board + daughter ed1) with device tree.
EV1 is the selected board by default in basic defconfig.

PS: CONFIG_PINCTRL_FULL activation avoid to increase
    SYS_MALLOC_F_LEN (Early malloc usage: 2034)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20 15:55:05 -04:00
Patrick Delaunay
bc06134e17 stm32mp1: activate MISC support in SPL
needed for RCC MISC driver and sysreset with syscon
in SPL

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20 15:55:05 -04:00
Patrick Delaunay
d090cbab64 misc: stm32: Add STM32MP1 support
Following next kernel rcc bindings, we must use a MFD
RCC driver which is able to bind both clock and reset
drivers.

We can reuse and adapt RCC MFD driver already available
for MCU SoCs (F4/F7/H7).

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20 15:55:05 -04:00
Patrick Delaunay
a674313c2c dts: import stm32mp1 device tree from linux kernel
This patch rebase the stm32mp1 device tree source from
linux kernel v4.18-rc1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-07-20 15:55:05 -04:00
Bin Meng
05855fd31a x86: acpi: Prevent acpi_table.h from being included more than once
The wrapper #ifndef is currently missing in acpi_table.h. Add it to
prevent it from being included multiple times.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-20 09:33:22 +08:00
Bin Meng
474a62bc74 x86: acpi: Don't touch ACPI hardware in write_acpi_tables()
write_acpi_tables() currently touches ACPI hardware to switch to
ACPI mode at the end. Move such operation out of this function,
so that it only does what the function name tells us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-20 09:33:22 +08:00
Bin Meng
a0609a8d19 x86: acpi: Move APIs unrelated to ACPI tables generation to a separate library
acpi_find_fadt(), acpi_find_wakeup_vector() and enter_acpi_mode()
are something unrelated to ACPI tables generation. Move these to
a separate library.

This also fixes several style issues reported by checkpatch in the
original codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-20 09:33:22 +08:00
Bin Meng
b37b7b2063 x86: Switch to use DM sysreset driver
This converts all x86 boards over to DM sysreset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-20 09:33:22 +08:00
Bin Meng
7bb6028768 x86: fsp: Eliminate the reset_cpu() call
In preparation for the reset driver conversion, eliminate the
reset_cpu() call in the FSP init path as it's too early for the
reset driver to work.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-20 09:33:22 +08:00