mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
arm: mvebu: Better align Clearfog dts file with Linux kernel
This makes changes so the u-boot dts file is structured more similar to the mainline linux dtsi file. It provides a minimal common dts that can work for most boards based on the ClearFog platform. Ethernet support is only supported for eth0 however all devices are left enabled so u-boot can generate and provide mac addresses for all of the network interfaces. Signed-off-by: Jon Nettleton <jon@solid-run.com> [baruch: rebase on recent changes] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Dennis Gilmore <dennis@ausil.us> Tested-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Jon Nettleton
Stefan Roese
parent
a4adb1f576
commit
334eebefc2
1 changed files with 151 additions and 235 deletions
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@ -81,174 +81,6 @@
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soc {
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internal-regs {
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ethernet@30000 {
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mac-address = [00 50 43 02 02 02];
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phy-mode = "sgmii";
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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ethernet@34000 {
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mac-address = [00 50 43 02 02 03];
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managed = "in-band-status";
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phy-mode = "sgmii";
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status = "okay";
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};
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i2c@11000 {
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/* Is there anything on this? */
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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/*
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* PCA9655 GPIO expander, up to 1MHz clock.
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* 0-CON3 CLKREQ#
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* 1-CON3 PERST#
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* 2-CON2 PERST#
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* 3-CON3 W_DISABLE
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* 4-CON2 CLKREQ#
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* 5-USB3 overcurrent
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* 6-USB3 power
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* 7-CON2 W_DISABLE
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* 8-JP4 P1
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* 9-JP4 P4
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* 10-JP4 P5
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* 11-m.2 DEVSLP
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* 12-SFP_LOS
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* 13-SFP_TX_FAULT
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* 14-SFP_TX_DISABLE
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* 15-SFP_MOD_DEF0
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*/
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expander0: gpio-expander@20 {
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/*
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* This is how it should be:
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* compatible = "onnn,pca9655",
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* "nxp,pca9555";
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* but you can't do this because of
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* the way I2C works.
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*/
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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pcie1_0_clkreq {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie1.0-clkreq";
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};
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pcie1_0_w_disable {
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gpio-hog;
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gpios = <3 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie1.0-w-disable";
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};
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pcie2_0_clkreq {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie2.0-clkreq";
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};
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pcie2_0_w_disable {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie2.0-w-disable";
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};
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usb3_ilimit {
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gpio-hog;
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gpios = <5 GPIO_ACTIVE_LOW>;
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input;
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line-name = "usb3-current-limit";
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};
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usb3_power {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb3-power";
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};
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m2_devslp {
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gpio-hog;
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gpios = <11 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "m.2 devslp";
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};
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};
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/* The MCP3021 is 100kHz clock only */
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mikrobus_adc: mcp3021@4c {
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compatible = "microchip,mcp3021";
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reg = <0x4c>;
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};
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/* Also something at 0x64 */
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};
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i2c@11100 {
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/*
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* Routed to SFP, mikrobus, and PCIe.
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* SFP limits this to 100kHz, and requires
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* an AT24C01A/02/04 with address pins tied
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* low, which takes addresses 0x50 and 0x51.
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* Mikrobus doesn't specify beyond an I2C
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* bus being present.
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* PCIe uses ARP to assign addresses, or
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* 0x63-0x64.
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*/
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clock-frequency = <100000>;
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pinctrl-0 = <&clearfog_i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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pinctrl@18000 {
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clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
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marvell,pins = "mpp46";
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marvell,function = "ref";
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};
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clearfog_dsa0_pins: clearfog-dsa0-pins {
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marvell,pins = "mpp23", "mpp41";
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marvell,function = "gpio";
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};
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clearfog_i2c1_pins: i2c1-pins {
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/* SFP, PCIe, mSATA, mikrobus */
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "i2c1";
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};
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clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
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marvell,pins = "mpp20";
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marvell,function = "gpio";
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};
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clearfog_spi1_cs_pins: spi1-cs-pins {
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marvell,pins = "mpp55";
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marvell,function = "spi1";
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};
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mikro_pins: mikro-pins {
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/* int: mpp22 rst: mpp29 */
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marvell,pins = "mpp22", "mpp29";
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marvell,function = "gpio";
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};
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mikro_spi_pins: mikro-spi-pins {
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marvell,pins = "mpp43";
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marvell,function = "spi1";
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};
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mikro_uart_pins: mikro-uart-pins {
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marvell,pins = "mpp24", "mpp25";
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marvell,function = "ua1";
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};
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rear_button_pins: rear-button-pins {
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marvell,pins = "mpp34";
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marvell,function = "gpio";
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};
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};
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rtc@a3800 {
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/*
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* If the rtc doesn't work, run "date reset"
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@ -297,7 +129,8 @@
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status = "okay";
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};
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usb3@f8000 {
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usb0: usb3@f8000 {
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/* CON7, USB-A port on back of device */
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status = "okay";
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};
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};
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@ -321,72 +154,6 @@
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};
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};
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sfp: sfp {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
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moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
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sfp,ethernet = <ð2>;
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tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
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};
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dsa@0 {
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compatible = "marvell,dsa";
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dsa,ethernet = <ð1>;
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dsa,mii-bus = <&mdio>;
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pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
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pinctrl-names = "default";
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#address-cells = <2>;
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#size-cells = <0>;
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switch@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4 0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@4 {
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reg = <4>;
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label = "lan5";
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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};
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port@6 {
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/* 88E1512 external phy */
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reg = <6>;
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label = "lan6";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&rear_button_pins>;
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@ -406,6 +173,155 @@
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status = "okay";
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};
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ð1 {
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managed = "in-band-status";
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phy-mode = "sgmii";
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status = "okay";
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};
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ð2 {
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phy-mode = "sgmii";
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status = "okay";
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};
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&i2c0 {
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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/*
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* PCA9655 GPIO expander, up to 1MHz clock.
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* 0-CON3 CLKREQ#
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* 1-CON3 PERST#
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* 2-CON2 PERST#
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* 3-CON3 W_DISABLE
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* 4-CON2 CLKREQ#
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* 5-USB3 overcurrent
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* 6-USB3 power
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* 7-CON2 W_DISABLE
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* 8-JP4 P1
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* 9-JP4 P4
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* 10-JP4 P5
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* 11-m.2 DEVSLP
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* 12-SFP_LOS
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* 13-SFP_TX_FAULT
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* 14-SFP_TX_DISABLE
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* 15-SFP_MOD_DEF0
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*/
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expander0: gpio-expander@20 {
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/*
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* This is how it should be:
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* compatible = "onnn,pca9655",
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* "nxp,pca9555";
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* but you can't do this because of
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* the way I2C works.
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*/
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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pcie1_0_clkreq {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie1.0-clkreq";
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};
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pcie1_0_w_disable {
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gpio-hog;
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gpios = <3 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie1.0-w-disable";
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};
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pcie2_0_clkreq {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie2.0-clkreq";
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};
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pcie2_0_w_disable {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie2.0-w-disable";
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};
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usb3_ilimit {
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gpio-hog;
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gpios = <5 GPIO_ACTIVE_LOW>;
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input;
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line-name = "usb3-current-limit";
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};
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usb3_power {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb3-power";
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};
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m2_devslp {
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gpio-hog;
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gpios = <11 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "m.2 devslp";
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};
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};
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mikrobus_adc: mcp3021@4c {
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compatible = "microchip,mcp3021";
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reg = <0x4c>;
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};
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};
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&i2c1 {
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/*
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* Routed to SFP, mikrobus, and PCIe.
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* SFP limits this to 100kHz, and requires
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* an AT24C01A/02/04 with address pins tied
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* low, which takes addresses 0x50 and 0x51.
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* Mikrobus doesn't specify beyond an I2C
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* bus being present.
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* PCIe uses ARP to assign addresses, or
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* 0x63-0x64.
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*/
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clock-frequency = <100000>;
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pinctrl-0 = <&clearfog_i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pinctrl {
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clearfog_i2c1_pins: i2c1-pins {
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/* SFP, PCIe, mSATA, mikrobus */
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marvell,pins = "mpp26", "mpp27";
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marvell,function = "i2c1";
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};
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clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
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marvell,pins = "mpp20";
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marvell,function = "gpio";
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};
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clearfog_spi1_cs_pins: spi1-cs-pins {
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marvell,pins = "mpp55";
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marvell,function = "spi1";
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};
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mikro_pins: mikro-pins {
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/* int: mpp22 rst: mpp29 */
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marvell,pins = "mpp22", "mpp29";
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marvell,function = "gpio";
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};
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mikro_spi_pins: mikro-spi-pins {
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marvell,pins = "mpp43";
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marvell,function = "spi1";
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};
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mikro_uart_pins: mikro-uart-pins {
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marvell,pins = "mpp24", "mpp25";
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marvell,function = "ua1";
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};
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rear_button_pins: rear-button-pins {
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marvell,pins = "mpp34";
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marvell,function = "gpio";
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};
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};
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/*
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+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
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MPP18: gpio ? (pca9655 int?)
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