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sunxi: add clock code for H6
The new Allwinner H6 SoC has a brand new CCU layout. Add clock code for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Icenowy Zheng
Jagan Teki
parent
6958c30319
commit
0558676d4b
4 changed files with 417 additions and 0 deletions
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@ -16,6 +16,8 @@
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/* clock control module regs definition */
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#if defined(CONFIG_MACH_SUN8I_A83T)
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#include <asm/arch/clock_sun8i_a83t.h>
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#elif defined(CONFIG_MACH_SUN50I_H6)
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#include <asm/arch/clock_sun50i_h6.h>
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#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
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defined(CONFIG_MACH_SUN50I)
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#include <asm/arch/clock_sun6i.h>
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320
arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
Normal file
320
arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
Normal file
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@ -0,0 +1,320 @@
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/*
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* Allwinner H6 clock register definitions
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*
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_CLOCK_SUN50I_H6_H
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#define _SUNXI_CLOCK_SUN50I_H6_H
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struct sunxi_ccm_reg {
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u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
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u8 reserved_0x004[12];
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u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
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u8 reserved_0x014[12];
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u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
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u8 reserved_0x020[4];
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u32 pll_periph1_cfg; /* 0x028 pll periph1 control */
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u8 reserved_0x028[4];
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u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
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u8 reserved_0x034[12];
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u32 pll3_cfg; /* 0x040 pll3 (video0) control */
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u8 reserved_0x044[4];
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u32 pll_video1_cfg; /* 0x048 pll video1 control */
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u8 reserved_0x04c[12];
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u32 pll4_cfg; /* 0x058 pll4 (ve) control */
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u8 reserved_0x05c[4];
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u32 pll10_cfg; /* 0x060 pll10 (de) control */
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u8 reserved_0x064[12];
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u32 pll9_cfg; /* 0x070 pll9 (hsic) control */
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u8 reserved_0x074[4];
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u32 pll2_cfg; /* 0x078 pll2 (audio) control */
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u8 reserved_0x07c[148];
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u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */
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u8 reserved_0x114[20];
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u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */
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u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */
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u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */
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u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */
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u8 reserved_0x138[8];
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u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */
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u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */
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u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */
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u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */
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u8 reserved_0x150[8];
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u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */
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u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */
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u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */
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u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */
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u8 reserved_0x168[8];
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u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */
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u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */
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u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */
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u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */
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u8 reserved_0x180[384];
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u32 pll1_bias; /* 0x300 pll1 (cpux) bias */
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u8 reserved_0x304[12];
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u32 pll5_bias; /* 0x310 pll5 (ddr) bias */
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u8 reserved_0x314[12];
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u32 pll6_bias; /* 0x320 pll6 (periph0) bias */
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u8 reserved_0x324[4];
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u32 pll_periph1_bias; /* 0x328 pll periph1 bias */
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u8 reserved_0x32c[4];
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u32 pll7_bias; /* 0x330 pll7 (gpu) bias */
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u8 reserved_0x334[12];
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u32 pll3_bias; /* 0x340 pll3 (video0) bias */
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u8 reserved_0x344[4];
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u32 pll_video1_bias; /* 0x348 pll video1 bias */
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u8 reserved_0x34c[12];
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u32 pll4_bias; /* 0x358 pll4 (ve) bias */
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u8 reserved_0x35c[4];
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u32 pll10_bias; /* 0x360 pll10 (de) bias */
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u8 reserved_0x364[12];
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u32 pll9_bias; /* 0x370 pll9 (hsic) bias */
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u8 reserved_0x374[4];
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u32 pll2_bias; /* 0x378 pll2 (audio) bias */
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u8 reserved_0x37c[132];
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u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */
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u8 reserved_0x404[252];
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u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/
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u8 reserved_0x504[12];
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u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */
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u8 reserved_0x514[8];
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u32 ahb3_cfg; /* 0x51c AHB3 clock control */
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u32 apb1_cfg; /* 0x520 APB1 clock control */
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u32 apb2_cfg; /* 0x524 APB2 clock control */
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u8 reserved_0x528[24];
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u32 mbus_cfg; /* 0x540 MBUS clock control */
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u8 reserved_0x544[188];
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u32 de_clk_cfg; /* 0x600 DE clock control */
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u8 reserved_0x604[8];
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u32 de_gate_reset; /* 0x60c DE gate/reset control */
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u8 reserved_0x610[16];
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u32 di_clk_cfg; /* 0x620 DI clock control */
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u8 reserved_0x024[8];
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u32 di_gate_reset; /* 0x62c DI gate/reset control */
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u8 reserved_0x630[64];
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u32 gpu_clk_cfg; /* 0x670 GPU clock control */
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u8 reserved_0x674[8];
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u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */
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u32 ce_clk_cfg; /* 0x680 CE clock control */
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u8 reserved_0x684[8];
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u32 ce_gate_reset; /* 0x68c CE gate/reset control */
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u32 ve_clk_cfg; /* 0x690 VE clock control */
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u8 reserved_0x694[8];
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u32 ve_gate_reset; /* 0x69c VE gate/reset control */
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u8 reserved_0x6a0[16];
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u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */
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u8 reserved_0x6b4[8];
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u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */
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u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */
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u8 reserved_0x6c4[8];
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u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */
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u8 reserved_0x6d0[60];
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u32 dma_gate_reset; /* 0x70c DMA gate/reset control */
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u8 reserved_0x710[12];
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u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */
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u8 reserved_0x720[12];
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u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */
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u8 reserved_0x730[12];
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u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */
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u32 avs_gate_reset; /* 0x740 AVS gate/reset control */
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u8 reserved_0x744[72];
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u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */
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u8 reserved_0x790[12];
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u32 psi_gate_reset; /* 0x79c PSI gate/reset control */
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u8 reserved_0x7a0[12];
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u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */
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u8 reserved_0x7b0[12];
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u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */
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u8 reserved_0x7c0[64];
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u32 dram_clk_cfg; /* 0x800 DRAM clock control */
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u32 mbus_gate; /* 0x804 MBUS gate control */
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u8 reserved_0x808[4];
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u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */
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u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */
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u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */
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u8 reserved_0x818[20];
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u32 nand_gate_reset; /* 0x82c NAND gate/reset control */
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u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */
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u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */
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u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */
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u8 reserved_0x83c[16];
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u32 sd_gate_reset; /* 0x84c MMC gate/reset control */
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u8 reserved_0x850[188];
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u32 uart_gate_reset; /* 0x90c UART gate/reset control */
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u8 reserved_0x910[12];
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u32 twi_gate_reset; /* 0x91c I2C gate/reset control */
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u8 reserved_0x920[28];
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u32 scr_gate_reset; /* 0x93c SCR gate/reset control */
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u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */
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u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */
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u8 reserved_0x948[36];
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u32 spi_gate_reset; /* 0x96c SPI gate/reset control */
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u8 reserved_0x970[12];
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u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */
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u8 reserved_0x980[48];
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u32 ts_clk_cfg; /* 0x9b0 TS clock control */
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u8 reserved_0x9b4[8];
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u32 ts_gate_reset; /* 0x9bc TS gate/reset control */
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u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */
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u8 reserved_0x9c4[8];
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u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */
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u8 reserved_0x9d0[44];
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u32 ths_gate_reset; /* 0x9fc THS gate/reset control */
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u8 reserved_0xa00[12];
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u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */
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u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */
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u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */
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u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */
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u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */
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u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */
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u8 reserved_0xa24[8];
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u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */
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u8 reserved_0xa30[16];
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u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */
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u8 reserved_0xa44[8];
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u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */
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u8 reserved_0xa50[16];
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u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */
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u8 reserved_0xa64[8];
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u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */
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u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */
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u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */
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u8 reserved_0xa78[4];
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u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */
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u8 reserved_0xa80[12];
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u32 usb_gate_reset; /* 0xa8c USB gate/reset control */
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u8 reserved_0xa90[32];
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u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */
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u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */
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u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */
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u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */
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u8 reserved_0xac0[64];
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u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */
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u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */
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u8 reserved_0xb08[8];
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u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */
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u8 reserved_0xb14[8];
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u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */
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u8 reserved_0xb20[60];
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u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */
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u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */
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u8 reserved_0xb64[24];
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u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */
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u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */
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u8 reserved_0xb84[24];
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u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */
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u8 reserved_0xba0[96];
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u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */
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u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */
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u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */
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u8 reserved_0xc0c[32];
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u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */
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u8 reserved_0xc30[16];
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u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */
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u8 reserved_0xc44[8];
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u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */
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u8 reserved_0xc50[688];
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u32 ccu_sec_switch; /* 0xf00 CCU security switch */
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u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */
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};
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/* pll1 bit field */
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#define CCM_PLL1_CTRL_EN BIT(31)
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#define CCM_PLL1_LOCK_EN BIT(29)
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#define CCM_PLL1_LOCK BIT(28)
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#define CCM_PLL1_CLOCK_TIME_2 (2 << 24)
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#define CCM_PLL1_CTRL_P(p) ((p) << 16)
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#define CCM_PLL1_CTRL_N(n) ((n) << 8)
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/* pll5 bit field */
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#define CCM_PLL5_CTRL_EN BIT(31)
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#define CCM_PLL5_LOCK_EN BIT(29)
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#define CCM_PLL5_LOCK BIT(28)
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#define CCM_PLL5_CTRL_N(n) ((n) << 8)
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#define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0)
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#define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1)
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/* pll6 bit field */
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#define CCM_PLL6_CTRL_EN BIT(31)
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#define CCM_PLL6_LOCK_EN BIT(29)
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#define CCM_PLL6_LOCK BIT(28)
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#define CCM_PLL6_CTRL_N_SHIFT 8
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#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT)
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#define CCM_PLL6_CTRL_DIV1_SHIFT 0
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#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT)
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#define CCM_PLL6_CTRL_DIV2_SHIFT 1
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#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT)
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#define CCM_PLL6_DEFAULT 0xa0006300
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/* cpu_axi bit field*/
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#define CCM_CPU_AXI_MUX_MASK (0x3 << 24)
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#define CCM_CPU_AXI_MUX_OSC24M (0x0 << 24)
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#define CCM_CPU_AXI_MUX_PLL_CPUX (0x3 << 24)
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#define CCM_CPU_AXI_APB_MASK 0x300
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#define CCM_CPU_AXI_AXI_MASK 0x3
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#define CCM_CPU_AXI_DEFAULT_FACTORS 0x301
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/* psi_ahb1_ahb2 bit field */
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#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102
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/* ahb3 bit field */
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#define CCM_AHB3_DEFAULT 0x03000002
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/* apb1 bit field */
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#define CCM_APB1_DEFAULT 0x03000102
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/* apb2 bit field */
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#define APB2_CLK_SRC_OSC24M (0x0 << 24)
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#define APB2_CLK_SRC_OSC32K (0x1 << 24)
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#define APB2_CLK_SRC_PSI (0x2 << 24)
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#define APB2_CLK_SRC_PLL6 (0x3 << 24)
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#define APB2_CLK_SRC_MASK (0x3 << 24)
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#define APB2_CLK_RATE_N_1 (0x0 << 8)
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#define APB2_CLK_RATE_N_2 (0x1 << 8)
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#define APB2_CLK_RATE_N_4 (0x2 << 8)
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#define APB2_CLK_RATE_N_8 (0x3 << 8)
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#define APB2_CLK_RATE_N_MASK (3 << 8)
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#define APB2_CLK_RATE_M(m) (((m)-1) << 0)
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#define APB2_CLK_RATE_M_MASK (3 << 0)
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/* MBUS clock bit field */
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#define MBUS_ENABLE BIT(31)
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#define MBUS_RESET BIT(30)
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#define MBUS_CLK_SRC_MASK GENMASK(25, 24)
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#define MBUS_CLK_SRC_OSCM24 (0 << 24)
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#define MBUS_CLK_SRC_PLL6X2 (1 << 24)
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#define MBUS_CLK_SRC_PLL5 (2 << 24)
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#define MBUS_CLK_SRC_PLL6X4 (3 << 24)
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#define MBUS_CLK_M(m) (((m)-1) << 0)
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/* Module gate/reset shift*/
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#define RESET_SHIFT (16)
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/* DRAM clock bit field */
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#define DRAM_MOD_RESET BIT(30)
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#define DRAM_CLK_UPDATE BIT(27)
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#define DRAM_CLK_SRC_MASK GENMASK(25, 24)
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#define DRAM_CLK_SRC_PLL5 (0 << 24)
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#define DRAM_CLK_M(m) (((m)-1) << 0)
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/* MMC clock bit field */
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#define CCM_MMC_CTRL_M(x) ((x) - 1)
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#define CCM_MMC_CTRL_N(x) ((x) << 8)
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#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
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#define CCM_MMC_CTRL_PLL6X2 (0x1 << 24)
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#define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24)
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#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
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/* H6 doesn't have these delays */
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#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0)
|
||||
#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void clock_set_pll1(unsigned int hz);
|
||||
unsigned int clock_get_pll6(void);
|
||||
#endif
|
||||
|
||||
#endif /* _SUNXI_CLOCK_SUN50I_H6_H */
|
||||
|
|
@ -26,6 +26,7 @@ else
|
|||
obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
|
||||
endif
|
||||
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
|
||||
obj-$(CONFIG_MACH_SUN50I_H6) += clock_sun50i_h6.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
|
||||
|
|
|
|||
94
arch/arm/mach-sunxi/clock_sun50i_h6.c
Normal file
94
arch/arm/mach-sunxi/clock_sun50i_h6.c
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void clock_init_safe(void)
|
||||
{
|
||||
struct sunxi_ccm_reg *const ccm =
|
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
clock_set_pll1(408000000);
|
||||
|
||||
writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
|
||||
while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK))
|
||||
;
|
||||
|
||||
clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK,
|
||||
CCM_CPU_AXI_DEFAULT_FACTORS);
|
||||
|
||||
writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
|
||||
writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
|
||||
writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
|
||||
|
||||
/*
|
||||
* The mux and factor are set, but the clock will be enabled in
|
||||
* DRAM initialization code.
|
||||
*/
|
||||
writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
|
||||
}
|
||||
#endif
|
||||
|
||||
void clock_init_uart(void)
|
||||
{
|
||||
struct sunxi_ccm_reg *const ccm =
|
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
|
||||
/* uart clock source is apb2 */
|
||||
writel(APB2_CLK_SRC_OSC24M|
|
||||
APB2_CLK_RATE_N_1|
|
||||
APB2_CLK_RATE_M(1),
|
||||
&ccm->apb2_cfg);
|
||||
|
||||
/* open the clock for uart */
|
||||
setbits_le32(&ccm->uart_gate_reset,
|
||||
1 << (CONFIG_CONS_INDEX - 1));
|
||||
|
||||
/* deassert uart reset */
|
||||
setbits_le32(&ccm->uart_gate_reset,
|
||||
1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void clock_set_pll1(unsigned int clk)
|
||||
{
|
||||
struct sunxi_ccm_reg * const ccm =
|
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
u32 val;
|
||||
|
||||
/* Do not support clocks < 288MHz as they need factor P */
|
||||
if (clk < 288000000) clk = 288000000;
|
||||
|
||||
/* Switch to 24MHz clock while changing PLL1 */
|
||||
val = readl(&ccm->cpu_axi_cfg);
|
||||
val &= ~CCM_CPU_AXI_MUX_MASK;
|
||||
val |= CCM_CPU_AXI_MUX_OSC24M;
|
||||
writel(val, &ccm->cpu_axi_cfg);
|
||||
|
||||
/* clk = 24*n/p, p is ignored if clock is >288MHz */
|
||||
writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
|
||||
CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
|
||||
while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
|
||||
|
||||
/* Switch CPU to PLL1 */
|
||||
val = readl(&ccm->cpu_axi_cfg);
|
||||
val &= ~CCM_CPU_AXI_MUX_MASK;
|
||||
val |= CCM_CPU_AXI_MUX_PLL_CPUX;
|
||||
writel(val, &ccm->cpu_axi_cfg);
|
||||
}
|
||||
#endif
|
||||
|
||||
unsigned int clock_get_pll6(void)
|
||||
{
|
||||
struct sunxi_ccm_reg *const ccm =
|
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
|
||||
uint32_t rval = readl(&ccm->pll6_cfg);
|
||||
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
|
||||
int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
|
||||
CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
|
||||
int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
|
||||
CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
|
||||
/* The register defines PLL6-4X, not plain PLL6 */
|
||||
return 24000000 / 4 * n / div1 / div2;
|
||||
}
|
||||
Loading…
Reference in a new issue