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https://github.com/AsahiLinux/u-boot
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ARM: meson: Add regmap support for clock driver
This patch modifies the meson clock driver to use syscon/regmap like the Linux kernel does, as it is needed if we want to share the same DTS files. DTS files are synchronized from Linux 4.19. Signed-off-by: Loic Devulder <ldevulder@suse.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Loic Devulder
Neil Armstrong
parent
952061352a
commit
8973d81658
9 changed files with 151 additions and 66 deletions
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@ -35,10 +35,16 @@
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no-map;
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};
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/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved_alt: secmon@5000000 {
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reg = <0x0 0x05000000 0x0 0x300000>;
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no-map;
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};
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0xbc00000>;
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size = <0x0 0x10000000>;
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alignment = <0x0 0x400000>;
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linux,cma-default;
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};
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@ -338,7 +344,7 @@
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ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
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sysctrl_AO: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
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compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
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reg = <0x0 0x0 0x0 0x100>;
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pwrc_vpu: power-controller-vpu {
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@ -417,6 +423,19 @@
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};
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};
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dmcbus: bus@c8838000 {
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compatible = "simple-bus";
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reg = <0x0 0xc8838000 0x0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
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canvas: video-lut@48 {
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compatible = "amlogic,canvas";
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reg = <0x0 0x48 0x0 0x14>;
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};
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};
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hiubus: bus@c883c000 {
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compatible = "simple-bus";
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reg = <0x0 0xc883c000 0x0 0x2000>;
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@ -425,7 +444,7 @@
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ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
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sysctrl: system-controller@0 {
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compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
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compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
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reg = <0 0 0 0x400>;
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};
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@ -457,21 +476,21 @@
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sd_emmc_a: mmc@70000 {
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compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
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reg = <0x0 0x70000 0x0 0x2000>;
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reg = <0x0 0x70000 0x0 0x800>;
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interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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sd_emmc_b: mmc@72000 {
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compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
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reg = <0x0 0x72000 0x0 0x2000>;
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reg = <0x0 0x72000 0x0 0x800>;
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interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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sd_emmc_c: mmc@74000 {
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compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
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reg = <0x0 0x74000 0x0 0x2000>;
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reg = <0x0 0x74000 0x0 0x800>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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@ -106,6 +106,42 @@
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
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};
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/* CVBS is available on CON1 pin 36, disabled by default */
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cvbs-connector {
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compatible = "composite-video-connector";
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status = "disabled";
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port {
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cvbs_connector_in: endpoint {
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remote-endpoint = <&cvbs_vdac_out>;
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};
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};
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};
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hdmi-connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi_tx_tmds_out>;
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};
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};
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};
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};
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&cec_AO {
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status = "okay";
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pinctrl-0 = <&ao_cec_pins>;
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pinctrl-names = "default";
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hdmi-phandle = <&hdmi_tx>;
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};
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&cvbs_vdac_port {
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cvbs_vdac_out: endpoint {
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remote-endpoint = <&cvbs_connector_in>;
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};
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};
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ðmac {
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@ -137,6 +173,18 @@
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};
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};
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&hdmi_tx {
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status = "okay";
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pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
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pinctrl-names = "default";
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};
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&hdmi_tx_tmds_port {
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hdmi_tx_tmds_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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&ir {
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status = "okay";
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pinctrl-0 = <&remote_input_ao_pins>;
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@ -307,11 +307,10 @@
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clock-names = "isfr", "iahb", "venci";
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};
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&hiubus {
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clkc: clock-controller@0 {
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&sysctrl {
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clkc: clock-controller {
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compatible = "amlogic,gxbb-clkc";
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#clock-cells = <1>;
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reg = <0x0 0x0 0x0 0x3db>;
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};
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};
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@ -391,7 +390,7 @@
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};
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};
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spi_pins: spi {
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spi_pins: spi-pins {
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mux {
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groups = "spi_miso",
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"spi_mosi",
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@ -716,6 +715,7 @@
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<&clkc CLKID_SD_EMMC_A_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_A>;
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};
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&sd_emmc_b {
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@ -723,6 +723,7 @@
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<&clkc CLKID_SD_EMMC_B_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_B>;
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};
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&sd_emmc_c {
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@ -730,6 +731,7 @@
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<&clkc CLKID_SD_EMMC_C_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_C>;
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};
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&spicc {
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@ -749,12 +751,12 @@
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};
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&uart_AO {
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clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
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clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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};
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&uart_AO_B {
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clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
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clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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};
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@ -6,7 +6,7 @@
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&apb {
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mali: gpu@c0000 {
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compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
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compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
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reg = <0x0 0xc0000 0x0 0x40000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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@ -13,7 +13,7 @@
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/ {
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compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
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model = "Libre Technology CC";
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model = "Libre Computer Board AML-S905X-CC";
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aliases {
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serial0 = &uart_AO;
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@ -234,9 +234,6 @@
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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max-frequency = <100000000>;
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disable-wp;
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@ -191,8 +191,8 @@
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};
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&usb2_phy0 {
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/*
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* HDMI_5V is also used as supply for the USB VBUS.
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*/
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phy-supply = <&hdmi_5v>;
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/*
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* HDMI_5V is also used as supply for the USB VBUS.
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*/
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phy-supply = <&hdmi_5v>;
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};
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@ -13,14 +13,6 @@
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/ {
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compatible = "amlogic,meson-gxl";
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reserved-memory {
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/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved_alt: secmon@5000000 {
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reg = <0x0 0x05000000 0x0 0x300000>;
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no-map;
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};
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};
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soc {
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usb0: usb@c9000000 {
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status = "disabled";
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@ -267,11 +259,10 @@
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clock-names = "isfr", "iahb", "venci";
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};
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&hiubus {
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clkc: clock-controller@0 {
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compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
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&sysctrl {
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clkc: clock-controller {
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compatible = "amlogic,gxl-clkc";
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#clock-cells = <1>;
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reg = <0x0 0x0 0x0 0x3db>;
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};
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};
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@ -346,7 +337,7 @@
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};
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};
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spi_pins: spi {
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spi_pins: spi-pins {
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mux {
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groups = "spi_miso",
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"spi_mosi",
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@ -725,13 +716,15 @@
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<&clkc CLKID_SD_EMMC_A_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_A>;
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};
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&sd_emmc_b {
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clocks = <&clkc CLKID_SD_EMMC_B>,
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<&clkc CLKID_SD_EMMC_B_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_B>;
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};
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&sd_emmc_c {
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@ -739,6 +732,7 @@
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<&clkc CLKID_SD_EMMC_C_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_C>;
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};
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&spicc {
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@ -758,12 +752,12 @@
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};
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&uart_AO {
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clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
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clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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};
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&uart_AO_B {
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clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
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clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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};
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@ -209,10 +209,34 @@
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#cooling-cells = <2>;
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};
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&cpu1 {
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#cooling-cells = <2>;
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};
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&cpu2 {
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#cooling-cells = <2>;
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};
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&cpu3 {
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#cooling-cells = <2>;
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};
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&cpu4 {
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#cooling-cells = <2>;
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};
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&cpu5 {
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#cooling-cells = <2>;
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};
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&cpu6 {
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#cooling-cells = <2>;
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};
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&cpu7 {
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#cooling-cells = <2>;
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};
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ðmac {
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pinctrl-0 = <ð_pins>;
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pinctrl-names = "default";
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@ -11,6 +11,8 @@
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#include <clk-uclass.h>
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#include <div64.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <dt-bindings/clock/gxbb-clkc.h>
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#include "clk_meson.h"
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@ -65,7 +67,7 @@
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#define XTAL_RATE 24000000
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struct meson_clk {
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void __iomem *addr;
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struct regmap *map;
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};
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static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
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@ -217,8 +219,8 @@ static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
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debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
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clrsetbits_le32(priv->addr + gate->reg,
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BIT(gate->bit), on ? BIT(gate->bit) : 0);
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regmap_update_bits(priv->map, gate->reg,
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BIT(gate->bit), on ? BIT(gate->bit) : 0);
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/* Propagate to next gate(s) */
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switch (id) {
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@ -269,7 +271,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
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unsigned int rate, parent_rate;
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struct parm *parm;
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int parent;
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u32 reg;
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uint reg;
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switch (id) {
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case CLKID_VPU_0_DIV:
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@ -292,7 +294,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
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return -ENOENT;
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}
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reg = readl(priv->addr + parm->reg_off);
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regmap_read(priv->map, parm->reg_off, ®);
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reg = PARM_GET(parm->width, parm->shift, reg);
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debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
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@ -318,7 +320,6 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
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unsigned long parent_rate;
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struct parm *parm;
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int parent;
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u32 reg;
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int ret;
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if (current_rate == rate)
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@ -383,9 +384,8 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
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debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
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reg = readl(priv->addr + parm->reg_off);
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writel(PARM_SET(parm->width, parm->shift, reg, new_div - 1),
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priv->addr + parm->reg_off);
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regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
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(new_div - 1) << parm->shift);
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debug("%s: new rate of %ld is %ld\n",
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__func__, id, meson_div_get_rate(clk, id));
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@ -446,7 +446,7 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
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struct meson_clk *priv = dev_get_priv(clk->dev);
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struct parm *parm;
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int *parents;
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u32 reg;
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uint reg;
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switch (id) {
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case CLKID_VPU:
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@ -477,7 +477,7 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
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return -ENOENT;
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}
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reg = readl(priv->addr + parm->reg_off);
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regmap_read(priv->map, parm->reg_off, ®);
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reg = PARM_GET(parm->width, parm->shift, reg);
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debug("%s: parent of %ld is %d (%d)\n",
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||||
|
|
@ -494,7 +494,6 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
|
|||
unsigned int new_index = -EINVAL;
|
||||
struct parm *parm;
|
||||
int *parents;
|
||||
u32 reg;
|
||||
int i;
|
||||
|
||||
if (IS_ERR_VALUE(cur_parent))
|
||||
|
|
@ -546,9 +545,8 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
|
|||
|
||||
debug("%s: new index of %ld is %d\n", __func__, id, new_index);
|
||||
|
||||
reg = readl(priv->addr + parm->reg_off);
|
||||
writel(PARM_SET(parm->width, parm->shift, reg, new_index),
|
||||
priv->addr + parm->reg_off);
|
||||
regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
|
||||
new_index << parm->shift);
|
||||
|
||||
debug("%s: new parent of %ld is %ld\n",
|
||||
__func__, id, meson_mux_get_parent(clk, id));
|
||||
|
|
@ -570,7 +568,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
|
|||
{
|
||||
struct meson_clk *priv = dev_get_priv(clk->dev);
|
||||
unsigned long parent_rate;
|
||||
u32 reg;
|
||||
uint reg;
|
||||
int parents[] = {
|
||||
-1,
|
||||
-1,
|
||||
|
|
@ -583,7 +581,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
|
|||
};
|
||||
|
||||
/* mux */
|
||||
reg = readl(priv->addr + HHI_MPEG_CLK_CNTL);
|
||||
regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
|
||||
reg = (reg >> 12) & 7;
|
||||
|
||||
switch (reg) {
|
||||
|
|
@ -597,7 +595,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
|
|||
}
|
||||
|
||||
/* divider */
|
||||
reg = readl(priv->addr + HHI_MPEG_CLK_CNTL);
|
||||
regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
|
||||
reg = reg & ((1 << 7) - 1);
|
||||
|
||||
/* clk81 divider is zero based */
|
||||
|
|
@ -641,8 +639,9 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
|
|||
{
|
||||
struct meson_clk *priv = dev_get_priv(clk->dev);
|
||||
struct parm *psdm, *pn2;
|
||||
unsigned long reg, sdm, n2;
|
||||
unsigned long sdm, n2;
|
||||
unsigned long parent_rate;
|
||||
uint reg;
|
||||
|
||||
switch (id) {
|
||||
case CLKID_MPLL0:
|
||||
|
|
@ -665,10 +664,10 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
|
|||
if (IS_ERR_VALUE(parent_rate))
|
||||
return parent_rate;
|
||||
|
||||
reg = readl(priv->addr + psdm->reg_off);
|
||||
regmap_read(priv->map, psdm->reg_off, ®);
|
||||
sdm = PARM_GET(psdm->width, psdm->shift, reg);
|
||||
|
||||
reg = readl(priv->addr + pn2->reg_off);
|
||||
regmap_read(priv->map, pn2->reg_off, ®);
|
||||
n2 = PARM_GET(pn2->width, pn2->shift, reg);
|
||||
|
||||
return mpll_rate_from_params(parent_rate, sdm, n2);
|
||||
|
|
@ -692,7 +691,7 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
|
|||
struct parm *pm, *pn, *pod;
|
||||
unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
|
||||
u16 n, m, od;
|
||||
u32 reg;
|
||||
uint reg;
|
||||
|
||||
switch (id) {
|
||||
case CLKID_FIXED_PLL:
|
||||
|
|
@ -709,13 +708,13 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
|
|||
return -ENOENT;
|
||||
}
|
||||
|
||||
reg = readl(priv->addr + pn->reg_off);
|
||||
regmap_read(priv->map, pn->reg_off, ®);
|
||||
n = PARM_GET(pn->width, pn->shift, reg);
|
||||
|
||||
reg = readl(priv->addr + pm->reg_off);
|
||||
regmap_read(priv->map, pm->reg_off, ®);
|
||||
m = PARM_GET(pm->width, pm->shift, reg);
|
||||
|
||||
reg = readl(priv->addr + pod->reg_off);
|
||||
regmap_read(priv->map, pod->reg_off, ®);
|
||||
od = PARM_GET(pod->width, pod->shift, reg);
|
||||
|
||||
return ((parent_rate_mhz * m / n) >> od) * 1000000;
|
||||
|
|
@ -876,8 +875,8 @@ static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
|
|||
if (IS_ERR_VALUE(ret))
|
||||
return ret;
|
||||
|
||||
printf("clock %lu has new rate %lu\n", clk->id,
|
||||
meson_clk_get_rate_by_id(clk, clk->id));
|
||||
debug("clock %lu has new rate %lu\n", clk->id,
|
||||
meson_clk_get_rate_by_id(clk, clk->id));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -886,9 +885,11 @@ static int meson_clk_probe(struct udevice *dev)
|
|||
{
|
||||
struct meson_clk *priv = dev_get_priv(dev);
|
||||
|
||||
priv->addr = dev_read_addr_ptr(dev);
|
||||
priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
|
||||
if (IS_ERR(priv->map))
|
||||
return PTR_ERR(priv->map);
|
||||
|
||||
debug("meson-clk: probed at addr %p\n", priv->addr);
|
||||
debug("meson-clk: probed\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue