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ARM: dts: socfpga: Flag timer clock as pre-reloc

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Flag timer clock as DM pre-reloc, so that a timer driver can be used and
it can extract information about it's clock rate using the clock framework.
This patch also moves some of the pre-reloc flags into the core dtsi file,
this is because the timer is not board specific, but rather is used on all
boards.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Marek Vasut 2018-08-18 19:13:28 +02:00
parent 66011a0883
commit cca9af63a3
2 changed files with 10 additions and 12 deletions
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10
arch/arm/dts/socfpga_arria10.dtsi
View file

@ -21,6 +21,11 @@
#address-cells = <1>;
#size-cells = <1>;
chosen {
tick-timer = &timer2;
u-boot,dm-pre-reloc;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -147,6 +152,7 @@
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
div-reg = <0x144 0 11>;
u-boot,dm-pre-reloc;
};
main_emaca_clk: main_emaca_clk@68 {
@ -236,6 +242,7 @@
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
div-reg = <0x144 16 11>;
u-boot,dm-pre-reloc;
};
peri_emaca_clk: peri_emaca_clk@e8 {
@ -311,6 +318,7 @@
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
reg = <0x64>;
u-boot,dm-pre-reloc;
};
s2f_user1_free_clk: s2f_user1_free_clk@104 {
@ -337,6 +345,7 @@
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&noc_free_clk>;
fixed-divider = <4>;
u-boot,dm-pre-reloc;
};
l4_main_clk: l4_main_clk {
@ -800,6 +809,7 @@
reg = <0xffd00000 0x100>;
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
u-boot,dm-pre-reloc;
};
timer3: timer3@ffd00100 {

12
arch/arm/dts/socfpga_arria10_socdk.dtsi
View file

@ -169,22 +169,10 @@
};
/* Clock available early */
&main_noc_base_clk {
u-boot,dm-pre-reloc;
};
&main_periph_ref_clk {
u-boot,dm-pre-reloc;
};
&peri_noc_base_clk {
u-boot,dm-pre-reloc;
};
&noc_free_clk {
u-boot,dm-pre-reloc;
};
&l4_mp_clk {
u-boot,dm-pre-reloc;
};