mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
arc: Add support for IoT development kit
The DesignWare ARC IoT Development Kit is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. More information is avaialble here [1] and here [2]. The board is based on real silicon with ARC EM9D-based Data Fusion IP Subsystem. It sports a rich set of I/O including * DW USB OTG * DW MobileStorage (used for micro SD-card) * GPIO * multiple serial interface including DW APB UART * ADC, PWM and eFlash, SRAM and SPI Flash memory * Real-Time Clock (RTC) * Bluetooth module with worldwide regulatory compliance (FCC, IC, CE, ETSI, TELEC) * On-board 9-axis sensor (gyro, accelerometer and compass) Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18 extension header. One of the most interesting features for developers is built-in Digilent USB JTAG probe so only micro-USB cable is needed! [1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit [2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdf Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin
parent
f31414a0ed
commit
5396e8b1dd
11 changed files with 444 additions and 0 deletions
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@ -157,6 +157,10 @@ config TARGET_EMDK
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config TARGET_HSDK
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bool "Support Synpsys HS DevelopmentKit board"
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config TARGET_IOT_DEVKIT
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bool "Synopsys Brite IoT Development kit"
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select CPU_ARCEM6
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endchoice
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source "board/abilis/tb100/Kconfig"
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@ -164,5 +168,6 @@ source "board/synopsys/Kconfig"
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source "board/synopsys/axs10x/Kconfig"
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source "board/synopsys/emdk/Kconfig"
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source "board/synopsys/hsdk/Kconfig"
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source "board/synopsys/iot_devkit/Kconfig"
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endmenu
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@ -6,6 +6,7 @@ dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
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dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
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dtb-$(CONFIG_TARGET_EMDK) += emdk.dtb
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dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb
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dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
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targets += $(dtb-y)
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45
arch/arc/dts/iot_devkit.dts
Normal file
45
arch/arc/dts/iot_devkit.dts
Normal file
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@ -0,0 +1,45 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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console = &uart0;
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};
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cpu_card {
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <144000000>;
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u-boot,dm-pre-reloc;
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};
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};
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uart0: serial0@80014000 {
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compatible = "snps,dw-apb-uart";
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clock-frequency = <16000000>;
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reg = <0x80014000 0x1000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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usb: usb@f0040000 {
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compatible = "snps,dwc2";
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reg = <0xf0040000 0x10000>;
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phys = <&usbphy>;
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phy-names = "usb2-phy";
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};
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usbphy: phy {
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compatible = "nop-phy";
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#phy-cells = <0>;
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};
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};
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12
board/synopsys/iot_devkit/Kconfig
Normal file
12
board/synopsys/iot_devkit/Kconfig
Normal file
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@ -0,0 +1,12 @@
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if TARGET_IOT_DEVKIT
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config SYS_BOARD
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default "iot_devkit"
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config SYS_VENDOR
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default "synopsys"
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config SYS_CONFIG_NAME
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default "iot_devkit"
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endif
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5
board/synopsys/iot_devkit/MAINTAINERS
Normal file
5
board/synopsys/iot_devkit/MAINTAINERS
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@ -0,0 +1,5 @@
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IOT DEVKIT BOARD
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M: Alexey Brodkin <abrodkin@synopsys.com>
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S: Maintained
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F: board/synopsys/iot_devkit/
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F: configs/iot_devkit_defconfig
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7
board/synopsys/iot_devkit/Makefile
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7
board/synopsys/iot_devkit/Makefile
Normal file
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@ -0,0 +1,7 @@
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#
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# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += iot_devkit.o
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2
board/synopsys/iot_devkit/config.mk
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2
board/synopsys/iot_devkit/config.mk
Normal file
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@ -0,0 +1,2 @@
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PLATFORM_CPPFLAGS += -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter
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LDSCRIPT = $(srctree)/board/synopsys/iot_devkit/u-boot.lds
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168
board/synopsys/iot_devkit/iot_devkit.c
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168
board/synopsys/iot_devkit/iot_devkit.c
Normal file
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@ -0,0 +1,168 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
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*/
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#include <common.h>
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#include <malloc.h>
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#include <dwmmc.h>
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#include <linux/libfdt.h>
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#include <fdtdec.h>
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#include <asm/arcregs.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SYSCON_BASE 0xf000a000
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#define AHBCKDIV (void *)(SYSCON_BASE + 0x04)
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#define APBCKDIV (void *)(SYSCON_BASE + 0x08)
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#define APBCKEN (void *)(SYSCON_BASE + 0x0C)
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#define CLKSEL (void *)(SYSCON_BASE + 0x24)
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#define CLKSTAT (void *)(SYSCON_BASE + 0x28)
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#define PLLCON (void *)(SYSCON_BASE + 0x2C)
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#define APBCKSEL (void *)(SYSCON_BASE + 0x30)
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#define AHBCKEN (void *)(SYSCON_BASE + 0x34)
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#define USBPHY_PLL (void *)(SYSCON_BASE + 0x78)
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#define USBCFG (void *)(SYSCON_BASE + 0x7c)
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#define PLL_MASK_0 0xffcfffff
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#define PLL_MASK_1 0xffcfff00
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#define PLL_MASK_2 0xfbcfff00
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#define CLKSEL_DEFAULT 0x5a690000
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static int set_cpu_freq(unsigned int clk)
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{
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clk /= 1000000;
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/* Set clk to ext Xtal (LSN value 0) */
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writel(CLKSEL_DEFAULT, CLKSEL);
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switch (clk) {
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case 16:
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/* Bypass mode */
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return 0;
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case 50:
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writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
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/* pll_off=1, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
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writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON);
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/* pll_off=0, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
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writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON);
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break;
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case 72:
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writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
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/* pll_off=1, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
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writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON);
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/* pll_off=0, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
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writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON);
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break;
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case 100:
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writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
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/* pll_off=1,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
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writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON);
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/* pll_off=0,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
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writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON);
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break;
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case 144:
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writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
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/* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
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writel((readl(PLLCON) & PLL_MASK_1) | 0x100121, PLLCON);
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/* pll_off=0, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
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writel((readl(PLLCON) & PLL_MASK_2) | 0x100121, PLLCON);
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break;
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default:
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return -EINVAL;
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}
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while (!(readl(CLKSTAT) & 0x4))
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;
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/* Set clk from PLL on bus (LSN = 1) */
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writel(CLKSEL_DEFAULT | BIT(0), CLKSEL);
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return 0;
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}
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extern u8 __rom_end[];
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extern u8 __ram_start[];
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extern u8 __ram_end[];
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/*
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* Use mach_cpu_init() for .data section copy as board_early_init_f() will be
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* too late: initf_dm() will use a value of "av_" variable from not yet
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* initialized (by copy) area.
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*/
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int mach_cpu_init(void)
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{
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int offset, freq;
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/* Don't relocate U-Boot */
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gd->flags |= GD_FLG_SKIP_RELOC;
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/* Copy data from ROM to RAM */
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u8 *src = __rom_end;
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u8 *dst = __ram_start;
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while (dst < __ram_end)
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*dst++ = *src++;
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/* Enable debug uart */
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#define DEBUG_UART_BASE 0x80014000
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#define DEBUG_UART_DLF_OFFSET 0xc0
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write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1);
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offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk");
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if (offset < 0)
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return offset;
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freq = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0);
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if (!freq)
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return -EINVAL;
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/* If CPU freq > 100 MHz, divide eFLASH clock by 2 */
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if (freq > 100000000) {
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u32 reg = readl(AHBCKDIV);
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reg &= ~(0xF << 8);
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reg |= 2 << 8;
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writel(reg, AHBCKDIV);
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}
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return set_cpu_freq(freq);
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}
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#define ARC_PERIPHERAL_BASE 0xF0000000
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#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xB000)
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int board_mmc_init(bd_t *bis)
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{
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struct dwmci_host *host = NULL;
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host = malloc(sizeof(struct dwmci_host));
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if (!host) {
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printf("dwmci_host malloc fail!\n");
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return -ENOMEM;
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}
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memset(host, 0, sizeof(struct dwmci_host));
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host->name = "Synopsys Mobile storage";
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host->ioaddr = (void *)SDIO_BASE;
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host->buswidth = 4;
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host->dev_index = 0;
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host->bus_hz = 50000000;
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add_dwmci(host, host->bus_hz / 2, 400000);
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Synopsys IoT Development Kit\n");
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return 0;
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};
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77
board/synopsys/iot_devkit/u-boot.lds
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77
board/synopsys/iot_devkit/u-boot.lds
Normal file
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@ -0,0 +1,77 @@
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/*
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* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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MEMORY {
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ROM : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
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RAM : ORIGIN = RAM_DATA_BASE, LENGTH = RAM_DATA_SIZE
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}
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OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
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OUTPUT_ARCH(arc)
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ENTRY(_start)
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SECTIONS
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{
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. = CONFIG_SYS_MONITOR_BASE;
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__image_copy_start = .;
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.ivt :
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{
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__ivt_start = .;
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KEEP(*(.ivt));
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__ivt_end = .;
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} > ROM
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. = ALIGN(1024);
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.text : {
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__text_start = .;
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arch/arc/lib/start.o (.text*)
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*(.text*)
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__text_end = .;
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} > ROM
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. = ALIGN(4);
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.rodata : {
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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} > ROM
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. = ALIGN(4);
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.u_boot_list : {
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KEEP(*(SORT(.u_boot_list*)));
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/* Mark RAM's LMA */
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. = ALIGN(4);
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__rom_end = .;
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} > ROM
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.data : {
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/* Mark RAM's VMA */
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. = ALIGN(4);
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/*
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* Everything between __ram_start and __ram_start will be
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* copied from ROM to RAM in board_early_init_f().
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*/
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__ram_start = .;
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*(.data*)
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__ram_end = .;
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} > RAM AT > ROM
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.bss : {
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. = ALIGN(1024);
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__bss_start = .;
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*(.bss*)
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__bss_end = .;
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} > RAM
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/* Keep relocation-related symbols to make linker happy */
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__rel_dyn_start = .;
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__rel_dyn_end = .;
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__image_copy_end = .;
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__init_end = .;
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}
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38
configs/iot_devkit_defconfig
Normal file
38
configs/iot_devkit_defconfig
Normal file
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@ -0,0 +1,38 @@
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CONFIG_ARC=y
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CONFIG_ISA_ARCV2=y
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CONFIG_CPU_ARCEM6=y
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CONFIG_SYS_ICACHE_OFF=y
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CONFIG_SYS_DCACHE_OFF=y
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CONFIG_TARGET_IOT_DEVKIT=y
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CONFIG_SYS_TEXT_BASE=0x20000000
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CONFIG_SYS_CLK_FREQ=16000000
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_SYS_PROMPT="IoTDK# "
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# CONFIG_CMD_BOOTD is not set
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# CONFIG_CMD_BOOTM is not set
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_NET is not set
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_EMBED=y
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CONFIG_DEFAULT_DEVICE_TREE="iot_devkit"
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CONFIG_ENV_IS_IN_FAT=y
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CONFIG_ENV_FAT_INTERFACE="mmc"
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CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
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CONFIG_DM=y
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CONFIG_MMC=y
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CONFIG_MMC_DW=y
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CONFIG_DM_SERIAL=y
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CONFIG_SYS_NS16550=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_DWC2_BUFFER_SIZE=16
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CONFIG_USB_STORAGE=y
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CONFIG_FS_FAT_MAX_CLUSTSIZE=4096
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84
include/configs/iot_devkit.h
Normal file
84
include/configs/iot_devkit.h
Normal file
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@ -0,0 +1,84 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
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*/
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#ifndef _CONFIG_IOT_DEVKIT_H_
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#define _CONFIG_IOT_DEVKIT_H_
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#include <linux/sizes.h>
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/*
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* MEMORY MAP
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*
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* eFlash: 0x0000_0000 - 0x0008_0000 (512K)
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* ICCM: 0x2000_0000 - 0x2004_0000 (256K)
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* SRAM: 0x3000_0000 - 0x3002_0000 (128K)
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* DCCM: 0x8000_0000 - 0x8002_0000 (128K)
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* Note: only data goes here, as IFQ cannot fetch instructions from DCCM
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*
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*
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* RAM PARTITIONING
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*
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* +-----------+----------+---------------------+-------------+
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* | <-- Stack | .data | Malloc | Environment |
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* +-----------+----------+---------------------+-------------+
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* : : : :\___________/
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* : : : : |
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* : : : : CONFIG_ENV_SIZE
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* : : \____________________/
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* : : |
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* : : CONFIG_SYS_MALLOC_LEN
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* : :
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* : Specified explicitly by CONFIG_SYS_INIT_SP_ADDR
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* :
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* Specified explicitly by CONFIG_SYS_SDRAM_BASE
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*
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* NOTES:
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* - Stack starts from CONFIG_SYS_INIT_SP_ADDR and grows down,
|
||||
* i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing
|
||||
* that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on
|
||||
* stack any longer and values popped from stack will contain garbage
|
||||
* leading to unexpected behavior, typically but not limited to:
|
||||
* - "Returning" back to bogus caller function
|
||||
* - Reading data from weird addresses
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define SRAM_BASE 0x30000000
|
||||
#define SRAM_SIZE SZ_128K
|
||||
|
||||
#define DCCM_BASE 0x80000000
|
||||
#define DCCM_SIZE SZ_128K
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE DCCM_BASE
|
||||
#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN SZ_64K
|
||||
#define CONFIG_SYS_BOOTM_LEN SZ_128K
|
||||
#define CONFIG_SYS_LOAD_ADDR SRAM_BASE
|
||||
|
||||
#define ROM_BASE CONFIG_SYS_MONITOR_BASE
|
||||
#define ROM_SIZE SZ_256K
|
||||
|
||||
#define RAM_DATA_BASE CONFIG_SYS_INIT_SP_ADDR
|
||||
#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \
|
||||
(CONFIG_SYS_INIT_SP_ADDR - \
|
||||
CONFIG_SYS_SDRAM_BASE) - \
|
||||
CONFIG_SYS_MALLOC_LEN - \
|
||||
CONFIG_ENV_SIZE
|
||||
|
||||
/* Required by DW MMC driver */
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE SZ_4K
|
||||
#define CONFIG_BOOTFILE "app.bin"
|
||||
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
||||
|
||||
#endif /* _CONFIG_IOT_DEVKIT_H_ */
|
||||
Loading…
Reference in a new issue