mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
parent
08a00cba06
commit
58008cbab5
20 changed files with 111 additions and 110 deletions
24
Kconfig
24
Kconfig
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@ -68,25 +68,25 @@ config CC_COVERAGE
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config DISTRO_DEFAULTS
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bool "Select defaults suitable for booting general purpose Linux distributions"
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imply USE_BOOTCOMMAND
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select CMD_BOOTZ if ARM && !ARM64
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select AUTO_COMPLETE
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select CMDLINE_EDITING
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select CMD_BOOTI if ARM64
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select CMD_BOOTZ if ARM && !ARM64
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select CMD_DHCP if CMD_NET
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select CMD_PING if CMD_NET
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select CMD_PXE if NET
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select CMD_ENV_EXISTS
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select CMD_EXT2
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select CMD_EXT4
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select CMD_FAT
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select CMD_FS_GENERIC
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imply CMD_MII if NET
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select CMD_PART if PARTITIONS
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select HUSH_PARSER
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select CMDLINE_EDITING
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select AUTO_COMPLETE
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select SYS_LONGHELP
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select SUPPORT_RAW_INITRD
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select CMD_PING if CMD_NET
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select CMD_PXE if NET
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select ENV_VARS_UBOOT_CONFIG
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select HUSH_PARSER
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select SUPPORT_RAW_INITRD
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select SYS_LONGHELP
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imply CMD_MII if NET
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imply USE_BOOTCOMMAND
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help
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Select this to enable various options and commands which are suitable
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for building u-boot for booting general purpose Linux distributions.
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@ -237,8 +237,8 @@ if FIT
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config FIT_ENABLE_SHA256_SUPPORT
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bool "Support SHA256 checksum of FIT image contents"
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select SHA256
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default y
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select SHA256
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help
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Enable this to support SHA256 checksum of FIT image contents. A
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SHA256 checksum is a 256-bit (32-byte) hash value used to check that
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@ -252,8 +252,8 @@ config FIT_ENABLE_SHA256_SUPPORT
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config FIT_SIGNATURE
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bool "Enable signature verification of FIT uImages"
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depends on DM
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select RSA
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select HASH
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select RSA
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help
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This option enables signature verification of FIT uImages,
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using a hash signed and verified using RSA. If
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@ -31,36 +31,36 @@ choice
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config CPU_ARC750D
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bool "ARC 750D"
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select ARC_MMU_V2
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depends on ISA_ARCOMPACT
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select ARC_MMU_V2
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help
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Choose this option to build an U-Boot for ARC750D CPU.
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config CPU_ARC770D
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bool "ARC 770D"
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select ARC_MMU_V3
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depends on ISA_ARCOMPACT
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select ARC_MMU_V3
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help
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Choose this option to build an U-Boot for ARC770D CPU.
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config CPU_ARCEM6
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bool "ARC EM6"
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select ARC_MMU_ABSENT
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depends on ISA_ARCV2
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select ARC_MMU_ABSENT
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help
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Next Generation ARC Core based on ISA-v2 ISA without MMU.
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config CPU_ARCHS36
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bool "ARC HS36"
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select ARC_MMU_ABSENT
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depends on ISA_ARCV2
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select ARC_MMU_ABSENT
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help
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Next Generation ARC Core based on ISA-v2 ISA without MMU.
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config CPU_ARCHS38
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bool "ARC HS38"
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select ARC_MMU_V4
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depends on ISA_ARCV2
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select ARC_MMU_V4
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help
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Next Generation ARC Core based on ISA-v2 ISA with MMU.
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@ -1,5 +1,7 @@
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config ARCH_LS1021A
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bool
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select SYS_FSL_DDR_BE if SYS_FSL_DDR
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_ERRATUM_A008378
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select SYS_FSL_ERRATUM_A008407
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select SYS_FSL_ERRATUM_A008997
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@ -10,18 +12,16 @@ config ARCH_LS1021A
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_HAS_CCI400
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR_BE if SYS_FSL_DDR
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
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select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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imply CMD_PCI
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imply SCSI
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imply SCSI_AHCI
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imply CMD_PCI
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menu "LS102xA architecture"
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depends on ARCH_LS1021A
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@ -44,8 +44,8 @@ config ARMV8_SPIN_TABLE
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menu "ARMv8 secure monitor firmware"
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config ARMV8_SEC_FIRMWARE_SUPPORT
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bool "Enable ARMv8 secure monitor firmware framework support"
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select OF_LIBFDT
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select FIT
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select OF_LIBFDT
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help
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This framework is aimed at making secure monitor firmware load
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process brief.
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@ -60,8 +60,8 @@ config ARMV8_SEC_FIRMWARE_SUPPORT
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config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
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bool "Enable ARMv8 secure monitor firmware framework support for SPL"
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select SPL_OF_LIBFDT
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select SPL_FIT
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select SPL_OF_LIBFDT
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help
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Say Y here to support this framework in SPL phase.
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@ -18,9 +18,9 @@ config TARGET_DA850EVM
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config TARGET_EA20
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bool "EA20 board"
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select BOARD_LATE_INIT
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select MACH_DAVINCI_DA850_EVM
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select SOC_DA850
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select BOARD_LATE_INIT
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config TARGET_OMAPL138_LCDK
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bool "OMAPL138 LCDK"
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@ -57,8 +57,8 @@ config SOC_DA850
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config SOC_DA8XX
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bool
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select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
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select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
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select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
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config MACH_DAVINCI_DA850_EVM
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bool
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@ -6,8 +6,8 @@ choice
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config ARCH_EXYNOS4
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bool "Exynos4 SoC family"
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select CPU_V7A
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select BOARD_EARLY_INIT_F
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select CPU_V7A
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help
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Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
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are multiple SoCs in this family including Exynos4210, Exynos4412,
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@ -15,14 +15,14 @@ config ARCH_EXYNOS4
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config ARCH_EXYNOS5
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bool "Exynos5 SoC family"
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select CPU_V7A
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select BOARD_EARLY_INIT_F
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select CPU_V7A
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select SHA_HW_ACCEL
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imply CRC32_VERIFY
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imply CMD_HASH
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imply CRC32_VERIFY
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imply HASH_VERIFY
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imply USB_ETHER_RTL8152
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imply USB_ETHER_ASIX
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imply USB_ETHER_RTL8152
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imply USB_ETHER_SMSC95XX
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help
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Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
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@ -46,9 +46,9 @@ choice
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prompt "EXYNOS4 board select"
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config TARGET_SMDKV310
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select SUPPORT_SPL
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bool "Exynos4210 SMDKV310 board"
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select OF_CONTROL
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select SUPPORT_SPL
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config TARGET_TRATS
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bool "Exynos4210 Trats board"
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@ -93,39 +93,39 @@ config TARGET_ARNDALE
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select ARM_ERRATA_774769
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select SUPPORT_SPL
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select OF_CONTROL
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select SUPPORT_SPL
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config TARGET_SMDK5250
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bool "SMDK5250 board"
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select SUPPORT_SPL
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select OF_CONTROL
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select SUPPORT_SPL
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config TARGET_SNOW
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bool "Snow board"
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select SUPPORT_SPL
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select OF_CONTROL
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select SUPPORT_SPL
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config TARGET_SPRING
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bool "Spring board"
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select SUPPORT_SPL
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select OF_CONTROL
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select SPL_DISABLE_OF_CONTROL
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select SUPPORT_SPL
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config TARGET_SMDK5420
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bool "SMDK5420 board"
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select SUPPORT_SPL
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select OF_CONTROL
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select SUPPORT_SPL
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config TARGET_PEACH_PI
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bool "Peach Pi board"
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select SUPPORT_SPL
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select OF_CONTROL
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select SUPPORT_SPL
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config TARGET_PEACH_PIT
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bool "Peach Pit board"
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select SUPPORT_SPL
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select OF_CONTROL
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select SUPPORT_SPL
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endchoice
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endif
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@ -139,12 +139,12 @@ config TARGET_ESPRESSO7420
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bool "ESPRESSO7420 board"
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select ARM64
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select ARMV8_MULTIENTRY
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select SUPPORT_SPL
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select CLK_EXYNOS
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select OF_CONTROL
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select SPL_DISABLE_OF_CONTROL
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select PINCTRL
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select PINCTRL_EXYNOS7420
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select CLK_EXYNOS
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select SPL_DISABLE_OF_CONTROL
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select SUPPORT_SPL
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endchoice
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endif
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@ -9,9 +9,9 @@ choice
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config TARGET_MX31PDK
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bool "Support the i.MX31 PDK board from Freescale/NXP"
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select SUPPORT_SPL
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select BOARD_EARLY_INIT_F
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endchoice
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@ -6,14 +6,14 @@ config HAVE_MVEBU_EFUSE
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config ARMADA_32BIT
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bool
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select ARCH_MISC_INIT
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select BOARD_EARLY_INIT_F
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select CPU_V7A
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select SUPPORT_SPL
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select SPL_DM
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select SPL_DM_SEQ_ALIAS
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select SPL_OF_CONTROL
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select SPL_SIMPLE_BUS
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select BOARD_EARLY_INIT_F
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select ARCH_MISC_INIT
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select SUPPORT_SPL
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config ARMADA_64BIT
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bool
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@ -6,11 +6,11 @@ choice
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config OMAP34XX
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bool "OMAP34XX SoC"
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select ARM_CORTEX_A8_CVE_2017_5715
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select ARM_ERRATA_430973
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select ARM_ERRATA_454179
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select ARM_ERRATA_621766
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select ARM_ERRATA_725233
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select ARM_CORTEX_A8_CVE_2017_5715
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select USE_TINY_PRINTF
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imply NAND_OMAP_GPMC
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imply SPL_EXT_SUPPORT
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@ -52,9 +52,9 @@ config OMAP44XX
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config OMAP54XX
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bool "OMAP54XX SoC"
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select ARM_CORTEX_A15_CVE_2017_5715
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select ARM_ERRATA_798870
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select SYS_THUMB_BUILD
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select ARM_CORTEX_A15_CVE_2017_5715
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imply NAND_OMAP_ELM
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imply NAND_OMAP_GPMC
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imply SPL_DISPLAY_PRINT
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@ -116,8 +116,8 @@ config AM43XX
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config AM33XX
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bool "AM33XX SoC"
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select SPECIFY_CONSOLE_INDEX
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select ARM_CORTEX_A8_CVE_2017_5715
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select SPECIFY_CONSOLE_INDEX
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imply NAND_OMAP_ELM
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imply NAND_OMAP_GPMC
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imply SPL_NAND_AM33XX_BCH
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@ -23,26 +23,26 @@ config TARGET_DRA7XX_EVM
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bool "TI DRA7XX"
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select BOARD_LATE_INIT
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select DRA7XX
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select TI_I2C_BOARD_DETECT
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select PHYS_64BIT
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imply SCSI
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select TI_I2C_BOARD_DETECT
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imply DM_PMIC
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imply PMIC_LP87565
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imply DM_REGULATOR
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imply DM_REGULATOR_LP87565
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imply SPL_THERMAL
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imply DM_THERMAL
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imply PMIC_LP87565
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imply SCSI
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imply SPL_THERMAL
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imply TI_DRA7_THERMAL
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config TARGET_AM57XX_EVM
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bool "AM57XX"
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select BOARD_LATE_INIT
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select CMD_DDR3
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select DRA7XX
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select TI_I2C_BOARD_DETECT
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select CMD_DDR3
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imply DM_THERMAL
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imply SCSI
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imply SPL_THERMAL
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imply DM_THERMAL
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imply TI_DRA7_THERMAL
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endchoice
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@ -14,8 +14,8 @@ endif
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config TARGET_QEMU_ARM_32BIT
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bool "Support qemu_arm"
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depends on ARCH_QEMU
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select CPU_V7A
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select ARCH_SUPPORT_PSCI
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select CPU_V7A
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select SYS_ARCH_TIMER
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config TARGET_QEMU_ARM_64BIT
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@ -87,22 +87,22 @@ config TARGET_POPMETAL_RK3288
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config TARGET_VYASA_RK3288
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bool "Vyasa-RK3288"
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select BOARD_LATE_INIT
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select TPL
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select SUPPORT_TPL
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select TPL_DM
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select TPL_REGMAP
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select TPL_SYSCON
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select TPL_CLK
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select TPL_RAM
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select TPL_OF_PLATDATA
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select TPL_OF_CONTROL
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select TPL_BOOTROM_SUPPORT
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select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
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select ROCKCHIP_BROM_HELPER
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select SUPPORT_TPL
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select TPL
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select TPL_BOOTROM_SUPPORT
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select TPL_CLK
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select TPL_DM
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select TPL_DRIVERS_MISC_SUPPORT
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select TPL_LIBCOMMON_SUPPORT
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select TPL_LIBGENERIC_SUPPORT
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select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
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select TPL_OF_CONTROL
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select TPL_OF_PLATDATA
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select TPL_RAM
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select TPL_REGMAP
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select TPL_SERIAL_SUPPORT
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select TPL_SYSCON
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help
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Vyasa is a RK3288-based development board with 2 USB ports,
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HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
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@ -9,8 +9,8 @@ config TARGET_SOCFPGA_ARRIA5
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config TARGET_SOCFPGA_ARRIA10
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bool
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select SPL_BOARD_INIT if SPL
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select ALTERA_SDRAM
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select SPL_BOARD_INIT if SPL
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config TARGET_SOCFPGA_CYCLONE5
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bool
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@ -23,8 +23,8 @@ config TARGET_SOCFPGA_GEN5
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config TARGET_SOCFPGA_STRATIX10
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bool
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select ARMV8_MULTIENTRY
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select ARMV8_SPIN_TABLE
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select ARMV8_SET_SMPEN
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select ARMV8_SPIN_TABLE
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choice
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prompt "Altera SOCFPGA board select"
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|
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@ -9,9 +9,9 @@ config STM32F4
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select PINCTRL
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select PINCTRL_STM32
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select RAM
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select STM32_SDRAM
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select STM32_RCC
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select STM32_RESET
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select STM32_SDRAM
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select STM32_SERIAL
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select STM32_TIMER
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select TIMER
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@ -25,13 +25,6 @@ config STM32F7
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select PINCTRL
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select PINCTRL_STM32
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select RAM
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select STM32_SDRAM
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select STM32_RCC
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select STM32_RESET
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select STM32_SERIAL
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select STM32_TIMER
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select TIMER
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select SUPPORT_SPL
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select SPL
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select SPL_BOARD_INIT
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select SPL_CLK
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@ -46,13 +39,20 @@ config STM32F7
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select SPL_OF_CONTROL
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select SPL_OF_LIBFDT
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select SPL_OF_TRANSLATE
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imply SPL_OS_BOOT
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select SPL_PINCTRL
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select SPL_RAM
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select SPL_SERIAL_SUPPORT
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select SPL_SYS_MALLOC_SIMPLE
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select SPL_TIMER
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select SPL_XIP_SUPPORT
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select STM32_RCC
|
||||
select STM32_RESET
|
||||
select STM32_SDRAM
|
||||
select STM32_SERIAL
|
||||
select STM32_TIMER
|
||||
select SUPPORT_SPL
|
||||
select TIMER
|
||||
imply SPL_OS_BOOT
|
||||
|
||||
config STM32H7
|
||||
bool "stm32h7 family"
|
||||
|
@ -64,9 +64,9 @@ config STM32H7
|
|||
select PINCTRL_STM32
|
||||
select RAM
|
||||
select REGMAP
|
||||
select STM32_SDRAM
|
||||
select STM32_RCC
|
||||
select STM32_RESET
|
||||
select STM32_SDRAM
|
||||
select STM32_SERIAL
|
||||
select STM32_TIMER
|
||||
select SYSCON
|
||||
|
|
|
@ -6,16 +6,16 @@ choice
|
|||
|
||||
config TARGET_APALIS_TK1
|
||||
bool "Toradex Apalis TK1 module"
|
||||
select ARCH_SUPPORT_PSCI
|
||||
select CPU_V7_HAS_NONSEC
|
||||
select CPU_V7_HAS_VIRT
|
||||
select ARCH_SUPPORT_PSCI
|
||||
|
||||
config TARGET_JETSON_TK1
|
||||
bool "NVIDIA Tegra124 Jetson TK1 board"
|
||||
select ARCH_SUPPORT_PSCI
|
||||
select BOARD_LATE_INIT
|
||||
select CPU_V7_HAS_NONSEC
|
||||
select CPU_V7_HAS_VIRT
|
||||
select ARCH_SUPPORT_PSCI
|
||||
|
||||
config TARGET_CEI_TK1_SOM
|
||||
bool "Colorado Engineering Inc Tegra124 TK1-som board"
|
||||
|
|
|
@ -5,10 +5,10 @@ config SYS_CONFIG_NAME
|
|||
|
||||
config ARCH_UNIPHIER_32BIT
|
||||
bool
|
||||
select ARCH_SUPPORT_PSCI
|
||||
select ARMV7_NONSEC
|
||||
select CPU_V7A
|
||||
select CPU_V7_HAS_NONSEC
|
||||
select ARMV7_NONSEC
|
||||
select ARCH_SUPPORT_PSCI
|
||||
|
||||
choice
|
||||
prompt "UniPhier SoC select"
|
||||
|
@ -69,6 +69,7 @@ config ARCH_UNIPHIER_LD20
|
|||
bool "Enable UniPhier LD20 SoC support"
|
||||
depends on ARCH_UNIPHIER_V8_MULTI
|
||||
default y
|
||||
select OF_BOARD_SETUP
|
||||
|
||||
config ARCH_UNIPHIER_PXS3
|
||||
bool "Enable UniPhier PXs3 SoC support"
|
||||
|
@ -78,8 +79,8 @@ config ARCH_UNIPHIER_PXS3
|
|||
config CACHE_UNIPHIER
|
||||
bool "Enable the UniPhier L2 cache controller"
|
||||
depends on ARCH_UNIPHIER_32BIT
|
||||
select SYS_CACHE_SHIFT_7
|
||||
default y
|
||||
select SYS_CACHE_SHIFT_7
|
||||
help
|
||||
This option allows to use the UniPhier System Cache as L2 cache.
|
||||
|
||||
|
|
|
@ -6,30 +6,30 @@ config SYS_SOC
|
|||
|
||||
config SOC_AR933X
|
||||
bool
|
||||
select MIPS_TUNE_24KC
|
||||
select ROM_EXCEPTION_VECTORS
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select SUPPORTS_CPU_MIPS32_R2
|
||||
select ROM_EXCEPTION_VECTORS
|
||||
select MIPS_TUNE_24KC
|
||||
help
|
||||
This supports QCA/Atheros ar933x family SOCs.
|
||||
|
||||
config SOC_AR934X
|
||||
bool
|
||||
select MIPS_TUNE_74KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select SUPPORTS_CPU_MIPS32_R2
|
||||
select MIPS_TUNE_74KC
|
||||
help
|
||||
This supports QCA/Atheros ar934x family SOCs.
|
||||
|
||||
config SOC_QCA953X
|
||||
bool
|
||||
select MIPS_TUNE_24KC
|
||||
select ROM_EXCEPTION_VECTORS
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select SUPPORTS_CPU_MIPS32_R2
|
||||
select ROM_EXCEPTION_VECTORS
|
||||
select MIPS_TUNE_24KC
|
||||
help
|
||||
This supports QCA/Atheros qca953x family SOCs.
|
||||
|
||||
|
|
|
@ -20,10 +20,10 @@ choice
|
|||
|
||||
config SOC_BMIPS_BCM3380
|
||||
bool "BMIPS BCM3380 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select MIPS_TUNE_4KC
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SWAP_IO_SPACE
|
||||
select SYSRESET_WATCHDOG
|
||||
help
|
||||
|
@ -31,10 +31,10 @@ config SOC_BMIPS_BCM3380
|
|||
|
||||
config SOC_BMIPS_BCM6318
|
||||
bool "BMIPS BCM6318 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select MIPS_TUNE_4KC
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SWAP_IO_SPACE
|
||||
select SYSRESET_SYSCON
|
||||
help
|
||||
|
@ -42,10 +42,10 @@ config SOC_BMIPS_BCM6318
|
|||
|
||||
config SOC_BMIPS_BCM6328
|
||||
bool "BMIPS BCM6328 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select MIPS_TUNE_4KC
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SWAP_IO_SPACE
|
||||
select SYSRESET_SYSCON
|
||||
help
|
||||
|
@ -53,10 +53,10 @@ config SOC_BMIPS_BCM6328
|
|||
|
||||
config SOC_BMIPS_BCM6338
|
||||
bool "BMIPS BCM6338 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select MIPS_TUNE_4KC
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SWAP_IO_SPACE
|
||||
select SYSRESET_SYSCON
|
||||
help
|
||||
|
@ -64,10 +64,10 @@ config SOC_BMIPS_BCM6338
|
|||
|
||||
config SOC_BMIPS_BCM6348
|
||||
bool "BMIPS BCM6348 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select MIPS_TUNE_4KC
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SWAP_IO_SPACE
|
||||
select SYSRESET_WATCHDOG
|
||||
help
|
||||
|
@ -75,10 +75,10 @@ config SOC_BMIPS_BCM6348
|
|||
|
||||
config SOC_BMIPS_BCM6358
|
||||
bool "BMIPS BCM6358 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select MIPS_TUNE_4KC
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SWAP_IO_SPACE
|
||||
select SYSRESET_SYSCON
|
||||
help
|
||||
|
@ -86,10 +86,10 @@ config SOC_BMIPS_BCM6358
|
|||
|
||||
config SOC_BMIPS_BCM6368
|
||||
bool "BMIPS BCM6368 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select MIPS_TUNE_4KC
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SWAP_IO_SPACE
|
||||
select SYSRESET_SYSCON
|
||||
help
|
||||
|
@ -97,10 +97,10 @@ config SOC_BMIPS_BCM6368
|
|||
|
||||
config SOC_BMIPS_BCM6362
|
||||
bool "BMIPS BCM6362 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select MIPS_TUNE_4KC
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SWAP_IO_SPACE
|
||||
select SYSRESET_SYSCON
|
||||
help
|
||||
|
@ -108,10 +108,10 @@ config SOC_BMIPS_BCM6362
|
|||
|
||||
config SOC_BMIPS_BCM63268
|
||||
bool "BMIPS BCM63268 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select MIPS_TUNE_4KC
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SWAP_IO_SPACE
|
||||
select SYSRESET_SYSCON
|
||||
help
|
||||
|
|
|
@ -9,12 +9,12 @@ choice
|
|||
|
||||
config SOC_PIC32MZDA
|
||||
bool "Microchip PIC32MZ[DA] family"
|
||||
select SUPPORTS_LITTLE_ENDIAN
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select ROM_EXCEPTION_VECTORS
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select SUPPORTS_CPU_MIPS32_R2
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
select ROM_EXCEPTION_VECTORS
|
||||
help
|
||||
This supports Microchip PIC32MZ[DA] family of microcontrollers.
|
||||
|
||||
|
|
|
@ -20,9 +20,9 @@ config MPC85xx
|
|||
select CREATE_ARCH_SYMLINK
|
||||
select SYS_FSL_DDR
|
||||
select SYS_FSL_DDR_BE
|
||||
imply USB_EHCI_HCD if USB
|
||||
imply CMD_HASH
|
||||
imply CMD_IRQ
|
||||
imply USB_EHCI_HCD if USB
|
||||
|
||||
config MPC86xx
|
||||
bool "MPC86xx"
|
||||
|
|
Loading…
Reference in a new issue