mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
This commit is contained in:
Tom Rini
commit
6d4a3ff264
31 changed files with 1269 additions and 346 deletions
|
|
@ -85,7 +85,7 @@
|
|||
};
|
||||
|
||||
qspi: qspi@2940000 {
|
||||
compatible = "cadence,qspi";
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compatible = "cdns,qspi-nor";
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#address-cells = <1>;
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||||
#size-cells = <0>;
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||||
reg = <0x02940000 0x1000>,
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|
|
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|||
|
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@ -1,9 +1,8 @@
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|||
// SPDX-License-Identifier: GPL-2.0+
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||||
/*
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* Copyright (C) 2012 Altera <www.altera.com>
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* Copyright (C) 2012 Altera <www.altera.com>
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*/
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||||
#include "skeleton.dtsi"
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#include <dt-bindings/reset/altr,rst-mgr.h>
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/ {
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|
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@ -11,34 +10,26 @@
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#size-cells = <1>;
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||||
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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serial0 = &uart0;
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serial1 = &uart1;
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timer0 = &timer0;
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timer1 = &timer1;
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timer2 = &timer2;
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timer3 = &timer3;
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spi0 = &qspi;
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spi1 = &spi0;
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spi2 = &spi1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "altr,socfpga-smp";
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cpu@0 {
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cpu0: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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||||
reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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cpu1: cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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|
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@ -46,6 +37,15 @@
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};
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};
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pmu: pmu@ff111000 {
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compatible = "arm,cortex-a9-pmu";
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interrupt-parent = <&intc>;
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interrupts = <0 176 4>, <0 177 4>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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reg = <0xff111000 0x1000>,
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<0xff113000 0x1000>;
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||||
};
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|
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intc: intc@fffed000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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|
|
@ -63,7 +63,7 @@
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ranges;
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amba {
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compatible = "arm,amba-bus";
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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||||
ranges;
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||||
|
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@ -87,6 +87,14 @@
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};
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};
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base_fpga_region {
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compatible = "fpga-region";
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fpga-mgr = <&fpgamgr0>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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};
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can0: can@ffc00000 {
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compatible = "bosch,d_can";
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reg = <0xffc00000 0x1000>;
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|
|
@ -131,7 +139,7 @@
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compatible = "fixed-clock";
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};
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|
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main_pll: main_pll {
|
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main_pll: main_pll@40 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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|
|
@ -139,7 +147,7 @@
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clocks = <&osc1>;
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reg = <0x40>;
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mpuclk: mpuclk {
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mpuclk: mpuclk@48 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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||||
|
|
@ -147,7 +155,7 @@
|
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reg = <0x48>;
|
||||
};
|
||||
|
||||
mainclk: mainclk {
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||||
mainclk: mainclk@4c {
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||||
#clock-cells = <0>;
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||||
compatible = "altr,socfpga-perip-clk";
|
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clocks = <&main_pll>;
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||||
|
|
@ -155,29 +163,29 @@
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|||
reg = <0x4C>;
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};
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||||
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dbg_base_clk: dbg_base_clk {
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dbg_base_clk: dbg_base_clk@50 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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clocks = <&main_pll>, <&osc1>;
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div-reg = <0xe8 0 9>;
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reg = <0x50>;
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||||
};
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main_qspi_clk: main_qspi_clk {
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main_qspi_clk: main_qspi_clk@54 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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reg = <0x54>;
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};
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||||
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||||
main_nand_sdmmc_clk: main_nand_sdmmc_clk {
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||||
main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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reg = <0x58>;
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};
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cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
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cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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|
@ -185,7 +193,7 @@
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};
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};
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periph_pll: periph_pll {
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periph_pll: periph_pll@80 {
|
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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@ -193,42 +201,42 @@
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clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
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reg = <0x80>;
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emac0_clk: emac0_clk {
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emac0_clk: emac0_clk@88 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x88>;
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};
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emac1_clk: emac1_clk {
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emac1_clk: emac1_clk@8c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x8C>;
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};
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per_qspi_clk: per_qsi_clk {
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per_qspi_clk: per_qsi_clk@90 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x90>;
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};
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per_nand_mmc_clk: per_nand_mmc_clk {
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per_nand_mmc_clk: per_nand_mmc_clk@94 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x94>;
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};
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|
||||
per_base_clk: per_base_clk {
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per_base_clk: per_base_clk@98 {
|
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x98>;
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};
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h2f_usr1_clk: h2f_usr1_clk {
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h2f_usr1_clk: h2f_usr1_clk@9c {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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@ -236,7 +244,7 @@
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};
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};
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sdram_pll: sdram_pll {
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sdram_pll: sdram_pll@c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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@ -244,28 +252,28 @@
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clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
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reg = <0xC0>;
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ddr_dqs_clk: ddr_dqs_clk {
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ddr_dqs_clk: ddr_dqs_clk@c8 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xC8>;
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};
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ddr_2x_dqs_clk: ddr_2x_dqs_clk {
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ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xCC>;
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};
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ddr_dq_clk: ddr_dq_clk {
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ddr_dq_clk: ddr_dq_clk@d0 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xD0>;
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};
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h2f_usr2_clk: h2f_usr2_clk {
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h2f_usr2_clk: h2f_usr2_clk@d4 {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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|
@ -312,7 +320,7 @@
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l3_sp_clk: l3_sp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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clocks = <&l3_mp_clk>;
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div-reg = <0x64 2 2>;
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};
|
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|
||||
|
|
@ -343,7 +351,7 @@
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dbg_clk: dbg_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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clocks = <&dbg_at_clk>;
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div-reg = <0x68 2 2>;
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clk-gate = <0x60 5>;
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};
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|
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@ -446,6 +454,14 @@
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clk-phase = <0 135>;
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};
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|
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sdmmc_clk_divided: sdmmc_clk_divided {
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#clock-cells = <0>;
|
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compatible = "altr,socfpga-gate-clk";
|
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clocks = <&sdmmc_clk>;
|
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clk-gate = <0xa0 8>;
|
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fixed-divider = <4>;
|
||||
};
|
||||
|
||||
nand_x_clk: nand_x_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
|
|
@ -453,10 +469,17 @@
|
|||
clk-gate = <0xa0 9>;
|
||||
};
|
||||
|
||||
nand_ecc_clk: nand_ecc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&nand_x_clk>;
|
||||
clk-gate = <0xa0 9>;
|
||||
};
|
||||
|
||||
nand_clk: nand_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clocks = <&nand_x_clk>;
|
||||
clk-gate = <0xa0 10>;
|
||||
fixed-divider = <4>;
|
||||
};
|
||||
|
|
@ -467,8 +490,58 @@
|
|||
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
|
||||
clk-gate = <0xa0 11>;
|
||||
};
|
||||
|
||||
ddr_dqs_clk_gate: ddr_dqs_clk_gate {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&ddr_dqs_clk>;
|
||||
clk-gate = <0xd8 0>;
|
||||
};
|
||||
|
||||
ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&ddr_2x_dqs_clk>;
|
||||
clk-gate = <0xd8 1>;
|
||||
};
|
||||
|
||||
ddr_dq_clk_gate: ddr_dq_clk_gate {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&ddr_dq_clk>;
|
||||
clk-gate = <0xd8 2>;
|
||||
};
|
||||
|
||||
h2f_user2_clk: h2f_user2_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&h2f_usr2_clk>;
|
||||
clk-gate = <0xd8 3>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fpga_bridge0: fpga_bridge@ff400000 {
|
||||
compatible = "altr,socfpga-lwhps2fpga-bridge";
|
||||
reg = <0xff400000 0x100000>;
|
||||
resets = <&rst LWHPS2FPGA_RESET>;
|
||||
clocks = <&l4_main_clk>;
|
||||
};
|
||||
|
||||
fpga_bridge1: fpga_bridge@ff500000 {
|
||||
compatible = "altr,socfpga-hps2fpga-bridge";
|
||||
reg = <0xff500000 0x10000>;
|
||||
resets = <&rst HPS2FPGA_RESET>;
|
||||
clocks = <&l4_main_clk>;
|
||||
};
|
||||
|
||||
fpgamgr0: fpgamgr@ff706000 {
|
||||
compatible = "altr,socfpga-fpga-mgr";
|
||||
reg = <0xff706000 0x1000
|
||||
0xffb90000 0x4>;
|
||||
interrupts = <0 175 4>;
|
||||
};
|
||||
|
||||
gmac0: ethernet@ff700000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
|
||||
|
|
@ -477,12 +550,14 @@
|
|||
interrupts = <0 115 4>;
|
||||
interrupt-names = "macirq";
|
||||
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
|
||||
clocks = <&emac0_clk>;
|
||||
clocks = <&emac_0_clk>;
|
||||
clock-names = "stmmaceth";
|
||||
resets = <&rst EMAC0_RESET>;
|
||||
reset-names = "stmmaceth";
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
tx-fifo-depth = <4096>;
|
||||
rx-fifo-depth = <4096>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -493,60 +568,14 @@
|
|||
interrupts = <0 120 4>;
|
||||
interrupt-names = "macirq";
|
||||
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
|
||||
clocks = <&emac1_clk>;
|
||||
clocks = <&emac_1_clk>;
|
||||
clock-names = "stmmaceth";
|
||||
resets = <&rst EMAC1_RESET>;
|
||||
reset-names = "stmmaceth";
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@ffc04000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc04000 0x1000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
resets = <&rst I2C0_RESET>;
|
||||
reset-names = "i2c";
|
||||
interrupts = <0 158 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@ffc05000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc05000 0x1000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
resets = <&rst I2C1_RESET>;
|
||||
reset-names = "i2c";
|
||||
interrupts = <0 159 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@ffc06000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc06000 0x1000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
resets = <&rst I2C2_RESET>;
|
||||
reset-names = "i2c";
|
||||
interrupts = <0 160 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@ffc07000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc07000 0x1000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
resets = <&rst I2C3_RESET>;
|
||||
reset-names = "i2c";
|
||||
interrupts = <0 161 0x4>;
|
||||
tx-fifo-depth = <4096>;
|
||||
rx-fifo-depth = <4096>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -555,12 +584,11 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff708000 0x1000>;
|
||||
clocks = <&per_base_clk>;
|
||||
clocks = <&l4_mp_clk>;
|
||||
status = "disabled";
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "porta";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <29>;
|
||||
|
|
@ -576,12 +604,11 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff709000 0x1000>;
|
||||
clocks = <&per_base_clk>;
|
||||
clocks = <&l4_mp_clk>;
|
||||
status = "disabled";
|
||||
|
||||
portb: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portb";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <29>;
|
||||
|
|
@ -597,12 +624,11 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff70a000 0x1000>;
|
||||
clocks = <&per_base_clk>;
|
||||
clocks = <&l4_mp_clk>;
|
||||
status = "disabled";
|
||||
|
||||
portc: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
bank-name = "portc";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <27>;
|
||||
|
|
@ -613,15 +639,68 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdr: sdr@ffc25000 {
|
||||
compatible = "syscon";
|
||||
reg = <0xffc25000 0x1000>;
|
||||
i2c0: i2c@ffc04000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc04000 0x1000>;
|
||||
resets = <&rst I2C0_RESET>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
interrupts = <0 158 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdramedac {
|
||||
compatible = "altr,sdram-edac";
|
||||
altr,sdr-syscon = <&sdr>;
|
||||
interrupts = <0 39 4>;
|
||||
i2c1: i2c@ffc05000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc05000 0x1000>;
|
||||
resets = <&rst I2C1_RESET>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
interrupts = <0 159 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@ffc06000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc06000 0x1000>;
|
||||
resets = <&rst I2C2_RESET>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
interrupts = <0 160 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@ffc07000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc07000 0x1000>;
|
||||
resets = <&rst I2C3_RESET>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
interrupts = <0 161 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eccmgr: eccmgr {
|
||||
compatible = "altr,socfpga-ecc-manager";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
l2-ecc@ffd08140 {
|
||||
compatible = "altr,socfpga-l2-ecc";
|
||||
reg = <0xffd08140 0x4>;
|
||||
interrupts = <0 36 1>, <0 37 1>;
|
||||
};
|
||||
|
||||
ocram-ecc@ffd08144 {
|
||||
compatible = "altr,socfpga-ocram-ecc";
|
||||
reg = <0xffd08144 0x4>;
|
||||
iram = <&ocram>;
|
||||
interrupts = <0 178 1>, <0 179 1>;
|
||||
};
|
||||
};
|
||||
|
||||
L2: l2-cache@fffef000 {
|
||||
|
|
@ -632,36 +711,89 @@
|
|||
cache-level = <2>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
arm,data-latency = <2 1 1>;
|
||||
prefetch-data = <1>;
|
||||
prefetch-instr = <1>;
|
||||
arm,shared-override;
|
||||
arm,double-linefill = <1>;
|
||||
arm,double-linefill-incr = <0>;
|
||||
arm,double-linefill-wrap = <1>;
|
||||
arm,prefetch-drop = <0>;
|
||||
arm,prefetch-offset = <7>;
|
||||
};
|
||||
|
||||
mmc0: dwmmc0@ff704000 {
|
||||
l3regs@0xff800000 {
|
||||
compatible = "altr,l3regs", "syscon";
|
||||
reg = <0xff800000 0x1000>;
|
||||
};
|
||||
|
||||
mmc: dwmmc0@ff704000 {
|
||||
compatible = "altr,socfpga-dw-mshc";
|
||||
reg = <0xff704000 0x1000>;
|
||||
interrupts = <0 139 4>;
|
||||
fifo-depth = <0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
|
||||
clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
|
||||
clock-names = "biu", "ciu";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand0: nand@ff900000 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "altr,socfpga-denali-nand";
|
||||
reg = <0xff900000 0x100000>,
|
||||
<0xffb80000 0x10000>;
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
interrupts = <0x0 0x90 0x4>;
|
||||
dma-mask = <0xffffffff>;
|
||||
clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
|
||||
clock-names = "nand", "nand_x", "ecc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ocram: sram@ffff0000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xffff0000 0x10000>;
|
||||
};
|
||||
|
||||
qspi: spi@ff705000 {
|
||||
compatible = "cadence,qspi";
|
||||
#address-cells = <1>;
|
||||
compatible = "cdns,qspi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xff705000 0x1000>,
|
||||
<0xffa00000 0x1000>;
|
||||
<0xffa00000 0x1000>;
|
||||
interrupts = <0 151 4>;
|
||||
clocks = <&qspi_clk>;
|
||||
ext-decoder = <0>; /* external decoder */
|
||||
num-cs = <4>;
|
||||
cdns,fifo-depth = <128>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x00000000>;
|
||||
bus-num = <2>;
|
||||
clocks = <&qspi_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rst: rstmgr@ffd05000 {
|
||||
#reset-cells = <1>;
|
||||
compatible = "altr,rst-mgr";
|
||||
reg = <0xffd05000 0x1000>;
|
||||
altr,modrst-offset = <0x10>;
|
||||
};
|
||||
|
||||
scu: snoop-control-unit@fffec000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xfffec000 0x100>;
|
||||
};
|
||||
|
||||
sdr: sdr@ffc25000 {
|
||||
compatible = "altr,sdr-ctl", "syscon";
|
||||
reg = <0xffc25000 0x1000>;
|
||||
};
|
||||
|
||||
sdramedac {
|
||||
compatible = "altr,sdram-edac";
|
||||
altr,sdr-syscon = <&sdr>;
|
||||
interrupts = <0 39 4>;
|
||||
};
|
||||
|
||||
spi0: spi@fff00000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -669,10 +801,7 @@
|
|||
reg = <0xfff00000 0x1000>;
|
||||
interrupts = <0 154 4>;
|
||||
num-cs = <4>;
|
||||
bus-num = <0>;
|
||||
tx-dma-channel = <&pdma 16>;
|
||||
rx-dma-channel = <&pdma 17>;
|
||||
clocks = <&per_base_clk>;
|
||||
clocks = <&spi_m_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -681,20 +810,22 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xfff01000 0x1000>;
|
||||
interrupts = <0 156 4>;
|
||||
interrupts = <0 155 4>;
|
||||
num-cs = <4>;
|
||||
bus-num = <1>;
|
||||
tx-dma-channel = <&pdma 20>;
|
||||
rx-dma-channel = <&pdma 21>;
|
||||
clocks = <&per_base_clk>;
|
||||
clocks = <&spi_m_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sysmgr: sysmgr@ffd08000 {
|
||||
compatible = "altr,sys-mgr", "syscon";
|
||||
reg = <0xffd08000 0x4000>;
|
||||
};
|
||||
|
||||
/* Local timer */
|
||||
timer@fffec600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xfffec600 0x100>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
interrupts = <1 13 0xf01>;
|
||||
clocks = <&mpu_periph_clk>;
|
||||
};
|
||||
|
||||
|
|
@ -704,6 +835,8 @@
|
|||
reg = <0xffc08000 0x1000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
clock-names = "timer";
|
||||
resets = <&rst SPTIMER0_RESET>;
|
||||
reset-names = "timer";
|
||||
};
|
||||
|
||||
timer1: timer1@ffc09000 {
|
||||
|
|
@ -712,6 +845,8 @@
|
|||
reg = <0xffc09000 0x1000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
clock-names = "timer";
|
||||
resets = <&rst SPTIMER1_RESET>;
|
||||
reset-names = "timer";
|
||||
};
|
||||
|
||||
timer2: timer2@ffd00000 {
|
||||
|
|
@ -720,6 +855,8 @@
|
|||
reg = <0xffd00000 0x1000>;
|
||||
clocks = <&osc1>;
|
||||
clock-names = "timer";
|
||||
resets = <&rst OSC1TIMER0_RESET>;
|
||||
reset-names = "timer";
|
||||
};
|
||||
|
||||
timer3: timer3@ffd01000 {
|
||||
|
|
@ -728,6 +865,8 @@
|
|||
reg = <0xffd01000 0x1000>;
|
||||
clocks = <&osc1>;
|
||||
clock-names = "timer";
|
||||
resets = <&rst OSC1TIMER1_RESET>;
|
||||
reset-names = "timer";
|
||||
};
|
||||
|
||||
uart0: serial0@ffc02000 {
|
||||
|
|
@ -737,7 +876,9 @@
|
|||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
clock-frequency = <100000000>;
|
||||
dmas = <&pdma 28>,
|
||||
<&pdma 29>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart1: serial1@ffc03000 {
|
||||
|
|
@ -747,16 +888,12 @@
|
|||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
clock-frequency = <100000000>;
|
||||
dmas = <&pdma 30>,
|
||||
<&pdma 31>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
rst: rstmgr@ffd05000 {
|
||||
#reset-cells = <1>;
|
||||
compatible = "altr,rst-mgr";
|
||||
reg = <0xffd05000 0x1000>;
|
||||
};
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
usbphy0: usbphy {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
status = "okay";
|
||||
|
|
@ -768,6 +905,8 @@
|
|||
interrupts = <0 125 4>;
|
||||
clocks = <&usb_mp_clk>;
|
||||
clock-names = "otg";
|
||||
resets = <&rst USB0_RESET>;
|
||||
reset-names = "dwc2";
|
||||
phys = <&usbphy0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
|
|
@ -779,6 +918,8 @@
|
|||
interrupts = <0 128 4>;
|
||||
clocks = <&usb_mp_clk>;
|
||||
clock-names = "otg";
|
||||
resets = <&rst USB1_RESET>;
|
||||
reset-names = "dwc2";
|
||||
phys = <&usbphy0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
|
|
@ -799,10 +940,5 @@
|
|||
clocks = <&osc1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sysmgr: sysmgr@ffd08000 {
|
||||
compatible = "altr,sys-mgr", "syscon";
|
||||
reg = <0xffd08000 0x4000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -748,7 +748,7 @@
|
|||
};
|
||||
|
||||
qspi: spi@ff809000 {
|
||||
compatible = "cdns,qspi-nor", "cadence,qspi";
|
||||
compatible = "cdns,qspi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xff809000 0x100>,
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com>
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -19,13 +19,10 @@
|
|||
};
|
||||
|
||||
mmc0: dwmmc0@ff704000 {
|
||||
num-slots = <1>;
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
drvsel = <3>;
|
||||
smplsel = <0>;
|
||||
};
|
||||
|
||||
sysmgr@ffd08000 {
|
||||
|
|
@ -33,3 +30,7 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
56
arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
Normal file
56
arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* U-Boot additions
|
||||
*
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com>
|
||||
* Copyright (c) 2018 Simon Goldschmidt
|
||||
*/
|
||||
|
||||
/{
|
||||
aliases {
|
||||
spi0 = "/soc/spi@ff705000";
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&flash {
|
||||
compatible = "n25q00", "spi-flash";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com>
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com>
|
||||
*/
|
||||
|
||||
#include "socfpga_arria5.dtsi"
|
||||
|
|
@ -10,22 +10,44 @@
|
|||
compatible = "altr,socfpga-arria5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
bootargs = "earlyprintk";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
/* this allow the ethaddr uboot environment variable contents
|
||||
* to be added to the gmac1 device tree blob.
|
||||
*/
|
||||
/* this allow the ethaddr uboot environmnet variable contents
|
||||
* to be added to the gmac1 device tree blob.
|
||||
*/
|
||||
ethernet0 = &gmac1;
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
hps0 {
|
||||
label = "hps_led0";
|
||||
gpios = <&porta 0 1>;
|
||||
};
|
||||
|
||||
hps1 {
|
||||
label = "hps_led1";
|
||||
gpios = <&portb 11 1>;
|
||||
};
|
||||
|
||||
hps2 {
|
||||
label = "hps_led2";
|
||||
gpios = <&porta 17 1>;
|
||||
};
|
||||
|
||||
hps3 {
|
||||
label = "hps_led3";
|
||||
gpios = <&porta 18 1>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator_3_3v: 3-3-v-regulator {
|
||||
|
|
@ -34,10 +56,6 @@
|
|||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
|
|
@ -54,8 +72,28 @@
|
|||
rxc-skew-ps = <2000>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/*
|
||||
* adjust the falling times to decrease the i2c frequency to 50Khz
|
||||
* because the LCD module does not work at the standard 100Khz
|
||||
*/
|
||||
i2c-sda-falling-time-ns = <5000>;
|
||||
i2c-scl-falling-time-ns = <5000>;
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c32";
|
||||
|
|
@ -72,35 +110,42 @@
|
|||
&mmc0 {
|
||||
vmmc-supply = <®ulator_3_3v>;
|
||||
vqmmc-supply = <®ulator_3_3v>;
|
||||
bus-width = <4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
flash0: n25q00@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
flash: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q00", "spi-flash";
|
||||
reg = <0>; /* chip select */
|
||||
spi-max-frequency = <50000000>;
|
||||
compatible = "n25q256a";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
m25p,fast-read;
|
||||
page-size = <256>;
|
||||
block-size = <16>; /* 2^16, 64KB */
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
|
||||
partition@qspi-boot {
|
||||
/* 8MB for raw data. */
|
||||
label = "Flash 0 Raw Data";
|
||||
reg = <0x0 0x800000>;
|
||||
};
|
||||
|
||||
partition@qspi-rootfs {
|
||||
/* 120MB for jffs2 data. */
|
||||
label = "Flash 0 jffs2 Filesystem";
|
||||
reg = <0x800000 0x7800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -19,13 +19,10 @@
|
|||
};
|
||||
|
||||
mmc0: dwmmc0@ff704000 {
|
||||
num-slots = <1>;
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
drvsel = <3>;
|
||||
smplsel = <0>;
|
||||
};
|
||||
|
||||
sysmgr@ffd08000 {
|
||||
|
|
@ -33,3 +30,7 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -47,9 +47,20 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
|
|
@ -61,3 +72,7 @@
|
|||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
46
arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
Normal file
46
arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* U-Boot additions
|
||||
*
|
||||
* Copyright Altera Corporation (C) 2015
|
||||
* Copyright (c) 2018 Simon Goldschmidt
|
||||
*/
|
||||
|
||||
/{
|
||||
aliases {
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
|
@ -1,32 +1,43 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright Altera Corporation (C) 2015
|
||||
* Copyright Altera Corporation (C) 2015. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Terasic DE0-Nano(Atlas)";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
model = "Terasic DE-0(Atlas)";
|
||||
compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
bootargs = "earlyprintk";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
};
|
||||
|
||||
regulator_3_3v: 3-3-v-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
hps0 {
|
||||
label = "hps_led0";
|
||||
gpios = <&portb 24 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -34,14 +45,20 @@
|
|||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
|
||||
rxd0-skew-ps = <420>;
|
||||
rxd1-skew-ps = <420>;
|
||||
rxd2-skew-ps = <420>;
|
||||
rxd3-skew-ps = <420>;
|
||||
txen-skew-ps = <0>;
|
||||
txc-skew-ps = <1860>;
|
||||
rxdv-skew-ps = <420>;
|
||||
rxc-skew-ps = <1680>;
|
||||
txd0-skew-ps = <0>; /* -420ps */
|
||||
txd1-skew-ps = <0>; /* -420ps */
|
||||
txd2-skew-ps = <0>; /* -420ps */
|
||||
txd3-skew-ps = <0>; /* -420ps */
|
||||
rxd0-skew-ps = <420>; /* 0ps */
|
||||
rxd1-skew-ps = <420>; /* 0ps */
|
||||
rxd2-skew-ps = <420>; /* 0ps */
|
||||
rxd3-skew-ps = <420>; /* 0ps */
|
||||
txen-skew-ps = <0>; /* -420ps */
|
||||
txc-skew-ps = <1860>; /* 960ps */
|
||||
rxdv-skew-ps = <420>; /* 0ps */
|
||||
rxc-skew-ps = <1680>; /* 780ps */
|
||||
|
||||
max-frame-size = <3800>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
|
|
@ -58,8 +75,9 @@
|
|||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
dxl345: adxl345@0 {
|
||||
adxl345: adxl345@53 {
|
||||
compatible = "adi,adxl345";
|
||||
reg = <0x53>;
|
||||
|
||||
|
|
@ -69,14 +87,15 @@
|
|||
};
|
||||
|
||||
&mmc0 {
|
||||
vmmc-supply = <®ulator_3_3v>;
|
||||
vqmmc-supply = <®ulator_3_3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -58,6 +58,18 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
|
@ -70,3 +82,7 @@
|
|||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -56,6 +56,18 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
|
@ -68,3 +80,7 @@
|
|||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -55,6 +55,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -107,3 +111,7 @@
|
|||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
72
arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
Normal file
72
arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* U-Boot additions
|
||||
*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
* Copyright (c) 2018 Simon Goldschmidt
|
||||
*/
|
||||
|
||||
/{
|
||||
aliases {
|
||||
spi0 = "/soc/spi@ff705000";
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
compatible = "n25q00", "spi-flash";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
partition@qspi-boot {
|
||||
/* 8MB for raw data. */
|
||||
label = "Flash 0 Raw Data";
|
||||
reg = <0x0 0x800000>;
|
||||
};
|
||||
|
||||
partition@qspi-rootfs {
|
||||
/* 120MB for jffs2 data. */
|
||||
label = "Flash 0 jffs2 Filesystem";
|
||||
reg = <0x800000 0x7800000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
|
@ -1,31 +1,53 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*/
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Altera SOCFPGA Cyclone V SoC Development Kit";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
bootargs = "earlyprintk";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
/* this allow the ethaddr uboot environment variable contents
|
||||
/* this allow the ethaddr uboot environmnet variable contents
|
||||
* to be added to the gmac1 device tree blob.
|
||||
*/
|
||||
ethernet0 = &gmac1;
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
hps0 {
|
||||
label = "hps_led0";
|
||||
gpios = <&portb 15 1>;
|
||||
};
|
||||
|
||||
hps1 {
|
||||
label = "hps_led1";
|
||||
gpios = <&portb 14 1>;
|
||||
};
|
||||
|
||||
hps2 {
|
||||
label = "hps_led2";
|
||||
gpios = <&portb 13 1>;
|
||||
};
|
||||
|
||||
hps3 {
|
||||
label = "hps_led3";
|
||||
gpios = <&portb 12 1>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator_3_3v: 3-3-v-regulator {
|
||||
|
|
@ -34,10 +56,10 @@
|
|||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
&can0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
|
|
@ -68,6 +90,14 @@
|
|||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/*
|
||||
* adjust the falling times to decrease the i2c frequency to 50Khz
|
||||
* because the LCD module does not work at the standard 100Khz
|
||||
*/
|
||||
i2c-sda-falling-time-ns = <5000>;
|
||||
i2c-scl-falling-time-ns = <5000>;
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c32";
|
||||
|
|
@ -82,39 +112,55 @@
|
|||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cd-gpios = <&portb 18 0>;
|
||||
vmmc-supply = <®ulator_3_3v>;
|
||||
vqmmc-supply = <®ulator_3_3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
flash0: n25q00@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q00", "spi-flash";
|
||||
reg = <0>; /* chip select */
|
||||
compatible = "n25q00";
|
||||
reg = <0>; /* chip select */
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
m25p,fast-read;
|
||||
page-size = <256>;
|
||||
block-size = <16>; /* 2^16, 64KB */
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
|
||||
partition@qspi-boot {
|
||||
/* 8MB for raw data. */
|
||||
label = "Flash 0 Raw Data";
|
||||
reg = <0x0 0x800000>;
|
||||
};
|
||||
|
||||
partition@qspi-rootfs {
|
||||
/* 120MB for jffs2 data. */
|
||||
label = "Flash 0 jffs2 Filesystem";
|
||||
reg = <0x800000 0x7800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spidev@0 {
|
||||
compatible = "rohm,dh2228fv";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
|
|||
56
arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
Normal file
56
arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* U-Boot additions
|
||||
*
|
||||
* Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
* Copyright (c) 2018 Simon Goldschmidt
|
||||
*/
|
||||
|
||||
/{
|
||||
aliases {
|
||||
spi0 = "/soc/spi@ff705000";
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&flash {
|
||||
compatible = "n25q00", "spi-flash";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
|
@ -1,32 +1,121 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
* Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*/
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Terasic SoCkit";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
bootargs = "earlyprintk";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
aliases {
|
||||
/* this allow the ethaddr uboot environmnet variable contents
|
||||
* to be added to the gmac1 device tree blob.
|
||||
*/
|
||||
ethernet0 = &gmac1;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
hps_led0 {
|
||||
label = "hps:blue:led0";
|
||||
gpios = <&portb 24 0>; /* HPS_GPIO53 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
hps_led1 {
|
||||
label = "hps:blue:led1";
|
||||
gpios = <&portb 25 0>; /* HPS_GPIO54 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
hps_led2 {
|
||||
label = "hps:blue:led2";
|
||||
gpios = <&portb 26 0>; /* HPS_GPIO55 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
hps_led3 {
|
||||
label = "hps:blue:led3";
|
||||
gpios = <&portb 27 0>; /* HPS_GPIO56 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
hps_sw0 {
|
||||
label = "hps_sw0";
|
||||
gpios = <&portc 20 0>; /* HPS_GPI7 */
|
||||
linux,input-type = <5>; /* EV_SW */
|
||||
linux,code = <0x0>; /* SW_LID */
|
||||
};
|
||||
|
||||
hps_sw1 {
|
||||
label = "hps_sw1";
|
||||
gpios = <&portc 19 0>; /* HPS_GPI6 */
|
||||
linux,input-type = <5>; /* EV_SW */
|
||||
linux,code = <0x5>; /* SW_DOCK */
|
||||
};
|
||||
|
||||
hps_sw2 {
|
||||
label = "hps_sw2";
|
||||
gpios = <&portc 18 0>; /* HPS_GPI5 */
|
||||
linux,input-type = <5>; /* EV_SW */
|
||||
linux,code = <0xa>; /* SW_KEYPAD_SLIDE */
|
||||
};
|
||||
|
||||
hps_sw3 {
|
||||
label = "hps_sw3";
|
||||
gpios = <&portc 17 0>; /* HPS_GPI4 */
|
||||
linux,input-type = <5>; /* EV_SW */
|
||||
linux,code = <0xc>; /* SW_ROTATE_LOCK */
|
||||
};
|
||||
|
||||
hps_hkey0 {
|
||||
label = "hps_hkey0";
|
||||
gpios = <&portc 21 1>; /* HPS_GPI8 */
|
||||
linux,code = <187>; /* KEY_F17 */
|
||||
};
|
||||
|
||||
hps_hkey1 {
|
||||
label = "hps_hkey1";
|
||||
gpios = <&portc 22 1>; /* HPS_GPI9 */
|
||||
linux,code = <188>; /* KEY_F18 */
|
||||
};
|
||||
|
||||
hps_hkey2 {
|
||||
label = "hps_hkey2";
|
||||
gpios = <&portc 23 1>; /* HPS_GPI10 */
|
||||
linux,code = <189>; /* KEY_F19 */
|
||||
};
|
||||
|
||||
hps_hkey3 {
|
||||
label = "hps_hkey3";
|
||||
gpios = <&portc 24 1>; /* HPS_GPI11 */
|
||||
linux,code = <190>; /* KEY_F20 */
|
||||
};
|
||||
};
|
||||
|
||||
regulator_3_3v: vcc3p3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC3P3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -44,46 +133,50 @@
|
|||
rxc-skew-ps = <2000>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
&gpio0 { /* GPIO 0..29 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
&gpio1 { /* GPIO 30..57 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t82";
|
||||
reg = <0x68>;
|
||||
accel1: accelerometer@53 {
|
||||
compatible = "adi,adxl345";
|
||||
reg = <0x53>;
|
||||
|
||||
interrupt-parent = <&portc>;
|
||||
interrupts = <3 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
vmmc-supply = <®ulator_3_3v>;
|
||||
vqmmc-supply = <®ulator_3_3v>;
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
flash0: n25q00@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
flash: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q00", "spi-flash";
|
||||
reg = <0>; /* chip select */
|
||||
spi-max-frequency = <50000000>;
|
||||
compatible = "n25q00";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
m25p,fast-read;
|
||||
page-size = <256>;
|
||||
block-size = <16>; /* 2^16, 64KB */
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
|
|
@ -94,7 +187,3 @@
|
|||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
|
|||
60
arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
Normal file
60
arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* U-Boot additions
|
||||
*
|
||||
* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
* Copyright (c) 2018 Simon Goldschmidt
|
||||
*/
|
||||
|
||||
/{
|
||||
aliases {
|
||||
spi0 = "/soc/spi@ff705000";
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&flash {
|
||||
compatible = "n25q256a", "spi-flash";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*/
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
|
@ -9,83 +9,88 @@
|
|||
model = "EBV SOCrates";
|
||||
compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
bootargs = "earlyprintk";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
/*
|
||||
* This allows the ethaddr uboot environment variable
|
||||
* contents to be added to the gmac1 device tree blob.
|
||||
*/
|
||||
ethernet0 = &gmac1;
|
||||
udc0 = &usb1;
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
leds: gpio-leds {
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txen-skew-ps = <0>;
|
||||
txc-skew-ps = <2600>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxc-skew-ps = <2000>;
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t82";
|
||||
compatible = "st,m41t82";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
&leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led0 {
|
||||
label = "led:green:heartbeat";
|
||||
gpios = <&porta 28 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led1 {
|
||||
label = "led:green:D7";
|
||||
gpios = <&portb 19 1>;
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "led:green:D8";
|
||||
gpios = <&portb 25 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
flash0: n25q00@0 {
|
||||
flash: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q00", "spi-flash";
|
||||
reg = <0>; /* chip select */
|
||||
spi-max-frequency = <50000000>;
|
||||
compatible = "n25q256a";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000000>;
|
||||
m25p,fast-read;
|
||||
page-size = <256>;
|
||||
block-size = <16>; /* 2^16, 64KB */
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -50,6 +50,18 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
speed-mode = <0>;
|
||||
|
|
|
|||
60
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
Normal file
60
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
|
||||
/*
|
||||
* U-Boot additions
|
||||
*
|
||||
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
|
||||
* Copyright (c) 2018 Simon Goldschmidt
|
||||
*/
|
||||
|
||||
/{
|
||||
aliases {
|
||||
spi0 = "/soc/spi@ff705000";
|
||||
udc0 = &usb0;
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
n25q128@0 {
|
||||
compatible = "n25q128", "spi-flash";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
n25q00@1 {
|
||||
compatible = "n25q00", "spi-flash";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <100000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&porta {
|
||||
bank-name = "porta";
|
||||
};
|
||||
|
||||
&portb {
|
||||
bank-name = "portb";
|
||||
};
|
||||
|
||||
&portc {
|
||||
bank-name = "portc";
|
||||
};
|
||||
|
|
@ -1,100 +1,238 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
|
||||
/*
|
||||
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "samtec VIN|ING FPGA";
|
||||
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
bootargs = "earlyprintk";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
udc0 = &usb0;
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
aliases {
|
||||
/*
|
||||
* This allow the ethaddr uboot environment variable contents
|
||||
* to be added to the gmac1 device tree blob.
|
||||
*/
|
||||
ethernet0 = &gmac1;
|
||||
ethernet1 = &gmac0;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
hps_temp0 {
|
||||
label = "BTN_0"; /* TEMP_OS */
|
||||
gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */
|
||||
linux,code = <BTN_0>;
|
||||
};
|
||||
|
||||
hps_hkey0 {
|
||||
label = "BTN_1"; /* DIS_PWR */
|
||||
gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */
|
||||
linux,code = <BTN_1>;
|
||||
};
|
||||
|
||||
hps_hkey1 {
|
||||
label = "hps_hkey1"; /* POWER_DOWN */
|
||||
gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
};
|
||||
|
||||
regulator-usb-nrst {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_nrst";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&portb 5 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy1>;
|
||||
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txen-skew-ps = <0>;
|
||||
txc-skew-ps = <2600>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxc-skew-ps = <2000>;
|
||||
snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <10000 10000 10000>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
rxd0-skew-ps = <0>;
|
||||
rxd1-skew-ps = <0>;
|
||||
rxd2-skew-ps = <0>;
|
||||
rxd3-skew-ps = <0>;
|
||||
txen-skew-ps = <0>;
|
||||
txc-skew-ps = <2600>;
|
||||
rxdv-skew-ps = <0>;
|
||||
rxc-skew-ps = <2000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
&gpio0 { /* GPIO 0..29 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
&gpio1 { /* GPIO 30..57 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t82";
|
||||
reg = <0x68>;
|
||||
gpio: pca9557@1f {
|
||||
compatible = "nxp,pca9557";
|
||||
reg = <0x1f>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
temp: lm75@48 {
|
||||
compatible = "lm75";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
at24@50 {
|
||||
compatible = "atmel,24c01";
|
||||
pagesize = <8>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
i2cswitch@70 {
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x70>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
i2c@6 { /* Backplane EEPROM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c01";
|
||||
pagesize = <8>;
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7 { /* Power board EEPROM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c01";
|
||||
pagesize = <8>;
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
at24@50 {
|
||||
compatible = "atmel,24c02";
|
||||
pagesize = <8>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
flash0: n25q128@0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
n25q128@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128", "spi-flash";
|
||||
reg = <0>; /* chip select */
|
||||
spi-max-frequency = <50000000>;
|
||||
compatible = "n25q128";
|
||||
reg = <0>; /* chip select */
|
||||
spi-max-frequency = <100000000>;
|
||||
m25p,fast-read;
|
||||
page-size = <256>;
|
||||
block-size = <16>; /* 2^16, 64KB */
|
||||
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
cdns,tslch-ns = <4>;
|
||||
};
|
||||
|
||||
flash1: n25q00@1 {
|
||||
u-boot,dm-pre-reloc;
|
||||
n25q00@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q00", "spi-flash";
|
||||
reg = <1>; /* chip select */
|
||||
spi-max-frequency = <50000000>;
|
||||
compatible = "n25q00";
|
||||
reg = <1>; /* chip select */
|
||||
spi-max-frequency = <100000000>;
|
||||
m25p,fast-read;
|
||||
page-size = <256>;
|
||||
block-size = <16>; /* 2^16, 64KB */
|
||||
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
cdns,tchsh-ns = <4>;
|
||||
|
|
@ -103,13 +241,11 @@
|
|||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
};
|
||||
|
||||
qspi: spi@80203000 {
|
||||
compatible = "cadence,qspi";
|
||||
compatible = "cdns,qspi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80203000 0x100>,
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
#ifndef _SOCFPGA_BASE_ADDRS_H_
|
||||
#define _SOCFPGA_BASE_ADDRS_H_
|
||||
|
||||
#define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000
|
||||
#define SOCFPGA_STM_ADDRESS 0xfc000000
|
||||
#define SOCFPGA_DAP_ADDRESS 0xff000000
|
||||
#define SOCFPGA_EMAC0_ADDRESS 0xff700000
|
||||
|
|
|
|||
|
|
@ -6,6 +6,8 @@
|
|||
#ifndef _MISC_H_
|
||||
#define _MISC_H_
|
||||
|
||||
#include <asm/sections.h>
|
||||
|
||||
void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
|
||||
|
||||
struct bsel {
|
||||
|
|
@ -23,6 +25,13 @@ static inline void socfpga_fpga_add(void) {}
|
|||
|
||||
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
|
||||
void socfpga_sdram_remap_zero(void);
|
||||
static inline bool socfpga_is_booting_from_fpga(void)
|
||||
{
|
||||
if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) &&
|
||||
(__image_copy_start < (char *)SOCFPGA_STM_ADDRESS))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
|
||||
|
|
|
|||
|
|
@ -177,6 +177,8 @@ static void socfpga_nic301_slave_ns(void)
|
|||
|
||||
void socfpga_sdram_remap_zero(void)
|
||||
{
|
||||
u32 remap;
|
||||
|
||||
socfpga_nic301_slave_ns();
|
||||
|
||||
/*
|
||||
|
|
@ -187,7 +189,12 @@ void socfpga_sdram_remap_zero(void)
|
|||
setbits_le32(&scu_regs->sacr, 0xfff);
|
||||
|
||||
/* Configure the L2 controller to make SDRAM start at 0 */
|
||||
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
|
||||
remap = 0x1; /* remap.mpuzero */
|
||||
/* Keep fpga bridge enabled when running from FPGA onchip RAM */
|
||||
if (socfpga_is_booting_from_fpga())
|
||||
remap |= 0x8; /* remap.hps2fpga */
|
||||
writel(remap, &nic301_regs->remap);
|
||||
|
||||
writel(0x1, &pl310->pl310_addr_filter_start);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -92,8 +92,11 @@ void board_init_f(ulong dummy)
|
|||
|
||||
/* Put everything into reset but L4WD0. */
|
||||
socfpga_per_reset_all();
|
||||
/* Put FPGA bridges into reset too. */
|
||||
socfpga_bridges_reset(1);
|
||||
|
||||
if (!socfpga_is_booting_from_fpga()) {
|
||||
/* Put FPGA bridges into reset too. */
|
||||
socfpga_bridges_reset(1);
|
||||
}
|
||||
|
||||
socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
|
||||
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
|
||||
|
|
@ -163,5 +166,6 @@ void board_init_f(ulong dummy)
|
|||
hang();
|
||||
}
|
||||
|
||||
socfpga_bridges_reset(1);
|
||||
if (!socfpga_is_booting_from_fpga())
|
||||
socfpga_bridges_reset(1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -251,7 +251,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
|
|||
RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
|
||||
};
|
||||
|
||||
struct socfpga_sdram_io_config io_config = {
|
||||
static const struct socfpga_sdram_io_config io_config = {
|
||||
.delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
|
||||
.delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
|
||||
.delay_per_opa_tap = IO_DELAY_PER_OPA_TAP,
|
||||
|
|
@ -269,7 +269,7 @@ struct socfpga_sdram_io_config io_config = {
|
|||
.shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
|
||||
};
|
||||
|
||||
struct socfpga_sdram_misc_config misc_config = {
|
||||
static const struct socfpga_sdram_misc_config misc_config = {
|
||||
.afi_rate_ratio = AFI_RATE_RATIO,
|
||||
.calib_lfifo_offset = CALIB_LFIFO_OFFSET,
|
||||
.calib_vfifo_offset = CALIB_VFIFO_OFFSET,
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Cadence QSPI controller device tree bindings
|
|||
--------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "cadence,qspi".
|
||||
- compatible : should be "cdns,qspi-nor"
|
||||
- reg : 1.Physical base address and size of SPI registers map.
|
||||
2. Physical base address & size of NOR Flash.
|
||||
- clocks : Clock phandles (see clock bindings for details).
|
||||
|
|
|
|||
|
|
@ -180,6 +180,13 @@ static int gpio_dwapb_bind(struct udevice *dev)
|
|||
plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0);
|
||||
plat->name = fdt_stringlist_get(blob, node, "bank-name", 0,
|
||||
NULL);
|
||||
if (!plat->name) {
|
||||
/*
|
||||
* Fall back to node name. This means accessing pins
|
||||
* via bank name won't work.
|
||||
*/
|
||||
plat->name = fdt_get_name(blob, node, NULL);
|
||||
}
|
||||
|
||||
ret = device_bind(dev, dev->driver, plat->name,
|
||||
plat, -1, &subdev);
|
||||
|
|
|
|||
|
|
@ -329,7 +329,7 @@ static const struct dm_spi_ops cadence_spi_ops = {
|
|||
};
|
||||
|
||||
static const struct udevice_id cadence_spi_ids[] = {
|
||||
{ .compatible = "cadence,qspi" },
|
||||
{ .compatible = "cdns,qspi-nor" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue