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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Priyanka Jain
York Sun
parent
d6fdec211f
commit
4909b89ec7
16 changed files with 644 additions and 10 deletions
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@ -170,6 +170,42 @@ config ARCH_LS2080A
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imply DISTRO_DEFAULTS
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imply PANIC_HANG
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config ARCH_LX2160A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LSCH3
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select NXP_LSCH3_2
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select SYS_HAS_SERDES
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select SYS_FSL_SRDS_1
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select SYS_FSL_SRDS_2
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select SYS_NXP_SRDS_3
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select SYS_FSL_DDR
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_EC1
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select SYS_FSL_EC2
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select SYS_FSL_HAS_RGMII
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select SYS_FSL_HAS_SEC
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select SYS_FSL_HAS_CCN508
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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select SYS_I2C_MXC_I2C1
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select SYS_I2C_MXC_I2C2
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select SYS_I2C_MXC_I2C3
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select SYS_I2C_MXC_I2C4
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select SYS_I2C_MXC_I2C5
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select SYS_I2C_MXC_I2C6
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select SYS_I2C_MXC_I2C7
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select SYS_I2C_MXC_I2C8
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imply DISTRO_DEFAULTS
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imply PANIC_HANG
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imply SCSI
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imply SCSI_AHCI
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config FSL_LSCH2
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bool
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select SYS_FSL_HAS_CCI400
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@ -185,7 +221,7 @@ config NXP_LSCH3_2
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config FSL_MC_ENET
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bool "Management Complex network"
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depends on ARCH_LS2080A || ARCH_LS1088A
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depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
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default y
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select RESV_RAM
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help
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@ -202,6 +238,7 @@ config FSL_PCIE_COMPAT
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default "fsl,ls1046a-pcie" if ARCH_LS1046A
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default "fsl,ls2080a-pcie" if ARCH_LS2080A
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default "fsl,ls1088a-pcie" if ARCH_LS1088A
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default "fsl,lx2160a-pcie" if ARCH_LX2160A
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help
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This compatible is used to find pci controller node in Kernel DT
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to complete fixup.
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@ -300,6 +337,7 @@ config MAX_CPUS
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default 4 if ARCH_LS1046A
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default 16 if ARCH_LS2080A
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default 8 if ARCH_LS1088A
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default 16 if ARCH_LX2160A
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default 1
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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@ -342,6 +380,9 @@ config SYS_FSL_HAS_CCI400
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config SYS_FSL_HAS_CCN504
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bool
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config SYS_FSL_HAS_CCN508
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bool
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config SYS_FSL_HAS_DP_DDR
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bool
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@ -404,6 +445,7 @@ config SYS_FSL_DSPI_CLK_DIV
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config SYS_FSL_DUART_CLK_DIV
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int "DUART clock divider"
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default 1 if ARCH_LS1043A
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default 4 if ARCH_LX2160A
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default 2
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help
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This is the divider that is used to derive DUART clock from Platform
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@ -464,13 +506,15 @@ config RESV_RAM
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config SYS_FSL_EC1
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bool
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help
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Ethernet controller 1, this is connected to MAC3.
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Ethernet controller 1, this is connected to
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MAC17 for LX2160A or to MAC3 for other SoCs
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Provides DPAA2 capabilities
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config SYS_FSL_EC2
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bool
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help
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Ethernet controller 2, this is connected to MAC4.
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Ethernet controller 2, this is connected to
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MAC18 for LX2160A or to MAC4 for other SoCs
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Provides DPAA2 capabilities
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config SYS_FSL_ERRATUM_A008336
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@ -506,7 +550,7 @@ config SYS_FSL_HAS_RGMII
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config SYS_MC_RSV_MEM_ALIGN
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hex "Management Complex reserved memory alignment"
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depends on RESV_RAM
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default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
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default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
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help
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Reserved memory needs to be aligned for MC to use. Default value
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is 512MB.
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@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2016-2018 NXP
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# Copyright 2014-2015, Freescale Semiconductor
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obj-y += cpu.o
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@ -22,6 +22,10 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
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endif
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endif
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ifneq ($(CONFIG_ARCH_LX2160A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
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endif
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ifneq ($(CONFIG_ARCH_LS2080A),)
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obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
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endif
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@ -60,6 +60,9 @@ static struct cpu_type cpu_type_list[] = {
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CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
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CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
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CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
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CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
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CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
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CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
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};
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#define EARLY_PGTABLE_SIZE 0x5000
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@ -246,7 +249,7 @@ static struct mm_region final_map[] = {
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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#ifdef CONFIG_ARCH_LS2080A
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
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{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
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CONFIG_SYS_PCIE4_PHYS_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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@ -366,6 +369,10 @@ void cpu_name(char *name)
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
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strcpy(name, cpu_type_list[i].name);
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#ifdef CONFIG_ARCH_LX2160A
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if (IS_C_PROCESSOR(svr))
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strcat(name, "C");
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#endif
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if (IS_E_PROCESSOR(svr))
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strcat(name, "E");
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@ -1164,10 +1171,16 @@ void __efi_runtime reset_cpu(ulong addr)
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{
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u32 val;
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#ifdef CONFIG_ARCH_LX2160A
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val = in_le32(rstcr);
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val |= 0x01;
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out_le32(rstcr, val);
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#else
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/* Raise RESET_REQ_B */
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val = scfg_in32(rstcr);
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val |= 0x02;
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scfg_out32(rstcr, val);
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#endif
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}
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#ifdef CONFIG_EFI_LOADER
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@ -7,6 +7,7 @@ SoC overview
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5. LS1046A
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6. LS2088A
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7. LS2081A
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8. LX2160A
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LS1043A
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---------
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@ -271,3 +272,59 @@ Refer to LS2084A(LS2088A) section above for details.
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It has one more similar SoC personality
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1)LS2041A, few difference w.r.t. LS2081A:
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a) Four 64-bit ARM v8 Cortex-A72 CPUs
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LX2160A
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--------
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The QorIQ LX2160A processor is built in the 16FFC process on
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the Layerscape architecture combining sixteen ARM A72 processor
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cores with advanced, high-performance datapath acceleration and
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network, peripheral interfaces required for networking, wireless
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infrastructure, storage, and general-purpose embedded applications.
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LX2160A is compliant with the Layerscape Chassis Generation 3.2.
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The LX2160A SoC includes the following function and features:
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Sixteen 32-bit / 64-bit ARM v8 A72 CPUs
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Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”)
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Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC.
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Data path acceleration architecture (DPAA2)
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24 Serdes lanes at up to 25 GHz
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Ethernet interfaces
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Single WRIOP tile supporting 130Gbps using 18 MACs
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Support for 10G-SXGMII (aka USXGMII).
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Support for SGMII (and 1000Base-KX)
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Support for XFI (and 10GBase-KR)
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Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
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Support for XLAUI (and 40GBase-KR4) for 40G.
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Support for two RGMII parallel interfaces.
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Energy efficient Ethernet support (802.3az)
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IEEE 1588 support.
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High-speed peripheral interfaces
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Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV,
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Four PCIe Gen 4.0 4-lane controllers.
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Four serial ATA (SATA 3.0) controllers.
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Two USB 3.0 controllers with integrated PHY
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Two Enhanced secure digital host controllers
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Two Controller Area Network (CAN) modules
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Flexible Serial peripheral interface (FlexSPI) controller.
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Three Serial peripheral interface (SPI) controllers.
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Eight I2C Controllers.
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Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports.
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General Purpose IO (GPIO)
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Support for hardware virtualization and partitioning (ARM MMU-500)
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Support for GIC (ARM GIC-500)
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QorIQ platform Trust Architecture 3.0
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One Secure WatchDog timer and one Non-Secure Watchdog timer.
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ARM Generic Timer
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Two Flextimers
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Debug supporting run control, data acquisition, high-speed trace,
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performance/event monitoring
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Thermal Monitor Unit (TMU) with +/- 2C accuracy
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Support for Voltage ID (VID) for yield improvement
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LX2160A SoC has 2 more similar SoC personalities
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1)LX2120A, few difference w.r.t. LX2160A:
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a) Twelve 64-bit ARM v8 Cortex-A72 CPUs
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2)LX2080A, few difference w.r.t. LX2160A:
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a) Eight 64-bit ARM v8 Cortex-A72 CPUs
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@ -22,9 +22,18 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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#ifdef CONFIG_ARCH_LX2160A
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int xfi_dpmac[XFI14 + 1];
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int sgmii_dpmac[SGMII18 + 1];
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int a25gaui_dpmac[_25GE10 + 1];
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int xlaui_dpmac[_40GE2 + 1];
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int caui2_dpmac[_50GE2 + 1];
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int caui4_dpmac[_100GE2 + 1];
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#else
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int xfi_dpmac[XFI8 + 1];
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int sgmii_dpmac[SGMII16 + 1];
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#endif
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#endif
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__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
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{
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@ -146,6 +155,32 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
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else {
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serdes_prtcl_map[lane_prtcl] = 1;
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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#ifdef CONFIG_ARCH_LX2160A
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if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
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wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
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(int)lane_prtcl);
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if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
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wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
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(int)lane_prtcl);
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if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
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wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
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(int)lane_prtcl);
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if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
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wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
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(int)lane_prtcl);
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if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
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wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
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(int)lane_prtcl);
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if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
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wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
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(int)lane_prtcl);
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#else
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switch (lane_prtcl) {
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case QSGMII_A:
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case QSGMII_B:
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@ -166,6 +201,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
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(int)lane_prtcl);
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break;
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}
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#endif
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#endif
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}
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}
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@ -354,7 +354,7 @@ get_svr:
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ret
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#endif
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#ifdef CONFIG_SYS_FSL_HAS_CCN504
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#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508)
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hnf_pstate_poll:
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/* x0 has the desired status, return 0 for success, 1 for timeout
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* clobber x1, x2, x3, x4, x6, x7
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132
arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
Normal file
132
arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
Normal file
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@ -0,0 +1,132 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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struct serdes_config {
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u8 protocol;
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u8 lanes[SRDS_MAX_LANES];
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};
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static struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
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{0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } },
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{0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4,
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XFI3 } },
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{0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4,
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SGMII3 } },
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{0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1,
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PCIE1 } },
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{0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4,
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XFI3 } },
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{0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4,
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XFI3 } },
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{0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } },
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{0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4,
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PCIE1 } },
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{0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } },
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{0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } },
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{0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
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{0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1,
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_100GE1 } },
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{0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1,
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_100GE1 } },
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{0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } },
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{0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } },
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{0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } },
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{0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4,
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XFI3 } },
|
||||
{0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } },
|
||||
{0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1,
|
||||
_40GE1 } },
|
||||
{0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4,
|
||||
_25GE3 } },
|
||||
{0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct serdes_config serdes2_cfg_tbl[] = {
|
||||
/* SerDes 2 */
|
||||
{0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } },
|
||||
{0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
|
||||
{0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
|
||||
{0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
|
||||
{0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } },
|
||||
{0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13,
|
||||
XFI14 } },
|
||||
{0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13,
|
||||
XFI14 } },
|
||||
{0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } },
|
||||
{0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13,
|
||||
SGMII14} },
|
||||
{0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4,
|
||||
PCIE4 } },
|
||||
{0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13,
|
||||
SGMII14 } },
|
||||
{0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1,
|
||||
SATA2 } },
|
||||
{0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } },
|
||||
{0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13,
|
||||
SGMII14 } },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct serdes_config serdes3_cfg_tbl[] = {
|
||||
/* SerDes 3 */
|
||||
{0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } },
|
||||
{0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct serdes_config *serdes_cfg_tbl[] = {
|
||||
serdes1_cfg_tbl,
|
||||
serdes2_cfg_tbl,
|
||||
serdes3_cfg_tbl,
|
||||
};
|
||||
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
||||
{
|
||||
struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
ptr = serdes_cfg_tbl[serdes];
|
||||
while (ptr->protocol) {
|
||||
if (ptr->protocol == cfg)
|
||||
return ptr->lanes[lane];
|
||||
ptr++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
|
||||
{
|
||||
int i;
|
||||
struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
ptr = serdes_cfg_tbl[serdes];
|
||||
while (ptr->protocol) {
|
||||
if (ptr->protocol == prtcl)
|
||||
break;
|
||||
ptr++;
|
||||
}
|
||||
|
||||
if (!ptr->protocol)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (ptr->lanes[i] != NONE)
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
118
arch/arm/dts/fsl-lx2160a.dtsi
Normal file
118
arch/arm/dts/fsl-lx2160a.dtsi
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* NXP lx2160a SOC common device tree source
|
||||
*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
compatible = "fsl,lx2160a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0 0x80000000>;
|
||||
/* DRAM space - 1, size : 2 GB DRAM */
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
clockgen: clocking@1300000 {
|
||||
compatible = "fsl,ls2080a-clockgen";
|
||||
reg = <0 0x1300000 0 0xa0000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@6000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
|
||||
<0x0 0x06200000 0 0x100000>; /* GICR */
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <1 9 0x4>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
|
||||
<1 14 0x8>, /* Physical NS PPI, active-low */
|
||||
<1 11 0x8>, /* Virtual PPI, active-low */
|
||||
<1 10 0x8>; /* Hypervisor PPI, active-low */
|
||||
};
|
||||
|
||||
uart0: serial@21c0000 {
|
||||
compatible = "arm,pl011";
|
||||
reg = <0x0 0x21c0000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
uart1: serial@21d0000 {
|
||||
compatible = "arm,pl011";
|
||||
reg = <0x0 0x21d0000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
uart2: serial@21e0000 {
|
||||
compatible = "arm,pl011";
|
||||
reg = <0x0 0x21e0000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@21f0000 {
|
||||
compatible = "arm,pl011";
|
||||
reg = <0x0 0x21f0000 0x0 0x1000>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi0: dspi@2100000 {
|
||||
compatible = "fsl,vf610-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <0 26 0x4>; /* Level high type */
|
||||
num-cs = <6>;
|
||||
};
|
||||
|
||||
dspi1: dspi@2110000 {
|
||||
compatible = "fsl,vf610-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2110000 0x0 0x10000>;
|
||||
interrupts = <0 240 0x4>; /* Level high type */
|
||||
num-cs = <6>;
|
||||
};
|
||||
|
||||
dspi2: dspi@2120000 {
|
||||
compatible = "fsl,vf610-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2120000 0x0 0x10000>;
|
||||
interrupts = <0 241 0x4>; /* Level high type */
|
||||
num-cs = <6>;
|
||||
};
|
||||
|
||||
usb0: usb3@3100000 {
|
||||
compatible = "fsl,layerscape-dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <0 80 0x4>; /* Level high type */
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
usb1: usb3@3110000 {
|
||||
compatible = "fsl,layerscape-dwc3";
|
||||
reg = <0x0 0x3110000 0x0 0x10000>;
|
||||
interrupts = <0 81 0x4>; /* Level high type */
|
||||
dr_mode = "host";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2016-2018 NXP
|
||||
* Copyright 2015, Freescale Semiconductor
|
||||
*/
|
||||
|
||||
|
|
@ -176,6 +177,61 @@
|
|||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
||||
/* LX2160A Soc Support */
|
||||
#elif defined(CONFIG_ARCH_LX2160A)
|
||||
#define TZPC_BASE 0x02200000
|
||||
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_EARLY_INIT
|
||||
#define SRDS_MAX_LANES 8
|
||||
#ifndef L1_CACHE_BYTES
|
||||
#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
||||
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
|
||||
#define CONFIG_SYS_FSL_ESDHC_LE
|
||||
#define CONFIG_SYS_FSL_PEX_LUT_LE
|
||||
|
||||
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
#define GICR_BASE 0x06200000
|
||||
|
||||
/* SMMU Definitions */
|
||||
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
||||
|
||||
/* SFP */
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
||||
#define CONFIG_SYS_FSL_SFP_LE
|
||||
#define CONFIG_SYS_FSL_SRK_LE
|
||||
|
||||
/* Security Monitor */
|
||||
#define CONFIG_SYS_FSL_SEC_MON_LE
|
||||
|
||||
/* Secure Boot */
|
||||
#define CONFIG_ESBC_HDR_LS
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
||||
|
||||
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
||||
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
|
|
|
|||
|
|
@ -20,8 +20,12 @@ enum srds_prtcl {
|
|||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
PCIE5,
|
||||
PCIE6,
|
||||
SATA1,
|
||||
SATA2,
|
||||
SATA3,
|
||||
SATA4,
|
||||
XAUI1,
|
||||
XAUI2,
|
||||
XFI1,
|
||||
|
|
@ -32,6 +36,12 @@ enum srds_prtcl {
|
|||
XFI6,
|
||||
XFI7,
|
||||
XFI8,
|
||||
XFI9,
|
||||
XFI10,
|
||||
XFI11,
|
||||
XFI12,
|
||||
XFI13,
|
||||
XFI14,
|
||||
SGMII1,
|
||||
SGMII2,
|
||||
SGMII3,
|
||||
|
|
@ -48,10 +58,28 @@ enum srds_prtcl {
|
|||
SGMII14,
|
||||
SGMII15,
|
||||
SGMII16,
|
||||
SGMII17,
|
||||
SGMII18,
|
||||
QSGMII_A,
|
||||
QSGMII_B,
|
||||
QSGMII_C,
|
||||
QSGMII_D,
|
||||
_25GE1,
|
||||
_25GE2,
|
||||
_25GE3,
|
||||
_25GE4,
|
||||
_25GE5,
|
||||
_25GE6,
|
||||
_25GE7,
|
||||
_25GE8,
|
||||
_25GE9,
|
||||
_25GE10,
|
||||
_40GE1,
|
||||
_40GE2,
|
||||
_50GE1,
|
||||
_50GE2,
|
||||
_100GE1,
|
||||
_100GE2,
|
||||
SERDES_PRCTL_COUNT
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -15,7 +15,11 @@
|
|||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||
#ifdef CONFIG_ARCH_LX2160A
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
|
|
@ -324,6 +328,28 @@ struct ccsr_gur {
|
|||
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS1_REGSR 29
|
||||
#define FSL_CHASSIS3_SRDS2_REGSR 29
|
||||
#elif defined(CONFIG_ARCH_LX2160A)
|
||||
#define FSL_CHASSIS3_EC1_REGSR 27
|
||||
#define FSL_CHASSIS3_EC2_REGSR 27
|
||||
#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003
|
||||
#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0
|
||||
#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007
|
||||
#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000
|
||||
#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK
|
||||
#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT
|
||||
#define FSL_CHASSIS3_SRDS1_REGSR 29
|
||||
#define FSL_CHASSIS3_SRDS2_REGSR 29
|
||||
#define FSL_CHASSIS3_SRDS3_REGSR 29
|
||||
#elif defined(CONFIG_ARCH_LS1088A)
|
||||
#define FSL_CHASSIS3_EC1_REGSR 26
|
||||
#define FSL_CHASSIS3_EC2_REGSR 26
|
||||
|
|
|
|||
|
|
@ -96,12 +96,18 @@ enum boot_src get_boot_src(void);
|
|||
#define SVR_LS2044A 0x870930
|
||||
#define SVR_LS2081A 0x870918
|
||||
#define SVR_LS2041A 0x870914
|
||||
#define SVR_LX2160A 0x873601
|
||||
#define SVR_LX2120A 0x873621
|
||||
#define SVR_LX2080A 0x873603
|
||||
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
|
||||
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
|
||||
#ifdef CONFIG_ARCH_LX2160A
|
||||
#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
|
||||
#endif
|
||||
#define IS_SVR_REV(svr, maj, min) \
|
||||
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
|
||||
#define SVR_DEV(svr) ((svr) >> 8)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2015-2018 NXP
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
*/
|
||||
|
|
@ -69,11 +70,11 @@
|
|||
#define FSL_SDMMC_STREAM_ID 3
|
||||
#define FSL_SATA1_STREAM_ID 4
|
||||
|
||||
#if defined(CONFIG_ARCH_LS2080A)
|
||||
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
|
||||
#define FSL_SATA2_STREAM_ID 5
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_LS2080A)
|
||||
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
|
||||
#define FSL_DMA_STREAM_ID 6
|
||||
#elif defined(CONFIG_ARCH_LS1088A)
|
||||
#define FSL_DMA_STREAM_ID 5
|
||||
|
|
@ -82,6 +83,10 @@
|
|||
/* PCI - programmed in PEXn_LUT */
|
||||
#define FSL_PEX_STREAM_ID_START 7
|
||||
|
||||
#ifdef CONFIG_ARCH_LX2160A
|
||||
#define FSL_PEX_STREAM_ID_NUM (0x100)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_LS2080A)
|
||||
#define FSL_PEX_STREAM_ID_END 22
|
||||
#elif defined(CONFIG_ARCH_LS1088A)
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ config SYS_NUM_DDR_CTLRS
|
|||
ARCH_P4080 || \
|
||||
ARCH_P5020 || \
|
||||
ARCH_P5040 || \
|
||||
ARCH_LX2160A || \
|
||||
ARCH_T4160
|
||||
default 1
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright 2015-2018 NXP
|
||||
# Copyright 2014 Freescale Semiconductor, Inc.
|
||||
|
||||
obj-y += ldpaa_wriop.o
|
||||
obj-y += ldpaa_eth.o
|
||||
obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
|
||||
obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
|
||||
obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o
|
||||
|
|
|
|||
107
drivers/net/ldpaa_eth/lx2160a.c
Normal file
107
drivers/net/ldpaa_eth/lx2160a.c
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <phy.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
u32 dpmac_to_devdisr[] = {
|
||||
[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
|
||||
[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
|
||||
[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
|
||||
[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
|
||||
[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
|
||||
[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
|
||||
[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
|
||||
[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
|
||||
[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
|
||||
[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
|
||||
[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
|
||||
[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
|
||||
[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
|
||||
[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
|
||||
[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
|
||||
[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
|
||||
[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
|
||||
[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
|
||||
};
|
||||
|
||||
static int is_device_disabled(int dpmac_id)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
u32 devdisr2 = in_le32(&gur->devdisr2);
|
||||
|
||||
return dpmac_to_devdisr[dpmac_id] & devdisr2;
|
||||
}
|
||||
|
||||
void wriop_dpmac_disable(int dpmac_id)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
|
||||
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
|
||||
}
|
||||
|
||||
void wriop_dpmac_enable(int dpmac_id)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
|
||||
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
|
||||
}
|
||||
|
||||
phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
|
||||
{
|
||||
enum srds_prtcl;
|
||||
|
||||
if (is_device_disabled(dpmac_id + 1))
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
|
||||
if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
|
||||
return PHY_INTERFACE_MODE_SGMII;
|
||||
|
||||
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
|
||||
return PHY_INTERFACE_MODE_XGMII;
|
||||
|
||||
if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
|
||||
return PHY_INTERFACE_MODE_25G_AUI;
|
||||
|
||||
if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
|
||||
return PHY_INTERFACE_MODE_XLAUI;
|
||||
|
||||
if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
|
||||
return PHY_INTERFACE_MODE_CAUI2;
|
||||
|
||||
if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
|
||||
return PHY_INTERFACE_MODE_CAUI4;
|
||||
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_HAS_RGMII
|
||||
void fsl_rgmii_init(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 ec;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_EC1
|
||||
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
|
||||
& FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
|
||||
ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
|
||||
|
||||
if (!ec)
|
||||
wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_EC2
|
||||
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
|
||||
& FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
|
||||
ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
|
||||
|
||||
if (!ec)
|
||||
wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in a new issue