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ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
The L4SP and MMC clock precalculation is specific to Gen5, it is not needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper clock driver for Gen5, at which point this will go away completely. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
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@ -42,9 +42,11 @@ int cm_wait_for_fsm(void)
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int set_cpu_clk_info(void)
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{
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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/* Calculate the clock frequencies required for drivers */
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cm_get_l4_sp_clk_hz();
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cm_get_mmc_controller_clk_hz();
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#endif
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gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
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gd->bd->bi_dsp_freq = 0;
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