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Merge branch 'master' of git://git.denx.de/u-boot-sunxi

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This commit is contained in:
Tom Rini 2018-11-14 18:25:34 -05:00
commit 6f44333018
35 changed files with 1710 additions and 202 deletions
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1
arch/arm/Kconfig
View file

@ -848,6 +848,7 @@ config ARCH_SUNXI
imply CMD_UBI if NAND
imply DISTRO_DEFAULTS
imply FAT_WRITE
imply FIT
imply OF_LIBFDT_OVERLAY
imply PRE_CONSOLE_BUFFER
imply SPL_GPIO_SUPPORT

3
arch/arm/dts/Makefile
View file

@ -365,6 +365,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-tbs-a711.dts
dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h2-plus-bananapi-m2-zero.dtb \
sun8i-h2-plus-libretech-all-h3-cc.dtb \
sun8i-h2-plus-orangepi-r1.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
@ -395,6 +396,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-orangepi-lite2.dtb \
sun50i-h6-orangepi-one-plus.dtb \
sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
@ -405,6 +407,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-orangepi-win.dtb \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb \
sun50i-a64-pinebook.dtb \
sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \

168
arch/arm/dts/sun50i-a64-amarula-relic.dts
View file

@ -22,11 +22,11 @@
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */
};
};
@ -34,10 +34,34 @@
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_dcdc1>;
/*
* Schematic shows both dldo4 and eldo1 connected for vcc-io-wifi, but
* dldo4 connection shows DNP(Do Not Populate) and eldo1 connected with
* 0Ohm register to vcc-io-wifi so eldo1 is used.
*/
vqmmc-supply = <&reg_eldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&r_pio>;
interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */
interrupt-names = "host-wake";
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&reg_vcc3v3>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
@ -48,9 +72,138 @@
status = "okay";
};
&r_rsb {
status = "okay";
axp803: pmic@3a3 {
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};
#include "axp803.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "avdd-csi";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pl";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pll-avcc";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1040000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vdd-cpux";
};
/* DCDC3 is polyphased with DCDC2 */
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-sys";
};
&reg_dldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-hdmi-dsi-sensor";
};
&reg_dldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-mipi";
};
&reg_dldo3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "dovdd-csi";
};
&reg_dldo4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-io";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_eldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "cpvdd";
};
&reg_eldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi";
};
&reg_fldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-1v2-hsic";
};
/*
* The A64 chip cannot work without this regulator off, although
* it seems to be only driving the AR100 core.
* Maybe we don't still know well about CPUs domain.
*/
&reg_fldo2 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
@ -61,5 +214,6 @@
&usbphy {
usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
usb0_vbus-supply = <&reg_drivevbus>;
status = "okay";
};

34
arch/arm/dts/sun50i-a64-bananapi-m64.dts
View file

@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
@ -86,6 +97,10 @@
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
@ -103,6 +118,17 @@
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@ -151,7 +177,7 @@
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
@ -296,9 +322,13 @@
regulator-name = "vcc-rtc";
};
&simplefb_hdmi {
vcc-hdmi-supply = <&reg_dldo1>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

89
arch/arm/dts/sun50i-a64-nanopi-a64.dts
View file

@ -51,12 +51,44 @@
compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
blue {
label = "nanopi-a64:blue:status";
gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
};
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};
&de {
status = "okay";
};
&ehci0 {
@ -67,6 +99,26 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dcdc1>;
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
/* i2c1 connected with gpio headers like pine64, bananapi */
&i2c1 {
pinctrl-names = "default";
@ -78,6 +130,13 @@
bias-pull-up;
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@ -88,6 +147,24 @@
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dldo4>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
rtl8189etv: wifi@1 {
reg = <1>;
interrupt-parent = <&r_pio>;
interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
interrupt-names = "host-wake";
};
};
&ohci0 {
status = "okay";
};
@ -125,9 +202,9 @@
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
@ -195,9 +272,13 @@
regulator-name = "vcc-rtc";
};
&simplefb_hdmi {
vcc-hdmi-supply = <&reg_dldo1>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

103
arch/arm/dts/sun50i-a64-olinuxino.dts
View file

@ -51,6 +51,7 @@
compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -58,12 +59,74 @@
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
status = "okay";
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dcdc1>;
allwinner,tx-delay-ps = <600>;
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@ -92,6 +155,14 @@
};
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&r_rsb {
status = "okay";
@ -100,6 +171,7 @@
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};
@ -142,10 +214,14 @@
/* DCDC3 is polyphased with DCDC2 */
/*
* The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal
* 1.35V that the PMIC can drive.
*/
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-min-microvolt = <1360000>;
regulator-max-microvolt = <1360000>;
regulator-name = "vcc-ddr3";
};
@ -180,6 +256,11 @@
regulator-name = "vcc-wifi-io";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_eldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -214,8 +295,24 @@
regulator-name = "vcc-rtc";
};
&simplefb_hdmi {
vcc-hdmi-supply = <&reg_dldo1>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
status = "okay";
usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
};

179
arch/arm/dts/sun50i-a64-orangepi-win.dts
View file

@ -1,5 +1,6 @@
/*
* Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
* Copyright (C) 2017-2018 Samuel Holland <samuel@sholland.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -51,23 +52,127 @@
compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
status {
label = "orangepi:green:status";
gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
};
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>; /* PD14 */
status = "okay";
};
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */
status = "okay";
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_gmac_3v3>;
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
disable-wp;
bus-width = <4>;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_dldo2>;
vqmmc-supply = <&reg_dldo4>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&ohci0 {
status = "okay";
};
@ -89,9 +194,8 @@
#include "axp803.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "afvcc-csi";
};
@ -163,12 +267,23 @@
regulator-name = "vcc-wifi-io";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_eldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "cpvdd";
};
&reg_eldo3 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi";
};
&reg_fldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@ -191,13 +306,65 @@
regulator-name = "vcc-rtc";
};
&simplefb_hdmi {
vcc-hdmi-supply = <&reg_dldo1>;
};
&spi0 {
status = "okay";
spi-flash@0 {
compatible = "mxicy,mx25l1606e", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
m25p,fast-read;
status = "okay";
};
};
/* On debug connector */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
/* Bluetooth */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
/* On Pi-2 connector, RTS/CTS optional */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
/* On Pi-2 connector, RTS/CTS optional */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "disabled";
};
/* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
status = "disabled";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

13
arch/arm/dts/sun50i-a64-pine64-lts.dts Normal file
View file

@ -0,0 +1,13 @@
/*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*
* Copyright (c) 2018 ARM Ltd.
*/
#include "sun50i-a64-sopine-baseboard.dts"
/ {
model = "Pine64 LTS";
compatible = "pine64,pine64-lts", "allwinner,sun50i-r18",
"allwinner,sun50i-a64";
};

32
arch/arm/dts/sun50i-a64-pine64.dts
View file

@ -62,6 +62,21 @@
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
};
&de {
status = "okay";
};
&ehci0 {
@ -82,6 +97,17 @@
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@ -229,6 +255,10 @@
regulator-name = "vcc-rtc";
};
&simplefb_hdmi {
vcc-hdmi-supply = <&reg_dldo1>;
};
/* On Euler connector */
&spdif {
status = "disabled";
@ -237,7 +267,7 @@
/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

15
arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
*
*/
/* The ANX6345 eDP-bridge is on r_i2c */
&r_i2c {
anx6345: edp-bridge@38 {
compatible = "analogix,anx6345";
reg = <0x38>;
reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
status = "okay";
};
};

294
arch/arm/dts/sun50i-a64-pinebook.dts Normal file
View file

@ -0,0 +1,294 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
* Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
*
*/
/dts-v1/;
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Pinebook";
compatible = "pine64,pinebook", "allwinner,sun50i-a64";
aliases {
serial0 = &uart0;
ethernet0 = &rtl8723cs;
};
vdd_bl: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "bl-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
enable-active-high;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 50000 0>;
brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
default-brightness-level = <2>;
enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
power-supply = <&vdd_bl>;
};
chosen {
stdout-path = "serial0:115200n8";
framebuffer-lcd {
panel-supply = <&reg_dc1sw>;
dvdd25-supply = <&reg_dldo2>;
dvdd12-supply = <&reg_fldo1>;
};
};
gpio_keys {
compatible = "gpio-keys";
lid_switch {
label = "Lid Switch";
gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
linux,can-disable;
wakeup-source;
};
};
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};
&ehci0 {
phys = <&usbphy 0>;
phy-names = "usb";
status = "okay";
};
&ehci1 {
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_dldo4>;
vqmmc-supply = <&reg_eldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
rtl8723cs: wifi@1 {
reg = <1>;
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_eldo1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
mmc-hs200-1_8v;
status = "okay";
};
&ohci0 {
phys = <&usbphy 0>;
phy-names = "usb";
status = "okay";
};
&ohci1 {
status = "okay";
};
&pwm {
status = "okay";
};
&r_rsb {
status = "okay";
axp803: pmic@3a3 {
compatible = "x-powers,axp803";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
/* The ANX6345 eDP-bridge is on r_i2c */
&r_i2c {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&r_i2c_pl89_pins>;
status = "okay";
};
#include "axp803.dtsi"
&reg_aldo1 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc-csi";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pl";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pll-avcc";
};
&reg_dc1sw {
regulator-name = "vcc-lcd";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vdd-cpux";
};
/* DCDC3 is polyphased with DCDC2 */
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-sys";
};
&reg_dldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-hdmi";
};
&reg_dldo2 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc-edp";
};
&reg_dldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "avdd-csi";
};
&reg_dldo4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
&reg_eldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "cpvdd";
};
&reg_eldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vdd-1v8-csi";
};
&reg_fldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-1v2-hsic";
};
&reg_fldo2 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_ldo_io0 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-usb";
status = "okay";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&simplefb_hdmi {
vcc-hdmi-supply = <&reg_dldo1>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usb_otg {
dr_mode = "host";
};
&usbphy {
usb0_vbus-supply = <&reg_ldo_io0>;
usb1_vbus-supply = <&reg_ldo_io0>;
status = "okay";
};

32
arch/arm/dts/sun50i-a64-sopine-baseboard.dts
View file

@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
reg_vcc1v8: vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
@ -69,6 +80,10 @@
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
@ -86,6 +101,17 @@
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@ -134,9 +160,13 @@
regulator-name = "vcc-wifi";
};
&simplefb_hdmi {
vcc-hdmi-supply = <&reg_dldo1>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

15
arch/arm/dts/sun50i-a64-sopine.dtsi
View file

@ -45,6 +45,8 @@
#include "sun50i-a64.dtsi"
#include <dt-bindings/gpio/gpio.h>
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@ -52,6 +54,7 @@
non-removable;
disable-wp;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
@ -66,6 +69,18 @@
};
};
&spi0 {
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
#include "axp803.dtsi"
&reg_aldo2 {

312
arch/arm/dts/sun50i-a64.dtsi
View file

@ -43,9 +43,12 @@
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@ -57,17 +60,21 @@
#size-cells = <1>;
ranges;
/*
* The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
* However there is no support for this clock on A64 yet, so we depend
* on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
*/
simplefb_lcd: framebuffer-lcd {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "mixer0-lcd0";
clocks = <&ccu CLK_TCON0>,
<&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
<&display_clocks CLK_MIXER0>;
status = "disabled";
};
simplefb_hdmi: framebuffer-hdmi {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "mixer1-lcd1-hdmi";
clocks = <&display_clocks CLK_MIXER1>,
<&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
status = "disabled";
};
};
@ -81,6 +88,7 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@ -88,6 +96,7 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@ -95,6 +104,7 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@ -102,7 +112,20 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
next-level-cache = <&L2>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
de: display-engine {
compatible = "allwinner,sun50i-a64-display-engine";
allwinner,pipelines = <&mixer0>,
<&mixer1>;
status = "disabled";
};
osc24M: osc24M_clk {
@ -168,10 +191,93 @@
#size-cells = <1>;
ranges;
de2@1000000 {
compatible = "allwinner,sun50i-a64-de2";
reg = <0x1000000 0x400000>;
allwinner,sram = <&de2_sram 1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000000 0x400000>;
display_clocks: clock@0 {
compatible = "allwinner,sun50i-a64-de2-clk";
reg = <0x0 0x100000>;
clocks = <&ccu CLK_DE>,
<&ccu CLK_BUS_DE>;
clock-names = "mod",
"bus";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
mixer0: mixer@100000 {
compatible = "allwinner,sun50i-a64-de2-mixer-0";
reg = <0x100000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER0>,
<&display_clocks CLK_MIXER0>;
clock-names = "bus",
"mod";
resets = <&display_clocks RST_MIXER0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer0_out: port@1 {
reg = <1>;
mixer0_out_tcon0: endpoint {
remote-endpoint = <&tcon0_in_mixer0>;
};
};
};
};
mixer1: mixer@200000 {
compatible = "allwinner,sun50i-a64-de2-mixer-1";
reg = <0x200000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER1>,
<&display_clocks CLK_MIXER1>;
clock-names = "bus",
"mod";
resets = <&display_clocks RST_MIXER1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer1_out: port@1 {
reg = <1>;
mixer1_out_tcon1: endpoint {
remote-endpoint = <&tcon1_in_mixer1>;
};
};
};
};
};
syscon: syscon@1c00000 {
compatible = "allwinner,sun50i-a64-system-controller",
compatible = "allwinner,sun50i-a64-system-control",
"syscon";
reg = <0x01c00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_c: sram@18000 {
compatible = "mmio-sram";
reg = <0x00018000 0x28000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00018000 0x28000>;
de2_sram: sram-section@0 {
compatible = "allwinner,sun50i-a64-sram-c";
reg = <0x0000 0x28000>;
};
};
};
dma: dma-controller@1c02000 {
@ -185,6 +291,75 @@
#dma-cells = <1>;
};
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun50i-a64-tcon-lcd",
"allwinner,sun8i-a83t-tcon-lcd";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-pixel-clock";
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon0_in_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mixer0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
tcon1: lcd-controller@1c0d000 {
compatible = "allwinner,sun50i-a64-tcon-tv",
"allwinner,sun8i-a83t-tcon-tv";
reg = <0x01c0d000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON1>;
reset-names = "lcd";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon1_in: port@0 {
reg = <0>;
tcon1_in_mixer1: endpoint {
remote-endpoint = <&mixer1_out_tcon1>;
};
};
tcon1_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tcon1_out_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_in_tcon1>;
};
};
};
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
@ -227,6 +402,11 @@
#size-cells = <0>;
};
sid: eeprom@1c14000 {
compatible = "allwinner,sun50i-a64-sid";
reg = <0x1c14000 0x400>;
};
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
@ -356,7 +536,7 @@
};
mmc2_pins: mmc2-pins {
pins = "PC1", "PC5", "PC6", "PC8", "PC9",
pins = "PC5", "PC6", "PC8", "PC9",
"PC10","PC11", "PC12", "PC13",
"PC14", "PC15", "PC16";
function = "mmc2";
@ -364,6 +544,18 @@
bias-pull-up;
};
mmc2_ds_pin: mmc2-ds-pin {
pins = "PC1";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
pwm_pin: pwm_pin {
pins = "PD22";
function = "pwm";
};
rmii_pins: rmii_pins {
pins = "PD10", "PD11", "PD13", "PD14", "PD17",
"PD18", "PD19", "PD20", "PD22", "PD23";
@ -394,7 +586,7 @@
function = "spi1";
};
uart0_pins_a: uart0 {
uart0_pb_pins: uart0-pb-pins {
pins = "PB8", "PB9";
function = "uart0";
};
@ -474,15 +666,6 @@
status = "disabled";
};
pwm: pwm@1c21400 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
reg = <0x01c21400 0x8>;
clocks = <&osc24M>;
#pwm-cells = <3>;
status = "disabled";
};
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
@ -617,8 +800,6 @@
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
mdio: mdio {
compatible = "snps,dwmac-mdio";
@ -638,11 +819,69 @@
#interrupt-cells = <3>;
};
pwm: pwm@1c21400 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
reg = <0x01c21400 0x400>;
clocks = <&osc24M>;
pinctrl-names = "default";
pinctrl-0 = <&pwm_pin>;
#pwm-cells = <3>;
status = "disabled";
};
hdmi: hdmi@1ee0000 {
compatible = "allwinner,sun50i-a64-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee0000 0x10000>;
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu CLK_HDMI>;
clock-names = "iahb", "isfr", "tmds";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
hdmi_in_tcon1: endpoint {
remote-endpoint = <&tcon1_out_hdmi>;
};
};
hdmi_out: port@1 {
reg = <1>;
};
};
};
hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun50i-a64-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu 7>;
clock-names = "bus", "mod", "pll-0";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
#phy-cells = <0>;
};
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
clocks = <&osc32k>;
#clock-cells = <1>;
};
r_intc: interrupt-controller@1f00c00 {
@ -664,6 +903,29 @@
#reset-cells = <1>;
};
r_i2c: i2c@1f02400 {
compatible = "allwinner,sun50i-a64-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x01f02400 0x400>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_APB0_I2C>;
resets = <&r_ccu RST_APB0_I2C>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
r_pwm: pwm@1f03800 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
reg = <0x01f03800 0x400>;
clocks = <&osc24M>;
pinctrl-names = "default";
pinctrl-0 = <&r_pwm_pin>;
#pwm-cells = <3>;
status = "disabled";
};
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
@ -675,6 +937,16 @@
interrupt-controller;
#interrupt-cells = <3>;
r_i2c_pl89_pins: r-i2c-pl89-pins {
pins = "PL8", "PL9";
function = "s_i2c";
};
r_pwm_pin: pwm {
pins = "PL10";
function = "s_pwm";
};
r_rsb_pins: rsb {
pins = "PL0", "PL1";
function = "s_rsb";

12
arch/arm/dts/sun50i-h5-orangepi-pc2.dts
View file

@ -207,6 +207,18 @@
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;

2
arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts
View file

@ -105,7 +105,6 @@
};
};
/*
&spi0 {
status = "okay";
@ -117,7 +116,6 @@
spi-max-frequency = <40000000>;
};
};
*/
&ohci0 {
status = "okay";

11
arch/arm/dts/sun50i-h6-orangepi-lite2.dts Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2018 Jagan Teki <jagan@openedev.com>
*/
#include "sun50i-h6-orangepi.dtsi"
/ {
model = "OrangePi Lite2";
compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6";
};

140
arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
View file

@ -4,147 +4,9 @@
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
/dts-v1/;
#include "sun50i-h6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include "sun50i-h6-orangepi.dtsi"
/ {
model = "OrangePi One Plus";
compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&r_i2c {
status = "okay";
axp805: pmic@36 {
compatible = "x-powers,axp805", "x-powers,axp806";
reg = <0x36>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
x-powers,self-working-mode;
regulators {
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pl";
};
reg_aldo2: aldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-ac200";
};
reg_aldo3: aldo3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc25-dram";
};
reg_bldo1: bldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-bias-pll";
};
reg_bldo2: bldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-efuse-pcie-hdmi-io";
};
reg_bldo3: bldo3 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-dcxoio";
};
bldo4 {
/* unused */
};
reg_cldo1: cldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
reg_cldo2: cldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-1";
};
reg_cldo3: cldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-2";
};
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-cpu";
};
reg_dcdcc: dcdcc {
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-gpu";
};
reg_dcdcd: dcdcd {
regulator-always-on;
regulator-min-microvolt = <960000>;
regulator-max-microvolt = <960000>;
regulator-name = "vdd-sys";
};
reg_dcdce: dcdce {
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-dram";
};
sw {
/* unused */
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

150
arch/arm/dts/sun50i-h6-orangepi.dtsi Normal file
View file

@ -0,0 +1,150 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2018 Amarula Solutions
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
/dts-v1/;
#include "sun50i-h6.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "OrangePi One Plus";
compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&r_i2c {
status = "okay";
axp805: pmic@36 {
compatible = "x-powers,axp805", "x-powers,axp806";
reg = <0x36>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
x-powers,self-working-mode;
regulators {
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pl";
};
reg_aldo2: aldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-ac200";
};
reg_aldo3: aldo3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc25-dram";
};
reg_bldo1: bldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-bias-pll";
};
reg_bldo2: bldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-efuse-pcie-hdmi-io";
};
reg_bldo3: bldo3 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-dcxoio";
};
bldo4 {
/* unused */
};
reg_cldo1: cldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
reg_cldo2: cldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-1";
};
reg_cldo3: cldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-2";
};
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-cpu";
};
reg_dcdcc: dcdcc {
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-gpu";
};
reg_dcdcd: dcdcd {
regulator-always-on;
regulator-min-microvolt = <960000>;
regulator-max-microvolt = <960000>;
regulator-name = "vdd-sys";
};
reg_dcdce: dcdce {
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-dram";
};
sw {
/* unused */
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

121
arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts Normal file
View file

@ -0,0 +1,121 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*
* Based on sun8i-h3-bananapi-m2-plus.dts, which is:
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
*/
/dts-v1/;
#include "sun8i-h3.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Banana Pi BPI-M2-Zero";
compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pwr_led {
label = "bananapi-m2-zero:red:pwr";
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
default-state = "on";
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
sw4 {
label = "power";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
};
};
&ehci0 {
status = "okay";
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
/*
* On the production batch of this board the card detect GPIO is
* high active (card inserted), although on the early samples it's
* low active.
*/
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
interrupt-names = "host-wake";
};
};
&ohci0 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
/*
* There're two micro-USB connectors, one is power-only and another is
* OTG. The Vbus of these two connectors are connected together, so
* the external USB device will be powered just by the power input
* from the power-only USB port.
*/
status = "okay";
};

31
arch/arm/dts/sun8i-h3.dtsi
View file

@ -84,21 +84,30 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
};
};
@ -111,6 +120,28 @@
};
soc {
system-control@1c00000 {
compatible = "allwinner,sun8i-h3-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0x80000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun8i-h3-sram-c1",
"allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
mali: gpu@1c40000 {
compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;

2
arch/arm/dts/sunxi-h3-h5.dtsi
View file

@ -506,8 +506,6 @@
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
mdio: mdio {

1
arch/arm/include/asm/arch-sunxi/gpio.h
View file

@ -211,6 +211,7 @@ enum sunxi_gpio_number {
#define SUN8I_H3_GPL_R_TWI 2
#define SUN8I_A23_GPL_R_TWI 3
#define SUN8I_GPL_R_UART 2
#define SUN50I_GPL_R_TWI 2
#define SUN9I_GPN_R_RSB 3

6
arch/arm/include/asm/arch-sunxi/mmc.h
View file

@ -46,7 +46,9 @@ struct sunxi_mmc {
u32 cbda; /* 0x94 */
u32 res2[26];
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
u32 res3[64];
u32 res3[17];
u32 samp_dl;
u32 res4[46];
#endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */
};
@ -130,5 +132,7 @@ struct sunxi_mmc {
#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
#define SUNXI_MMC_COMMON_RESET (1 << 18)
#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
struct mmc *sunxi_mmc_init(int sdc_no);
#endif /* _SUNXI_MMC_H */

1
arch/arm/mach-sunxi/Kconfig
View file

@ -278,6 +278,7 @@ config MACH_SUN50I
select ARM64
select DM_I2C
select PHY_SUN4I_USB
select SUN6I_PRCM
select SUNXI_DE2
select SUNXI_GEN_SUN6I
select SUPPORT_SPL

4
arch/arm/mach-sunxi/clock_sun6i.c
View file

@ -149,7 +149,11 @@ void clock_set_pll3(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
#ifdef CONFIG_SUNXI_DE2
const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
#else
const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
#endif
if (clk == 0) {
clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);

10
board/sunxi/MAINTAINERS
View file

@ -149,6 +149,11 @@ S: Maintained
F: configs/Bananapi_m2m_defconfig
F: arch/arm/dts/sun8i-r16-bananapi-m2m.dts
BANANAPI M2 ZERO BOARD
M: Icenowy Zheng <icenowy@aosc.io>
S: Maintained
F: configs/bananapi_m2_zero_defconfig
BANANAPI M64
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
@ -330,6 +335,11 @@ S: Maintained
F: configs/A20-Olimex-SOM204-EVB_defconfig
F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
ORANGEPI LITE2 BOARD
M: Jagan Teki <jagan@openedev.com>
S: Maintained
F: configs/orangepi_lite2_defconfig
ORANGEPI ONE PLUS BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained

6
board/sunxi/board.c
View file

@ -168,10 +168,16 @@ void i2c_init_board(void)
#endif
#ifdef CONFIG_R_I2C_ENABLE
#ifdef CONFIG_MACH_SUN50I
clock_twi_onoff(5, 1);
sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
#else
clock_twi_onoff(5, 1);
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
#endif
#endif
}
#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)

13
configs/bananapi_m2_zero_defconfig Normal file
View file

@ -0,0 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-m2-zero"

12
configs/orangepi_lite2_defconfig Normal file
View file

@ -0,0 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-lite2"

19
configs/pine64-lts_defconfig Normal file
View file

@ -0,0 +1,19 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC0_CD_PIN=""
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-lts"
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

22
configs/pinebook_defconfig Normal file
View file

@ -0,0 +1,22 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_R_I2C_ENABLE=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook"
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_SUNXI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
# CONFIG_USB_GADGET is not set
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y

21
drivers/mmc/sunxi_mmc.c
View file

@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
{
unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
bool new_mode = false;
bool calibrate = false;
u32 val = 0;
if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
new_mode = true;
#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
calibrate = true;
#endif
/*
* The MMC clock has an extra /2 post-divider when operating in the new
* mode.
@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
val = CCM_MMC_CTRL_MODE_SEL_NEW;
setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
#endif
} else {
} else if (!calibrate) {
/*
* Use hardcoded delay values if controller doesn't support
* calibration
*/
val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
}
@ -228,6 +237,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
writel(rval, &priv->reg->clkcr);
#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
/* A64 supports calibration of delays on MMC controller and we
* have to set delay of zero before starting calibration.
* Allwinner BSP driver sets a delay only in the case of
* using HS400 which is not supported by mainline U-Boot or
* Linux at the moment
*/
writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
#endif
/* Re-enable Clock */
rval |= SUNXI_MMC_CLK_ENABLE;
writel(rval, &priv->reg->clkcr);

16
drivers/video/bridge/video-bridge-uclass.c
View file

@ -106,13 +106,19 @@ static int video_bridge_pre_probe(struct udevice *dev)
int video_bridge_set_active(struct udevice *dev, bool active)
{
struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
int ret = 0;
debug("%s: %d\n", __func__, active);
ret = dm_gpio_set_value(&uc_priv->sleep, !active);
if (ret)
return ret;
if (active) {
if (uc_priv->sleep.dev) {
ret = dm_gpio_set_value(&uc_priv->sleep, !active);
if (ret)
return ret;
}
if (!active)
return 0;
if (uc_priv->reset.dev) {
ret = dm_gpio_set_value(&uc_priv->reset, true);
if (ret)
return ret;

22
drivers/video/sunxi/lcdc.c
View file

@ -211,11 +211,17 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
int *clk_div, int *clk_double, bool is_composite)
{
int value, n, m, min_m, max_m, diff;
int value, n, m, min_m, max_m, diff, step;
int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
int best_double = 0;
bool use_mipi_pll = false;
#ifdef CONFIG_SUNXI_DE2
step = 6000;
#else
step = 3000;
#endif
if (tcon == 0) {
#if defined(CONFIG_VIDEO_LCD_IF_PARALLEL) || defined(CONFIG_SUNXI_DE2)
min_m = 6;
@ -237,10 +243,10 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
*/
for (m = min_m; m <= max_m; m++) {
#ifndef CONFIG_SUNXI_DE2
n = (m * dotclock) / 3000;
n = (m * dotclock) / step;
if ((n >= 9) && (n <= 127)) {
value = (3000 * n) / m;
value = (step * n) / m;
diff = dotclock - value;
if (diff < best_diff) {
best_diff = diff;
@ -256,9 +262,9 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
#endif
/* No double clock on DE2 */
n = (m * dotclock) / 6000;
n = (m * dotclock) / (step * 2);
if ((n >= 9) && (n <= 127)) {
value = (6000 * n) / m;
value = (step * 2 * n) / m;
diff = dotclock - value;
if (diff < best_diff) {
best_diff = diff;
@ -287,11 +293,11 @@ void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock,
} else
#endif
{
clock_set_pll3(best_n * 3000000);
debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
clock_set_pll3(best_n * step * 1000);
debug("dotclock: %dkHz = %dkHz: (%d * %dkHz * %d) / %d\n",
dotclock,
(best_double + 1) * clock_get_pll3() / best_m / 1000,
best_double + 1, best_n, best_m);
best_double + 1, step, best_n, best_m);
}
if (tcon == 0) {