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x86: Switch to use DM sysreset driver

Browse source 
This converts all x86 boards over to DM sysreset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This commit is contained in:
Bin Meng 2018-07-19 03:07:33 -07:00
parent 7bb6028768
commit b37b7b2063
31 changed files with 41 additions and 66 deletions
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2
arch/Kconfig
View file

@ -118,6 +118,8 @@ config X86
imply DM_SPI_FLASH
imply DM_USB
imply DM_VIDEO
imply SYSRESET
imply SYSRESET_X86
imply CMD_FPGA_LOADMK
imply CMD_GETTIME
imply CMD_IO

6
arch/x86/cpu/baytrail/valleyview.c
View file

@ -55,9 +55,3 @@ int arch_misc_init(void)
return 0;
}
void reset_cpu(ulong addr)
{
/* cold reset */
x86_full_reset();
}

6
arch/x86/cpu/braswell/braswell.c
View file

@ -27,9 +27,3 @@ int arch_misc_init(void)
return 0;
}
void reset_cpu(ulong addr)
{
/* cold reset */
x86_full_reset();
}

26
arch/x86/cpu/cpu.c
View file

@ -75,37 +75,11 @@ int x86_init_cache(void)
}
int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf("resetting ...\n");
/* wait 50 ms */
udelay(50000);
disable_interrupts();
reset_cpu(0);
/*NOTREACHED*/
return 0;
}
void flush_cache(unsigned long dummy1, unsigned long dummy2)
{
asm("wbinvd\n");
}
__weak void reset_cpu(ulong addr)
{
/* Do a hard reset through the chipset's reset control register */
outb(SYS_RST | RST_CPU, IO_PORT_RESET);
for (;;)
cpu_hlt();
}
void x86_full_reset(void)
{
outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
}
/* Define these functions to allow ehch-hcd to function */
void flush_dcache_range(unsigned long start, unsigned long stop)
{

7
arch/x86/cpu/ivybridge/early_me.c
View file

@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/pci.h>
#include <asm/cpu.h>
#include <asm/processor.h>
@ -138,17 +139,17 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(dev, 0);
reset_cpu(0);
sysreset_walk_halt(SYSRESET_COLD);
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(dev, 0);
x86_full_reset();
sysreset_walk_halt(SYSRESET_COLD);
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(dev, 1);
x86_full_reset();
sysreset_walk_halt(SYSRESET_COLD);
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:

3
arch/x86/cpu/ivybridge/sdram.c
View file

@ -18,6 +18,7 @@
#include <spi.h>
#include <spi_flash.h>
#include <syscon.h>
#include <sysreset.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/gpio.h>
@ -497,7 +498,7 @@ int dram_init(void)
/* If MRC data is not found we cannot continue S3 resume. */
if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
debug("Giving up in sdram_initialize: No MRC data\n");
reset_cpu(0);
sysreset_walk_halt(SYSRESET_COLD);
}
/* Pass console handler in pei_data */

6
arch/x86/cpu/qemu/qemu.c
View file

@ -156,12 +156,6 @@ int print_cpuinfo(void)
}
#endif
void reset_cpu(ulong addr)
{
/* cold reset */
x86_full_reset();
}
int arch_early_init_r(void)
{
qemu_chipset_init();

6
arch/x86/cpu/quark/quark.c
View file

@ -270,12 +270,6 @@ int print_cpuinfo(void)
return default_print_cpuinfo();
}
void reset_cpu(ulong addr)
{
/* cold reset */
x86_full_reset();
}
static void quark_pcie_init(void)
{
u32 val;

6
arch/x86/cpu/tangier/tangier.c
View file

@ -4,7 +4,6 @@
*/
#include <common.h>
#include <asm/scu.h>
#include <asm/u-boot-x86.h>
/*
@ -24,8 +23,3 @@ int print_cpuinfo(void)
{
return default_print_cpuinfo();
}
void reset_cpu(ulong addr)
{
scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
}

1
arch/x86/dts/bayleybay.dts
View file

@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"

1
arch/x86/dts/baytrail_som-db5800-som-6867.dts
View file

@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

1
arch/x86/dts/broadwell_som-6896.dts
View file

@ -2,6 +2,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"

1
arch/x86/dts/cherryhill.dts
View file

@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

1
arch/x86/dts/chromebook_link.dts
View file

@ -5,6 +5,7 @@
/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"

1
arch/x86/dts/chromebook_samus.dts
View file

@ -5,6 +5,7 @@
/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"

1
arch/x86/dts/chromebox_panther.dts
View file

@ -2,6 +2,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"

1
arch/x86/dts/conga-qeval20-qa3-e3845.dts
View file

@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

1
arch/x86/dts/cougarcanyon2.dts
View file

@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

1
arch/x86/dts/crownbay.dts
View file

@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

1
arch/x86/dts/dfi-bt700.dtsi
View file

@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-router/intel-irq.h>
#include "skeleton.dtsi"
#include "reset.dtsi"
#include "rtc.dtsi"
#include "tsc_timer.dtsi"

5
arch/x86/dts/edison.dts
View file

@ -85,4 +85,9 @@
compatible = "intel,scu-ipc";
reg = <0xff009000 0x1000>;
};
reset {
compatible = "intel,reset-tangier";
u-boot,dm-pre-reloc;
};
};

5
arch/x86/dts/efi-x86_app.dts
View file

@ -23,4 +23,9 @@
serial: serial {
compatible = "efi,uart";
};
reset {
compatible = "efi,reset";
u-boot,dm-pre-reloc;
};
};

1
arch/x86/dts/efi-x86_payload.dts
View file

@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

1
arch/x86/dts/galileo.dts
View file

@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-router/intel-irq.h>
/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

1
arch/x86/dts/minnowmax.dts
View file

@ -11,6 +11,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"

1
arch/x86/dts/qemu-x86_i440fx.dts
View file

@ -10,6 +10,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

1
arch/x86/dts/qemu-x86_q35.dts
View file

@ -20,6 +20,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"

6
arch/x86/dts/reset.dtsi Normal file
View file

@ -0,0 +1,6 @@
/ {
reset {
compatible = "x86,reset";
u-boot,dm-pre-reloc;
};
};

5
arch/x86/include/asm/processor.h
View file

@ -43,11 +43,6 @@ enum {
FULL_RST = 1 << 3, /* full power cycle */
};
/**
* x86_full_reset() - reset everything: perform a full power cycle
*/
void x86_full_reset(void);
static inline __attribute__((always_inline)) void cpu_hlt(void)
{
asm("hlt");

1
arch/x86/include/asm/u-boot-x86.h
View file

@ -40,7 +40,6 @@ int x86_cleanup_before_linux(void);
void x86_enable_caches(void);
void x86_disable_caches(void);
int x86_init_cache(void);
void reset_cpu(ulong addr);
ulong board_get_usable_ram_top(ulong total_size);
int default_print_cpuinfo(void);

1
configs/chromebook_link64_defconfig
View file

@ -4,6 +4,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200